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Merge branch 'for-linus' of git://oss.sgi.com/xfs/xfs
[linux/fpc-iii.git] / sound / pci / asihpi / hpi6000.c
blob12dab5e4892cd898b6cd53944a4bcfd585986527
1 /******************************************************************************
2
3 AudioScience HPI driver
4 Copyright (C) 1997-2010 AudioScience Inc. <support@audioscience.com>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of version 2 of the GNU General Public License as
8 published by the Free Software Foundation;
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18
19 Hardware Programming Interface (HPI) for AudioScience ASI6200 series adapters.
20 These PCI bus adapters are based on the TI C6711 DSP.
21
22 Exported functions:
23 void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
24
25 #defines
26 HIDE_PCI_ASSERTS to show the PCI asserts
27 PROFILE_DSP2 get profile data from DSP2 if present (instead of DSP 1)
28
29 (C) Copyright AudioScience Inc. 1998-2003
30 *******************************************************************************/
31 #define SOURCEFILE_NAME "hpi6000.c"
32
33 #include "hpi_internal.h"
34 #include "hpimsginit.h"
35 #include "hpidebug.h"
36 #include "hpi6000.h"
37 #include "hpidspcd.h"
38 #include "hpicmn.h"
39
40 #define HPI_HIF_BASE (0x00000200) /* start of C67xx internal RAM */
41 #define HPI_HIF_ADDR(member) \
42 (HPI_HIF_BASE + offsetof(struct hpi_hif_6000, member))
43 #define HPI_HIF_ERROR_MASK 0x4000
44
45 /* HPI6000 specific error codes */
46
47 #define HPI6000_ERROR_BASE 900
48 #define HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT 901
49 #define HPI6000_ERROR_MSG_RESP_SEND_MSG_ACK 902
50 #define HPI6000_ERROR_MSG_RESP_GET_RESP_ACK 903
51 #define HPI6000_ERROR_MSG_GET_ADR 904
52 #define HPI6000_ERROR_RESP_GET_ADR 905
53 #define HPI6000_ERROR_MSG_RESP_BLOCKWRITE32 906
54 #define HPI6000_ERROR_MSG_RESP_BLOCKREAD32 907
55 #define HPI6000_ERROR_MSG_INVALID_DSP_INDEX 908
56 #define HPI6000_ERROR_CONTROL_CACHE_PARAMS 909
57
58 #define HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT 911
59 #define HPI6000_ERROR_SEND_DATA_ACK 912
60 #define HPI6000_ERROR_SEND_DATA_ADR 913
61 #define HPI6000_ERROR_SEND_DATA_TIMEOUT 914
62 #define HPI6000_ERROR_SEND_DATA_CMD 915
63 #define HPI6000_ERROR_SEND_DATA_WRITE 916
64 #define HPI6000_ERROR_SEND_DATA_IDLECMD 917
65 #define HPI6000_ERROR_SEND_DATA_VERIFY 918
66
67 #define HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT 921
68 #define HPI6000_ERROR_GET_DATA_ACK 922
69 #define HPI6000_ERROR_GET_DATA_CMD 923
70 #define HPI6000_ERROR_GET_DATA_READ 924
71 #define HPI6000_ERROR_GET_DATA_IDLECMD 925
72
73 #define HPI6000_ERROR_CONTROL_CACHE_ADDRLEN 951
74 #define HPI6000_ERROR_CONTROL_CACHE_READ 952
75 #define HPI6000_ERROR_CONTROL_CACHE_FLUSH 953
76
77 #define HPI6000_ERROR_MSG_RESP_GETRESPCMD 961
78 #define HPI6000_ERROR_MSG_RESP_IDLECMD 962
79 #define HPI6000_ERROR_MSG_RESP_BLOCKVERIFY32 963
80
81 /* adapter init errors */
82 #define HPI6000_ERROR_UNHANDLED_SUBSYS_ID 930
83
84 /* can't access PCI2040 */
85 #define HPI6000_ERROR_INIT_PCI2040 931
86 /* can't access DSP HPI i/f */
87 #define HPI6000_ERROR_INIT_DSPHPI 932
88 /* can't access internal DSP memory */
89 #define HPI6000_ERROR_INIT_DSPINTMEM 933
90 /* can't access SDRAM - test#1 */
91 #define HPI6000_ERROR_INIT_SDRAM1 934
92 /* can't access SDRAM - test#2 */
93 #define HPI6000_ERROR_INIT_SDRAM2 935
94
95 #define HPI6000_ERROR_INIT_VERIFY 938
96
97 #define HPI6000_ERROR_INIT_NOACK 939
98
99 #define HPI6000_ERROR_INIT_PLDTEST1 941
100 #define HPI6000_ERROR_INIT_PLDTEST2 942
101
102 /* local defines */
103
104 #define HIDE_PCI_ASSERTS
105 #define PROFILE_DSP2
106
107 /* for PCI2040 i/f chip */
108 /* HPI CSR registers */
109 /* word offsets from CSR base */
110 /* use when io addresses defined as u32 * */
111
112 #define INTERRUPT_EVENT_SET 0
113 #define INTERRUPT_EVENT_CLEAR 1
114 #define INTERRUPT_MASK_SET 2
115 #define INTERRUPT_MASK_CLEAR 3
116 #define HPI_ERROR_REPORT 4
117 #define HPI_RESET 5
118 #define HPI_DATA_WIDTH 6
119
120 #define MAX_DSPS 2
121 /* HPI registers, spaced 8K bytes = 2K words apart */
122 #define DSP_SPACING 0x800
123
124 #define CONTROL 0x0000
125 #define ADDRESS 0x0200
126 #define DATA_AUTOINC 0x0400
127 #define DATA 0x0600
128
129 #define TIMEOUT 500000
130
131 struct dsp_obj {
132 __iomem u32 *prHPI_control;
133 __iomem u32 *prHPI_address;
134 __iomem u32 *prHPI_data;
135 __iomem u32 *prHPI_data_auto_inc;
136 char c_dsp_rev; /*A, B */
137 u32 control_cache_address_on_dsp;
138 u32 control_cache_length_on_dsp;
139 struct hpi_adapter_obj *pa_parent_adapter;
140 };
141
142 struct hpi_hw_obj {
143 __iomem u32 *dw2040_HPICSR;
144 __iomem u32 *dw2040_HPIDSP;
145
146 u16 num_dsp;
147 struct dsp_obj ado[MAX_DSPS];
148
149 u32 message_buffer_address_on_dsp;
150 u32 response_buffer_address_on_dsp;
151 u32 pCI2040HPI_error_count;
152
153 struct hpi_control_cache_single control_cache[HPI_NMIXER_CONTROLS];
154 struct hpi_control_cache *p_cache;
155 };
156
157 static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao,
158 u16 dsp_index, u32 hpi_address, u32 *source, u32 count);
159 static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao,
160 u16 dsp_index, u32 hpi_address, u32 *dest, u32 count);
161
162 static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
163 u32 *pos_error_code);
164 static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao,
165 u16 read_or_write);
166 #define H6READ 1
167 #define H6WRITE 0
168
169 static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao,
170 struct hpi_message *phm);
171 static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao,
172 u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr);
173
174 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
175 struct hpi_response *phr);
176
177 static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index,
178 u32 ack_value);
179
180 static short hpi6000_send_host_command(struct hpi_adapter_obj *pao,
181 u16 dsp_index, u32 host_cmd);
182
183 static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo);
184
185 static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index,
186 struct hpi_message *phm, struct hpi_response *phr);
187
188 static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index,
189 struct hpi_message *phm, struct hpi_response *phr);
190
191 static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data);
192
193 static u32 hpi_read_word(struct dsp_obj *pdo, u32 address);
194
195 static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
196 u32 length);
197
198 static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
199 u32 length);
200
201 static void subsys_create_adapter(struct hpi_message *phm,
202 struct hpi_response *phr);
203
204 static void subsys_delete_adapter(struct hpi_message *phm,
205 struct hpi_response *phr);
206
207 static void adapter_get_asserts(struct hpi_adapter_obj *pao,
208 struct hpi_message *phm, struct hpi_response *phr);
209
210 static short create_adapter_obj(struct hpi_adapter_obj *pao,
211 u32 *pos_error_code);
212
213 /* local globals */
214
215 static u16 gw_pci_read_asserts; /* used to count PCI2040 errors */
216 static u16 gw_pci_write_asserts; /* used to count PCI2040 errors */
217
218 static void subsys_message(struct hpi_message *phm, struct hpi_response *phr)
219 {
220
221 switch (phm->function) {
222 case HPI_SUBSYS_OPEN:
223 case HPI_SUBSYS_CLOSE:
224 case HPI_SUBSYS_GET_INFO:
225 case HPI_SUBSYS_DRIVER_UNLOAD:
226 case HPI_SUBSYS_DRIVER_LOAD:
227 case HPI_SUBSYS_FIND_ADAPTERS:
228 /* messages that should not get here */
229 phr->error = HPI_ERROR_UNIMPLEMENTED;
230 break;
231 case HPI_SUBSYS_CREATE_ADAPTER:
232 subsys_create_adapter(phm, phr);
233 break;
234 case HPI_SUBSYS_DELETE_ADAPTER:
235 subsys_delete_adapter(phm, phr);
236 break;
237 default:
238 phr->error = HPI_ERROR_INVALID_FUNC;
239 break;
240 }
241 }
242
243 static void control_message(struct hpi_adapter_obj *pao,
244 struct hpi_message *phm, struct hpi_response *phr)
245 {
246
247 switch (phm->function) {
248 case HPI_CONTROL_GET_STATE:
249 if (pao->has_control_cache) {
250 u16 err;
251 err = hpi6000_update_control_cache(pao, phm);
252
253 if (err) {
254 phr->error = err;
255 break;
256 }
257
258 if (hpi_check_control_cache(((struct hpi_hw_obj *)
259 pao->priv)->p_cache, phm,
260 phr))
261 break;
262 }
263 hw_message(pao, phm, phr);
264 break;
265 case HPI_CONTROL_GET_INFO:
266 hw_message(pao, phm, phr);
267 break;
268 case HPI_CONTROL_SET_STATE:
269 hw_message(pao, phm, phr);
270 hpi_sync_control_cache(((struct hpi_hw_obj *)pao->priv)->
271 p_cache, phm, phr);
272 break;
273 default:
274 phr->error = HPI_ERROR_INVALID_FUNC;
275 break;
276 }
277 }
278
279 static void adapter_message(struct hpi_adapter_obj *pao,
280 struct hpi_message *phm, struct hpi_response *phr)
281 {
282 switch (phm->function) {
283 case HPI_ADAPTER_GET_INFO:
284 hw_message(pao, phm, phr);
285 break;
286 case HPI_ADAPTER_GET_ASSERT:
287 adapter_get_asserts(pao, phm, phr);
288 break;
289 case HPI_ADAPTER_OPEN:
290 case HPI_ADAPTER_CLOSE:
291 case HPI_ADAPTER_TEST_ASSERT:
292 case HPI_ADAPTER_SELFTEST:
293 case HPI_ADAPTER_GET_MODE:
294 case HPI_ADAPTER_SET_MODE:
295 case HPI_ADAPTER_FIND_OBJECT:
296 case HPI_ADAPTER_GET_PROPERTY:
297 case HPI_ADAPTER_SET_PROPERTY:
298 case HPI_ADAPTER_ENUM_PROPERTY:
299 hw_message(pao, phm, phr);
300 break;
301 default:
302 phr->error = HPI_ERROR_INVALID_FUNC;
303 break;
304 }
305 }
306
307 static void outstream_message(struct hpi_adapter_obj *pao,
308 struct hpi_message *phm, struct hpi_response *phr)
309 {
310 switch (phm->function) {
311 case HPI_OSTREAM_HOSTBUFFER_ALLOC:
312 case HPI_OSTREAM_HOSTBUFFER_FREE:
313 /* Don't let these messages go to the HW function because
314 * they're called without allocating the spinlock.
315 * For the HPI6000 adapters the HW would return
316 * HPI_ERROR_INVALID_FUNC anyway.
317 */
318 phr->error = HPI_ERROR_INVALID_FUNC;
319 break;
320 default:
321 hw_message(pao, phm, phr);
322 return;
323 }
324 }
325
326 static void instream_message(struct hpi_adapter_obj *pao,
327 struct hpi_message *phm, struct hpi_response *phr)
328 {
329
330 switch (phm->function) {
331 case HPI_ISTREAM_HOSTBUFFER_ALLOC:
332 case HPI_ISTREAM_HOSTBUFFER_FREE:
333 /* Don't let these messages go to the HW function because
334 * they're called without allocating the spinlock.
335 * For the HPI6000 adapters the HW would return
336 * HPI_ERROR_INVALID_FUNC anyway.
337 */
338 phr->error = HPI_ERROR_INVALID_FUNC;
339 break;
340 default:
341 hw_message(pao, phm, phr);
342 return;
343 }
344 }
345
346 /************************************************************************/
347 /** HPI_6000()
348 * Entry point from HPIMAN
349 * All calls to the HPI start here
350 */
351 void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
352 {
353 struct hpi_adapter_obj *pao = NULL;
354
355 /* subsytem messages get executed by every HPI. */
356 /* All other messages are ignored unless the adapter index matches */
357 /* an adapter in the HPI */
358 HPI_DEBUG_LOG(DEBUG, "O %d,F %x\n", phm->object, phm->function);
359
360 /* if Dsp has crashed then do not communicate with it any more */
361 if (phm->object != HPI_OBJ_SUBSYSTEM) {
362 pao = hpi_find_adapter(phm->adapter_index);
363 if (!pao) {
364 HPI_DEBUG_LOG(DEBUG,
365 " %d,%d refused, for another HPI?\n",
366 phm->object, phm->function);
367 return;
368 }
369
370 if (pao->dsp_crashed >= 10) {
371 hpi_init_response(phr, phm->object, phm->function,
372 HPI_ERROR_DSP_HARDWARE);
373 HPI_DEBUG_LOG(DEBUG, " %d,%d dsp crashed.\n",
374 phm->object, phm->function);
375 return;
376 }
377 }
378 /* Init default response including the size field */
379 if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
380 hpi_init_response(phr, phm->object, phm->function,
381 HPI_ERROR_PROCESSING_MESSAGE);
382
383 switch (phm->type) {
384 case HPI_TYPE_MESSAGE:
385 switch (phm->object) {
386 case HPI_OBJ_SUBSYSTEM:
387 subsys_message(phm, phr);
388 break;
389
390 case HPI_OBJ_ADAPTER:
391 phr->size =
392 sizeof(struct hpi_response_header) +
393 sizeof(struct hpi_adapter_res);
394 adapter_message(pao, phm, phr);
395 break;
396
397 case HPI_OBJ_CONTROL:
398 control_message(pao, phm, phr);
399 break;
400
401 case HPI_OBJ_OSTREAM:
402 outstream_message(pao, phm, phr);
403 break;
404
405 case HPI_OBJ_ISTREAM:
406 instream_message(pao, phm, phr);
407 break;
408
409 default:
410 hw_message(pao, phm, phr);
411 break;
412 }
413 break;
414
415 default:
416 phr->error = HPI_ERROR_INVALID_TYPE;
417 break;
418 }
419 }
420
421 /************************************************************************/
422 /* SUBSYSTEM */
423
424 /* create an adapter object and initialise it based on resource information
425 * passed in in the message
426 * NOTE - you cannot use this function AND the FindAdapters function at the
427 * same time, the application must use only one of them to get the adapters
428 */
429 static void subsys_create_adapter(struct hpi_message *phm,
430 struct hpi_response *phr)
431 {
432 /* create temp adapter obj, because we don't know what index yet */
433 struct hpi_adapter_obj ao;
434 struct hpi_adapter_obj *pao;
435 u32 os_error_code;
436 short error = 0;
437 u32 dsp_index = 0;
438
439 HPI_DEBUG_LOG(VERBOSE, "subsys_create_adapter\n");
440
441 memset(&ao, 0, sizeof(ao));
442
443 /* this HPI only creates adapters for TI/PCI2040 based devices */
444 if (phm->u.s.resource.bus_type != HPI_BUS_PCI)
445 return;
446 if (phm->u.s.resource.r.pci->vendor_id != HPI_PCI_VENDOR_ID_TI)
447 return;
448 if (phm->u.s.resource.r.pci->device_id != HPI_PCI_DEV_ID_PCI2040)
449 return;
450
451 ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
452 if (!ao.priv) {
453 HPI_DEBUG_LOG(ERROR, "cant get mem for adapter object\n");
454 phr->error = HPI_ERROR_MEMORY_ALLOC;
455 return;
456 }
457
458 /* create the adapter object based on the resource information */
459 /*? memcpy(&ao.Pci,&phm->u.s.Resource.r.Pci,sizeof(ao.Pci)); */
460 ao.pci = *phm->u.s.resource.r.pci;
461
462 error = create_adapter_obj(&ao, &os_error_code);
463 if (!error)
464 error = hpi_add_adapter(&ao);
465 if (error) {
466 phr->u.s.data = os_error_code;
467 kfree(ao.priv);
468 phr->error = error;
469 return;
470 }
471 /* need to update paParentAdapter */
472 pao = hpi_find_adapter(ao.index);
473 if (!pao) {
474 /* We just added this adapter, why can't we find it!? */
475 HPI_DEBUG_LOG(ERROR, "lost adapter after boot\n");
476 phr->error = 950;
477 return;
478 }
479
480 for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) {
481 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
482 phw->ado[dsp_index].pa_parent_adapter = pao;
483 }
484
485 phr->u.s.aw_adapter_list[ao.index] = ao.adapter_type;
486 phr->u.s.adapter_index = ao.index;
487 phr->u.s.num_adapters++;
488 phr->error = 0;
489 }
490
491 static void subsys_delete_adapter(struct hpi_message *phm,
492 struct hpi_response *phr)
493 {
494 struct hpi_adapter_obj *pao = NULL;
495 struct hpi_hw_obj *phw;
496
497 pao = hpi_find_adapter(phm->adapter_index);
498 if (!pao)
499 return;
500
501 phw = (struct hpi_hw_obj *)pao->priv;
502
503 if (pao->has_control_cache)
504 hpi_free_control_cache(phw->p_cache);
505
506 hpi_delete_adapter(pao);
507 kfree(phw);
508
509 phr->error = 0;
510 }
511
512 /* this routine is called from SubSysFindAdapter and SubSysCreateAdapter */
513 static short create_adapter_obj(struct hpi_adapter_obj *pao,
514 u32 *pos_error_code)
515 {
516 short boot_error = 0;
517 u32 dsp_index = 0;
518 u32 control_cache_size = 0;
519 u32 control_cache_count = 0;
520 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
521
522 /* init error reporting */
523 pao->dsp_crashed = 0;
524
525 /* The PCI2040 has the following address map */
526 /* BAR0 - 4K = HPI control and status registers on PCI2040 (HPI CSR) */
527 /* BAR1 - 32K = HPI registers on DSP */
528 phw->dw2040_HPICSR = pao->pci.ap_mem_base[0];
529 phw->dw2040_HPIDSP = pao->pci.ap_mem_base[1];
530 HPI_DEBUG_LOG(VERBOSE, "csr %p, dsp %p\n", phw->dw2040_HPICSR,
531 phw->dw2040_HPIDSP);
532
533 /* set addresses for the possible DSP HPI interfaces */
534 for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) {
535 phw->ado[dsp_index].prHPI_control =
536 phw->dw2040_HPIDSP + (CONTROL +
537 DSP_SPACING * dsp_index);
538
539 phw->ado[dsp_index].prHPI_address =
540 phw->dw2040_HPIDSP + (ADDRESS +
541 DSP_SPACING * dsp_index);
542 phw->ado[dsp_index].prHPI_data =
543 phw->dw2040_HPIDSP + (DATA + DSP_SPACING * dsp_index);
544
545 phw->ado[dsp_index].prHPI_data_auto_inc =
546 phw->dw2040_HPIDSP + (DATA_AUTOINC +
547 DSP_SPACING * dsp_index);
548
549 HPI_DEBUG_LOG(VERBOSE, "ctl %p, adr %p, dat %p, dat++ %p\n",
550 phw->ado[dsp_index].prHPI_control,
551 phw->ado[dsp_index].prHPI_address,
552 phw->ado[dsp_index].prHPI_data,
553 phw->ado[dsp_index].prHPI_data_auto_inc);
554
555 phw->ado[dsp_index].pa_parent_adapter = pao;
556 }
557
558 phw->pCI2040HPI_error_count = 0;
559 pao->has_control_cache = 0;
560
561 /* Set the default number of DSPs on this card */
562 /* This is (conditionally) adjusted after bootloading */
563 /* of the first DSP in the bootload section. */
564 phw->num_dsp = 1;
565
566 boot_error = hpi6000_adapter_boot_load_dsp(pao, pos_error_code);
567 if (boot_error)
568 return boot_error;
569
570 HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
571
572 phw->message_buffer_address_on_dsp = 0L;
573 phw->response_buffer_address_on_dsp = 0L;
574
575 /* get info about the adapter by asking the adapter */
576 /* send a HPI_ADAPTER_GET_INFO message */
577 {
578 struct hpi_message hM;
579 struct hpi_response hR0; /* response from DSP 0 */
580 struct hpi_response hR1; /* response from DSP 1 */
581 u16 error = 0;
582
583 HPI_DEBUG_LOG(VERBOSE, "send ADAPTER_GET_INFO\n");
584 memset(&hM, 0, sizeof(hM));
585 hM.type = HPI_TYPE_MESSAGE;
586 hM.size = sizeof(struct hpi_message);
587 hM.object = HPI_OBJ_ADAPTER;
588 hM.function = HPI_ADAPTER_GET_INFO;
589 hM.adapter_index = 0;
590 memset(&hR0, 0, sizeof(hR0));
591 memset(&hR1, 0, sizeof(hR1));
592 hR0.size = sizeof(hR0);
593 hR1.size = sizeof(hR1);
594
595 error = hpi6000_message_response_sequence(pao, 0, &hM, &hR0);
596 if (hR0.error) {
597 HPI_DEBUG_LOG(DEBUG, "message error %d\n", hR0.error);
598 return hR0.error;
599 }
600 if (phw->num_dsp == 2) {
601 error = hpi6000_message_response_sequence(pao, 1, &hM,
602 &hR1);
603 if (error)
604 return error;
605 }
606 pao->adapter_type = hR0.u.a.adapter_type;
607 pao->index = hR0.u.a.adapter_index;
608 }
609
610 memset(&phw->control_cache[0], 0,
611 sizeof(struct hpi_control_cache_single) *
612 HPI_NMIXER_CONTROLS);
613 /* Read the control cache length to figure out if it is turned on */
614 control_cache_size =
615 hpi_read_word(&phw->ado[0],
616 HPI_HIF_ADDR(control_cache_size_in_bytes));
617 if (control_cache_size) {
618 control_cache_count =
619 hpi_read_word(&phw->ado[0],
620 HPI_HIF_ADDR(control_cache_count));
621 pao->has_control_cache = 1;
622
623 phw->p_cache =
624 hpi_alloc_control_cache(control_cache_count,
625 control_cache_size, (struct hpi_control_cache_info *)
626 &phw->control_cache[0]
627 );
628 } else
629 pao->has_control_cache = 0;
630
631 HPI_DEBUG_LOG(DEBUG, "get adapter info ASI%04X index %d\n",
632 pao->adapter_type, pao->index);
633 pao->open = 0; /* upon creation the adapter is closed */
634 return 0;
635 }
636
637 /************************************************************************/
638 /* ADAPTER */
639
640 static void adapter_get_asserts(struct hpi_adapter_obj *pao,
641 struct hpi_message *phm, struct hpi_response *phr)
642 {
643 #ifndef HIDE_PCI_ASSERTS
644 /* if we have PCI2040 asserts then collect them */
645 if ((gw_pci_read_asserts > 0) || (gw_pci_write_asserts > 0)) {
646 phr->u.a.serial_number =
647 gw_pci_read_asserts * 100 + gw_pci_write_asserts;
648 phr->u.a.adapter_index = 1; /* assert count */
649 phr->u.a.adapter_type = -1; /* "dsp index" */
650 strcpy(phr->u.a.sz_adapter_assert, "PCI2040 error");
651 gw_pci_read_asserts = 0;
652 gw_pci_write_asserts = 0;
653 phr->error = 0;
654 } else
655 #endif
656 hw_message(pao, phm, phr); /*get DSP asserts */
657
658 return;
659 }
660
661 /************************************************************************/
662 /* LOW-LEVEL */
663
664 static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
665 u32 *pos_error_code)
666 {
667 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
668 short error;
669 u32 timeout;
670 u32 read = 0;
671 u32 i = 0;
672 u32 data = 0;
673 u32 j = 0;
674 u32 test_addr = 0x80000000;
675 u32 test_data = 0x00000001;
676 u32 dw2040_reset = 0;
677 u32 dsp_index = 0;
678 u32 endian = 0;
679 u32 adapter_info = 0;
680 u32 delay = 0;
681
682 struct dsp_code dsp_code;
683 u16 boot_load_family = 0;
684
685 /* NOTE don't use wAdapterType in this routine. It is not setup yet */
686
687 switch (pao->pci.subsys_device_id) {
688 case 0x5100:
689 case 0x5110: /* ASI5100 revB or higher with C6711D */
690 case 0x6100:
691 case 0x6200:
692 boot_load_family = HPI_ADAPTER_FAMILY_ASI(0x6200);
693 break;
694 default:
695 return HPI6000_ERROR_UNHANDLED_SUBSYS_ID;
696 }
697
698 /* reset all DSPs, indicate two DSPs are present
699 * set RST3-=1 to disconnect HAD8 to set DSP in little endian mode
700 */
701 endian = 0;
702 dw2040_reset = 0x0003000F;
703 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
704
705 /* read back register to make sure PCI2040 chip is functioning
706 * note that bits 4..15 are read-only and so should always return zero,
707 * even though we wrote 1 to them
708 */
709 for (i = 0; i < 1000; i++)
710 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
711 if (delay != dw2040_reset) {
712 HPI_DEBUG_LOG(ERROR, "INIT_PCI2040 %x %x\n", dw2040_reset,
713 delay);
714 return HPI6000_ERROR_INIT_PCI2040;
715 }
716
717 /* Indicate that DSP#0,1 is a C6X */
718 iowrite32(0x00000003, phw->dw2040_HPICSR + HPI_DATA_WIDTH);
719 /* set Bit30 and 29 - which will prevent Target aborts from being
720 * issued upon HPI or GP error
721 */
722 iowrite32(0x60000000, phw->dw2040_HPICSR + INTERRUPT_MASK_SET);
723
724 /* isolate DSP HAD8 line from PCI2040 so that
725 * Little endian can be set by pullup
726 */
727 dw2040_reset = dw2040_reset & (~(endian << 3));
728 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
729
730 phw->ado[0].c_dsp_rev = 'B'; /* revB */
731 phw->ado[1].c_dsp_rev = 'B'; /* revB */
732
733 /*Take both DSPs out of reset, setting HAD8 to the correct Endian */
734 dw2040_reset = dw2040_reset & (~0x00000001); /* start DSP 0 */
735 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
736 dw2040_reset = dw2040_reset & (~0x00000002); /* start DSP 1 */
737 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
738
739 /* set HAD8 back to PCI2040, now that DSP set to little endian mode */
740 dw2040_reset = dw2040_reset & (~0x00000008);
741 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
742 /*delay to allow DSP to get going */
743 for (i = 0; i < 100; i++)
744 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
745
746 /* loop through all DSPs, downloading DSP code */
747 for (dsp_index = 0; dsp_index < phw->num_dsp; dsp_index++) {
748 struct dsp_obj *pdo = &phw->ado[dsp_index];
749
750 /* configure DSP so that we download code into the SRAM */
751 /* set control reg for little endian, HWOB=1 */
752 iowrite32(0x00010001, pdo->prHPI_control);
753
754 /* test access to the HPI address register (HPIA) */
755 test_data = 0x00000001;
756 for (j = 0; j < 32; j++) {
757 iowrite32(test_data, pdo->prHPI_address);
758 data = ioread32(pdo->prHPI_address);
759 if (data != test_data) {
760 HPI_DEBUG_LOG(ERROR, "INIT_DSPHPI %x %x %x\n",
761 test_data, data, dsp_index);
762 return HPI6000_ERROR_INIT_DSPHPI;
763 }
764 test_data = test_data << 1;
765 }
766
767 /* if C6713 the setup PLL to generate 225MHz from 25MHz.
768 * Since the PLLDIV1 read is sometimes wrong, even on a C6713,
769 * we're going to do this unconditionally
770 */
771 /* PLLDIV1 should have a value of 8000 after reset */
772 /*
773 if (HpiReadWord(pdo,0x01B7C118) == 0x8000)
774 */
775 {
776 /* C6713 datasheet says we cannot program PLL from HPI,
777 * and indeed if we try to set the PLL multiply from the
778 * HPI, the PLL does not seem to lock,
779 * so we enable the PLL and use the default of x 7
780 */
781 /* bypass PLL */
782 hpi_write_word(pdo, 0x01B7C100, 0x0000);
783 for (i = 0; i < 100; i++)
784 delay = ioread32(phw->dw2040_HPICSR +
785 HPI_RESET);
786
787 /* ** use default of PLL x7 ** */
788 /* EMIF = 225/3=75MHz */
789 hpi_write_word(pdo, 0x01B7C120, 0x8002);
790 /* peri = 225/2 */
791 hpi_write_word(pdo, 0x01B7C11C, 0x8001);
792 /* cpu = 225/1 */
793 hpi_write_word(pdo, 0x01B7C118, 0x8000);
794 /* ~200us delay */
795 for (i = 0; i < 2000; i++)
796 delay = ioread32(phw->dw2040_HPICSR +
797 HPI_RESET);
798 /* PLL not bypassed */
799 hpi_write_word(pdo, 0x01B7C100, 0x0001);
800 /* ~200us delay */
801 for (i = 0; i < 2000; i++)
802 delay = ioread32(phw->dw2040_HPICSR +
803 HPI_RESET);
804 }
805
806 /* test r/w to internal DSP memory
807 * C6711 has L2 cache mapped to 0x0 when reset
808 *
809 * revB - because of bug 3.0.1 last HPI read
810 * (before HPI address issued) must be non-autoinc
811 */
812 /* test each bit in the 32bit word */
813 for (i = 0; i < 100; i++) {
814 test_addr = 0x00000000;
815 test_data = 0x00000001;
816 for (j = 0; j < 32; j++) {
817 hpi_write_word(pdo, test_addr + i, test_data);
818 data = hpi_read_word(pdo, test_addr + i);
819 if (data != test_data) {
820 HPI_DEBUG_LOG(ERROR,
821 "DSP mem %x %x %x %x\n",
822 test_addr + i, test_data,
823 data, dsp_index);
824
825 return HPI6000_ERROR_INIT_DSPINTMEM;
826 }
827 test_data = test_data << 1;
828 }
829 }
830
831 /* memory map of ASI6200
832 00000000-0000FFFF 16Kx32 internal program
833 01800000-019FFFFF Internal peripheral
834 80000000-807FFFFF CE0 2Mx32 SDRAM running @ 100MHz
835 90000000-9000FFFF CE1 Async peripherals:
836
837 EMIF config
838 ------------
839 Global EMIF control
840 0 -
841 1 -
842 2 -
843 3 CLK2EN = 1 CLKOUT2 enabled
844 4 CLK1EN = 0 CLKOUT1 disabled
845 5 EKEN = 1 <--!! C6713 specific, enables ECLKOUT
846 6 -
847 7 NOHOLD = 1 external HOLD disabled
848 8 HOLDA = 0 HOLDA output is low
849 9 HOLD = 0 HOLD input is low
850 10 ARDY = 1 ARDY input is high
851 11 BUSREQ = 0 BUSREQ output is low
852 12,13 Reserved = 1
853 */
854 hpi_write_word(pdo, 0x01800000, 0x34A8);
855
856 /* EMIF CE0 setup - 2Mx32 Sync DRAM
857 31..28 Wr setup
858 27..22 Wr strobe
859 21..20 Wr hold
860 19..16 Rd setup
861 15..14 -
862 13..8 Rd strobe
863 7..4 MTYPE 0011 Sync DRAM 32bits
864 3 Wr hold MSB
865 2..0 Rd hold
866 */
867 hpi_write_word(pdo, 0x01800008, 0x00000030);
868
869 /* EMIF SDRAM Extension
870 31-21 0
871 20 WR2RD = 0
872 19-18 WR2DEAC = 1
873 17 WR2WR = 0
874 16-15 R2WDQM = 2
875 14-12 RD2WR = 4
876 11-10 RD2DEAC = 1
877 9 RD2RD = 1
878 8-7 THZP = 10b
879 6-5 TWR = 2-1 = 01b (tWR = 10ns)
880 4 TRRD = 0b = 2 ECLK (tRRD = 14ns)
881 3-1 TRAS = 5-1 = 100b (Tras=42ns = 5 ECLK)
882 1 CAS latency = 3 ECLK
883 (for Micron 2M32-7 operating at 100Mhz)
884 */
885
886 /* need to use this else DSP code crashes */
887 hpi_write_word(pdo, 0x01800020, 0x001BDF29);
888
889 /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank)
890 31 - -
891 30 SDBSZ 1 4 bank
892 29..28 SDRSZ 00 11 row address pins
893 27..26 SDCSZ 01 8 column address pins
894 25 RFEN 1 refersh enabled
895 24 INIT 1 init SDRAM
896 23..20 TRCD 0001
897 19..16 TRP 0001
898 15..12 TRC 0110
899 11..0 - -
900 */
901 /* need to use this else DSP code crashes */
902 hpi_write_word(pdo, 0x01800018, 0x47117000);
903
904 /* EMIF SDRAM Refresh Timing */
905 hpi_write_word(pdo, 0x0180001C, 0x00000410);
906
907 /*MIF CE1 setup - Async peripherals
908 @100MHz bus speed, each cycle is 10ns,
909 31..28 Wr setup = 1
910 27..22 Wr strobe = 3 30ns
911 21..20 Wr hold = 1
912 19..16 Rd setup =1
913 15..14 Ta = 2
914 13..8 Rd strobe = 3 30ns
915 7..4 MTYPE 0010 Async 32bits
916 3 Wr hold MSB =0
917 2..0 Rd hold = 1
918 */
919 {
920 u32 cE1 =
921 (1L << 28) | (3L << 22) | (1L << 20) | (1L <<
922 16) | (2L << 14) | (3L << 8) | (2L << 4) | 1L;
923 hpi_write_word(pdo, 0x01800004, cE1);
924 }
925
926 /* delay a little to allow SDRAM and DSP to "get going" */
927
928 for (i = 0; i < 1000; i++)
929 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
930
931 /* test access to SDRAM */
932 {
933 test_addr = 0x80000000;
934 test_data = 0x00000001;
935 /* test each bit in the 32bit word */
936 for (j = 0; j < 32; j++) {
937 hpi_write_word(pdo, test_addr, test_data);
938 data = hpi_read_word(pdo, test_addr);
939 if (data != test_data) {
940 HPI_DEBUG_LOG(ERROR,
941 "DSP dram %x %x %x %x\n",
942 test_addr, test_data, data,
943 dsp_index);
944
945 return HPI6000_ERROR_INIT_SDRAM1;
946 }
947 test_data = test_data << 1;
948 }
949 /* test every Nth address in the DRAM */
950 #define DRAM_SIZE_WORDS 0x200000 /*2_mx32 */
951 #define DRAM_INC 1024
952 test_addr = 0x80000000;
953 test_data = 0x0;
954 for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) {
955 hpi_write_word(pdo, test_addr + i, test_data);
956 test_data++;
957 }
958 test_addr = 0x80000000;
959 test_data = 0x0;
960 for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) {
961 data = hpi_read_word(pdo, test_addr + i);
962 if (data != test_data) {
963 HPI_DEBUG_LOG(ERROR,
964 "DSP dram %x %x %x %x\n",
965 test_addr + i, test_data,
966 data, dsp_index);
967 return HPI6000_ERROR_INIT_SDRAM2;
968 }
969 test_data++;
970 }
971
972 }
973
974 /* write the DSP code down into the DSPs memory */
975 /*HpiDspCode_Open(nBootLoadFamily,&DspCode,pdwOsErrorCode); */
976 dsp_code.ps_dev = pao->pci.p_os_data;
977
978 error = hpi_dsp_code_open(boot_load_family, &dsp_code,
979 pos_error_code);
980
981 if (error)
982 return error;
983
984 while (1) {
985 u32 length;
986 u32 address;
987 u32 type;
988 u32 *pcode;
989
990 error = hpi_dsp_code_read_word(&dsp_code, &length);
991 if (error)
992 break;
993 if (length == 0xFFFFFFFF)
994 break; /* end of code */
995
996 error = hpi_dsp_code_read_word(&dsp_code, &address);
997 if (error)
998 break;
999 error = hpi_dsp_code_read_word(&dsp_code, &type);
1000 if (error)
1001 break;
1002 error = hpi_dsp_code_read_block(length, &dsp_code,
1003 &pcode);
1004 if (error)
1005 break;
1006 error = hpi6000_dsp_block_write32(pao, (u16)dsp_index,
1007 address, pcode, length);
1008 if (error)
1009 break;
1010 }
1011
1012 if (error) {
1013 hpi_dsp_code_close(&dsp_code);
1014 return error;
1015 }
1016 /* verify that code was written correctly */
1017 /* this time through, assume no errors in DSP code file/array */
1018 hpi_dsp_code_rewind(&dsp_code);
1019 while (1) {
1020 u32 length;
1021 u32 address;
1022 u32 type;
1023 u32 *pcode;
1024
1025 hpi_dsp_code_read_word(&dsp_code, &length);
1026 if (length == 0xFFFFFFFF)
1027 break; /* end of code */
1028
1029 hpi_dsp_code_read_word(&dsp_code, &address);
1030 hpi_dsp_code_read_word(&dsp_code, &type);
1031 hpi_dsp_code_read_block(length, &dsp_code, &pcode);
1032
1033 for (i = 0; i < length; i++) {
1034 data = hpi_read_word(pdo, address);
1035 if (data != *pcode) {
1036 error = HPI6000_ERROR_INIT_VERIFY;
1037 HPI_DEBUG_LOG(ERROR,
1038 "DSP verify %x %x %x %x\n",
1039 address, *pcode, data,
1040 dsp_index);
1041 break;
1042 }
1043 pcode++;
1044 address += 4;
1045 }
1046 if (error)
1047 break;
1048 }
1049 hpi_dsp_code_close(&dsp_code);
1050 if (error)
1051 return error;
1052
1053 /* zero out the hostmailbox */
1054 {
1055 u32 address = HPI_HIF_ADDR(host_cmd);
1056 for (i = 0; i < 4; i++) {
1057 hpi_write_word(pdo, address, 0);
1058 address += 4;
1059 }
1060 }
1061 /* write the DSP number into the hostmailbox */
1062 /* structure before starting the DSP */
1063 hpi_write_word(pdo, HPI_HIF_ADDR(dsp_number), dsp_index);
1064
1065 /* write the DSP adapter Info into the */
1066 /* hostmailbox before starting the DSP */
1067 if (dsp_index > 0)
1068 hpi_write_word(pdo, HPI_HIF_ADDR(adapter_info),
1069 adapter_info);
1070
1071 /* step 3. Start code by sending interrupt */
1072 iowrite32(0x00030003, pdo->prHPI_control);
1073 for (i = 0; i < 10000; i++)
1074 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
1075
1076 /* wait for a non-zero value in hostcmd -
1077 * indicating initialization is complete
1078 *
1079 * Init could take a while if DSP checks SDRAM memory
1080 * Was 200000. Increased to 2000000 for ASI8801 so we
1081 * don't get 938 errors.
1082 */
1083 timeout = 2000000;
1084 while (timeout) {
1085 do {
1086 read = hpi_read_word(pdo,
1087 HPI_HIF_ADDR(host_cmd));
1088 } while (--timeout
1089 && hpi6000_check_PCI2040_error_flag(pao,
1090 H6READ));
1091
1092 if (read)
1093 break;
1094 /* The following is a workaround for bug #94:
1095 * Bluescreen on install and subsequent boots on a
1096 * DELL PowerEdge 600SC PC with 1.8GHz P4 and
1097 * ServerWorks chipset. Without this delay the system
1098 * locks up with a bluescreen (NOT GPF or pagefault).
1099 */
1100 else
1101 hpios_delay_micro_seconds(1000);
1102 }
1103 if (timeout == 0)
1104 return HPI6000_ERROR_INIT_NOACK;
1105
1106 /* read the DSP adapter Info from the */
1107 /* hostmailbox structure after starting the DSP */
1108 if (dsp_index == 0) {
1109 /*u32 dwTestData=0; */
1110 u32 mask = 0;
1111
1112 adapter_info =
1113 hpi_read_word(pdo,
1114 HPI_HIF_ADDR(adapter_info));
1115 if (HPI_ADAPTER_FAMILY_ASI
1116 (HPI_HIF_ADAPTER_INFO_EXTRACT_ADAPTER
1117 (adapter_info)) ==
1118 HPI_ADAPTER_FAMILY_ASI(0x6200))
1119 /* all 6200 cards have this many DSPs */
1120 phw->num_dsp = 2;
1121
1122 /* test that the PLD is programmed */
1123 /* and we can read/write 24bits */
1124 #define PLD_BASE_ADDRESS 0x90000000L /*for ASI6100/6200/8800 */
1125
1126 switch (boot_load_family) {
1127 case HPI_ADAPTER_FAMILY_ASI(0x6200):
1128 /* ASI6100/6200 has 24bit path to FPGA */
1129 mask = 0xFFFFFF00L;
1130 /* ASI5100 uses AX6 code, */
1131 /* but has no PLD r/w register to test */
1132 if (HPI_ADAPTER_FAMILY_ASI(pao->pci.
1133 subsys_device_id) ==
1134 HPI_ADAPTER_FAMILY_ASI(0x5100))
1135 mask = 0x00000000L;
1136 break;
1137 case HPI_ADAPTER_FAMILY_ASI(0x8800):
1138 /* ASI8800 has 16bit path to FPGA */
1139 mask = 0xFFFF0000L;
1140 break;
1141 }
1142 test_data = 0xAAAAAA00L & mask;
1143 /* write to 24 bit Debug register (D31-D8) */
1144 hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data);
1145 read = hpi_read_word(pdo,
1146 PLD_BASE_ADDRESS + 4L) & mask;
1147 if (read != test_data) {
1148 HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data,
1149 read);
1150 return HPI6000_ERROR_INIT_PLDTEST1;
1151 }
1152 test_data = 0x55555500L & mask;
1153 hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data);
1154 read = hpi_read_word(pdo,
1155 PLD_BASE_ADDRESS + 4L) & mask;
1156 if (read != test_data) {
1157 HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data,
1158 read);
1159 return HPI6000_ERROR_INIT_PLDTEST2;
1160 }
1161 }
1162 } /* for numDSP */
1163 return 0;
1164 }
1165
1166 #define PCI_TIMEOUT 100
1167
1168 static int hpi_set_address(struct dsp_obj *pdo, u32 address)
1169 {
1170 u32 timeout = PCI_TIMEOUT;
1171
1172 do {
1173 iowrite32(address, pdo->prHPI_address);
1174 } while (hpi6000_check_PCI2040_error_flag(pdo->pa_parent_adapter,
1175 H6WRITE)
1176 && --timeout);
1177
1178 if (timeout)
1179 return 0;
1180
1181 return 1;
1182 }
1183
1184 /* write one word to the HPI port */
1185 static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data)
1186 {
1187 if (hpi_set_address(pdo, address))
1188 return;
1189 iowrite32(data, pdo->prHPI_data);
1190 }
1191
1192 /* read one word from the HPI port */
1193 static u32 hpi_read_word(struct dsp_obj *pdo, u32 address)
1194 {
1195 u32 data = 0;
1196
1197 if (hpi_set_address(pdo, address))
1198 return 0; /*? no way to return error */
1199
1200 /* take care of errata in revB DSP (2.0.1) */
1201 data = ioread32(pdo->prHPI_data);
1202 return data;
1203 }
1204
1205 /* write a block of 32bit words to the DSP HPI port using auto-inc mode */
1206 static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
1207 u32 length)
1208 {
1209 u16 length16 = length - 1;
1210
1211 if (length == 0)
1212 return;
1213
1214 if (hpi_set_address(pdo, address))
1215 return;
1216
1217 iowrite32_rep(pdo->prHPI_data_auto_inc, pdata, length16);
1218
1219 /* take care of errata in revB DSP (2.0.1) */
1220 /* must end with non auto-inc */
1221 iowrite32(*(pdata + length - 1), pdo->prHPI_data);
1222 }
1223
1224 /** read a block of 32bit words from the DSP HPI port using auto-inc mode
1225 */
1226 static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
1227 u32 length)
1228 {
1229 u16 length16 = length - 1;
1230
1231 if (length == 0)
1232 return;
1233
1234 if (hpi_set_address(pdo, address))
1235 return;
1236
1237 ioread32_rep(pdo->prHPI_data_auto_inc, pdata, length16);
1238
1239 /* take care of errata in revB DSP (2.0.1) */
1240 /* must end with non auto-inc */
1241 *(pdata + length - 1) = ioread32(pdo->prHPI_data);
1242 }
1243
1244 static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao,
1245 u16 dsp_index, u32 hpi_address, u32 *source, u32 count)
1246 {
1247 struct dsp_obj *pdo =
1248 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1249 u32 time_out = PCI_TIMEOUT;
1250 int c6711_burst_size = 128;
1251 u32 local_hpi_address = hpi_address;
1252 int local_count = count;
1253 int xfer_size;
1254 u32 *pdata = source;
1255
1256 while (local_count) {
1257 if (local_count > c6711_burst_size)
1258 xfer_size = c6711_burst_size;
1259 else
1260 xfer_size = local_count;
1261
1262 time_out = PCI_TIMEOUT;
1263 do {
1264 hpi_write_block(pdo, local_hpi_address, pdata,
1265 xfer_size);
1266 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE)
1267 && --time_out);
1268
1269 if (!time_out)
1270 break;
1271 pdata += xfer_size;
1272 local_hpi_address += sizeof(u32) * xfer_size;
1273 local_count -= xfer_size;
1274 }
1275
1276 if (time_out)
1277 return 0;
1278 else
1279 return 1;
1280 }
1281
1282 static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao,
1283 u16 dsp_index, u32 hpi_address, u32 *dest, u32 count)
1284 {
1285 struct dsp_obj *pdo =
1286 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1287 u32 time_out = PCI_TIMEOUT;
1288 int c6711_burst_size = 16;
1289 u32 local_hpi_address = hpi_address;
1290 int local_count = count;
1291 int xfer_size;
1292 u32 *pdata = dest;
1293 u32 loop_count = 0;
1294
1295 while (local_count) {
1296 if (local_count > c6711_burst_size)
1297 xfer_size = c6711_burst_size;
1298 else
1299 xfer_size = local_count;
1300
1301 time_out = PCI_TIMEOUT;
1302 do {
1303 hpi_read_block(pdo, local_hpi_address, pdata,
1304 xfer_size);
1305 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1306 && --time_out);
1307 if (!time_out)
1308 break;
1309
1310 pdata += xfer_size;
1311 local_hpi_address += sizeof(u32) * xfer_size;
1312 local_count -= xfer_size;
1313 loop_count++;
1314 }
1315
1316 if (time_out)
1317 return 0;
1318 else
1319 return 1;
1320 }
1321
1322 static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao,
1323 u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr)
1324 {
1325 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1326 struct dsp_obj *pdo = &phw->ado[dsp_index];
1327 u32 timeout;
1328 u16 ack;
1329 u32 address;
1330 u32 length;
1331 u32 *p_data;
1332 u16 error = 0;
1333
1334 /* does the DSP we are referencing exist? */
1335 if (dsp_index >= phw->num_dsp)
1336 return HPI6000_ERROR_MSG_INVALID_DSP_INDEX;
1337
1338 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
1339 if (ack & HPI_HIF_ERROR_MASK) {
1340 pao->dsp_crashed++;
1341 return HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT;
1342 }
1343 pao->dsp_crashed = 0;
1344
1345 /* send the message */
1346
1347 /* get the address and size */
1348 if (phw->message_buffer_address_on_dsp == 0) {
1349 timeout = TIMEOUT;
1350 do {
1351 address =
1352 hpi_read_word(pdo,
1353 HPI_HIF_ADDR(message_buffer_address));
1354 phw->message_buffer_address_on_dsp = address;
1355 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1356 && --timeout);
1357 if (!timeout)
1358 return HPI6000_ERROR_MSG_GET_ADR;
1359 } else
1360 address = phw->message_buffer_address_on_dsp;
1361
1362 /* dwLength = sizeof(struct hpi_message); */
1363 length = phm->size;
1364
1365 /* send it */
1366 p_data = (u32 *)phm;
1367 if (hpi6000_dsp_block_write32(pao, dsp_index, address, p_data,
1368 (u16)length / 4))
1369 return HPI6000_ERROR_MSG_RESP_BLOCKWRITE32;
1370
1371 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_GET_RESP))
1372 return HPI6000_ERROR_MSG_RESP_GETRESPCMD;
1373 hpi6000_send_dsp_interrupt(pdo);
1374
1375 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_RESP);
1376 if (ack & HPI_HIF_ERROR_MASK)
1377 return HPI6000_ERROR_MSG_RESP_GET_RESP_ACK;
1378
1379 /* get the address and size */
1380 if (phw->response_buffer_address_on_dsp == 0) {
1381 timeout = TIMEOUT;
1382 do {
1383 address =
1384 hpi_read_word(pdo,
1385 HPI_HIF_ADDR(response_buffer_address));
1386 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1387 && --timeout);
1388 phw->response_buffer_address_on_dsp = address;
1389
1390 if (!timeout)
1391 return HPI6000_ERROR_RESP_GET_ADR;
1392 } else
1393 address = phw->response_buffer_address_on_dsp;
1394
1395 /* read the length of the response back from the DSP */
1396 timeout = TIMEOUT;
1397 do {
1398 length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
1399 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout);
1400 if (!timeout)
1401 length = sizeof(struct hpi_response);
1402
1403 /* get it */
1404 p_data = (u32 *)phr;
1405 if (hpi6000_dsp_block_read32(pao, dsp_index, address, p_data,
1406 (u16)length / 4))
1407 return HPI6000_ERROR_MSG_RESP_BLOCKREAD32;
1408
1409 /* set i/f back to idle */
1410 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
1411 return HPI6000_ERROR_MSG_RESP_IDLECMD;
1412 hpi6000_send_dsp_interrupt(pdo);
1413
1414 error = hpi_validate_response(phm, phr);
1415 return error;
1416 }
1417
1418 /* have to set up the below defines to match stuff in the MAP file */
1419
1420 #define MSG_ADDRESS (HPI_HIF_BASE+0x18)
1421 #define MSG_LENGTH 11
1422 #define RESP_ADDRESS (HPI_HIF_BASE+0x44)
1423 #define RESP_LENGTH 16
1424 #define QUEUE_START (HPI_HIF_BASE+0x88)
1425 #define QUEUE_SIZE 0x8000
1426
1427 static short hpi6000_send_data_check_adr(u32 address, u32 length_in_dwords)
1428 {
1429 /*#define CHECKING // comment this line in to enable checking */
1430 #ifdef CHECKING
1431 if (address < (u32)MSG_ADDRESS)
1432 return 0;
1433 if (address > (u32)(QUEUE_START + QUEUE_SIZE))
1434 return 0;
1435 if ((address + (length_in_dwords << 2)) >
1436 (u32)(QUEUE_START + QUEUE_SIZE))
1437 return 0;
1438 #else
1439 (void)address;
1440 (void)length_in_dwords;
1441 return 1;
1442 #endif
1443 }
1444
1445 static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index,
1446 struct hpi_message *phm, struct hpi_response *phr)
1447 {
1448 struct dsp_obj *pdo =
1449 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1450 u32 data_sent = 0;
1451 u16 ack;
1452 u32 length, address;
1453 u32 *p_data = (u32 *)phm->u.d.u.data.pb_data;
1454 u16 time_out = 8;
1455
1456 (void)phr;
1457
1458 /* round dwDataSize down to nearest 4 bytes */
1459 while ((data_sent < (phm->u.d.u.data.data_size & ~3L))
1460 && --time_out) {
1461 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
1462 if (ack & HPI_HIF_ERROR_MASK)
1463 return HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT;
1464
1465 if (hpi6000_send_host_command(pao, dsp_index,
1466 HPI_HIF_SEND_DATA))
1467 return HPI6000_ERROR_SEND_DATA_CMD;
1468
1469 hpi6000_send_dsp_interrupt(pdo);
1470
1471 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_SEND_DATA);
1472
1473 if (ack & HPI_HIF_ERROR_MASK)
1474 return HPI6000_ERROR_SEND_DATA_ACK;
1475
1476 do {
1477 /* get the address and size */
1478 address = hpi_read_word(pdo, HPI_HIF_ADDR(address));
1479 /* DSP returns number of DWORDS */
1480 length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
1481 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ));
1482
1483 if (!hpi6000_send_data_check_adr(address, length))
1484 return HPI6000_ERROR_SEND_DATA_ADR;
1485
1486 /* send the data. break data into 512 DWORD blocks (2K bytes)
1487 * and send using block write. 2Kbytes is the max as this is the
1488 * memory window given to the HPI data register by the PCI2040
1489 */
1490
1491 {
1492 u32 len = length;
1493 u32 blk_len = 512;
1494 while (len) {
1495 if (len < blk_len)
1496 blk_len = len;
1497 if (hpi6000_dsp_block_write32(pao, dsp_index,
1498 address, p_data, blk_len))
1499 return HPI6000_ERROR_SEND_DATA_WRITE;
1500 address += blk_len * 4;
1501 p_data += blk_len;
1502 len -= blk_len;
1503 }
1504 }
1505
1506 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
1507 return HPI6000_ERROR_SEND_DATA_IDLECMD;
1508
1509 hpi6000_send_dsp_interrupt(pdo);
1510
1511 data_sent += length * 4;
1512 }
1513 if (!time_out)
1514 return HPI6000_ERROR_SEND_DATA_TIMEOUT;
1515 return 0;
1516 }
1517
1518 static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index,
1519 struct hpi_message *phm, struct hpi_response *phr)
1520 {
1521 struct dsp_obj *pdo =
1522 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1523 u32 data_got = 0;
1524 u16 ack;
1525 u32 length, address;
1526 u32 *p_data = (u32 *)phm->u.d.u.data.pb_data;
1527
1528 (void)phr; /* this parameter not used! */
1529
1530 /* round dwDataSize down to nearest 4 bytes */
1531 while (data_got < (phm->u.d.u.data.data_size & ~3L)) {
1532 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
1533 if (ack & HPI_HIF_ERROR_MASK)
1534 return HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT;
1535
1536 if (hpi6000_send_host_command(pao, dsp_index,
1537 HPI_HIF_GET_DATA))
1538 return HPI6000_ERROR_GET_DATA_CMD;
1539 hpi6000_send_dsp_interrupt(pdo);
1540
1541 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_DATA);
1542
1543 if (ack & HPI_HIF_ERROR_MASK)
1544 return HPI6000_ERROR_GET_DATA_ACK;
1545
1546 /* get the address and size */
1547 do {
1548 address = hpi_read_word(pdo, HPI_HIF_ADDR(address));
1549 length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
1550 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ));
1551
1552 /* read the data */
1553 {
1554 u32 len = length;
1555 u32 blk_len = 512;
1556 while (len) {
1557 if (len < blk_len)
1558 blk_len = len;
1559 if (hpi6000_dsp_block_read32(pao, dsp_index,
1560 address, p_data, blk_len))
1561 return HPI6000_ERROR_GET_DATA_READ;
1562 address += blk_len * 4;
1563 p_data += blk_len;
1564 len -= blk_len;
1565 }
1566 }
1567
1568 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
1569 return HPI6000_ERROR_GET_DATA_IDLECMD;
1570 hpi6000_send_dsp_interrupt(pdo);
1571
1572 data_got += length * 4;
1573 }
1574 return 0;
1575 }
1576
1577 static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo)
1578 {
1579 iowrite32(0x00030003, pdo->prHPI_control); /* DSPINT */
1580 }
1581
1582 static short hpi6000_send_host_command(struct hpi_adapter_obj *pao,
1583 u16 dsp_index, u32 host_cmd)
1584 {
1585 struct dsp_obj *pdo =
1586 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1587 u32 timeout = TIMEOUT;
1588
1589 /* set command */
1590 do {
1591 hpi_write_word(pdo, HPI_HIF_ADDR(host_cmd), host_cmd);
1592 /* flush the FIFO */
1593 hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd));
1594 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) && --timeout);
1595
1596 /* reset the interrupt bit */
1597 iowrite32(0x00040004, pdo->prHPI_control);
1598
1599 if (timeout)
1600 return 0;
1601 else
1602 return 1;
1603 }
1604
1605 /* if the PCI2040 has recorded an HPI timeout, reset the error and return 1 */
1606 static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao,
1607 u16 read_or_write)
1608 {
1609 u32 hPI_error;
1610
1611 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1612
1613 /* read the error bits from the PCI2040 */
1614 hPI_error = ioread32(phw->dw2040_HPICSR + HPI_ERROR_REPORT);
1615 if (hPI_error) {
1616 /* reset the error flag */
1617 iowrite32(0L, phw->dw2040_HPICSR + HPI_ERROR_REPORT);
1618 phw->pCI2040HPI_error_count++;
1619 if (read_or_write == 1)
1620 gw_pci_read_asserts++; /************* inc global */
1621 else
1622 gw_pci_write_asserts++;
1623 return 1;
1624 } else
1625 return 0;
1626 }
1627
1628 static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index,
1629 u32 ack_value)
1630 {
1631 struct dsp_obj *pdo =
1632 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1633 u32 ack = 0L;
1634 u32 timeout;
1635 u32 hPIC = 0L;
1636
1637 /* wait for host interrupt to signal ack is ready */
1638 timeout = TIMEOUT;
1639 while (--timeout) {
1640 hPIC = ioread32(pdo->prHPI_control);
1641 if (hPIC & 0x04) /* 0x04 = HINT from DSP */
1642 break;
1643 }
1644 if (timeout == 0)
1645 return HPI_HIF_ERROR_MASK;
1646
1647 /* wait for dwAckValue */
1648 timeout = TIMEOUT;
1649 while (--timeout) {
1650 /* read the ack mailbox */
1651 ack = hpi_read_word(pdo, HPI_HIF_ADDR(dsp_ack));
1652 if (ack == ack_value)
1653 break;
1654 if ((ack & HPI_HIF_ERROR_MASK)
1655 && !hpi6000_check_PCI2040_error_flag(pao, H6READ))
1656 break;
1657 /*for (i=0;i<1000;i++) */
1658 /* dwPause=i+1; */
1659 }
1660 if (ack & HPI_HIF_ERROR_MASK)
1661 /* indicates bad read from DSP -
1662 typically 0xffffff is read for some reason */
1663 ack = HPI_HIF_ERROR_MASK;
1664
1665 if (timeout == 0)
1666 ack = HPI_HIF_ERROR_MASK;
1667 return (short)ack;
1668 }
1669
1670 static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao,
1671 struct hpi_message *phm)
1672 {
1673 const u16 dsp_index = 0;
1674 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1675 struct dsp_obj *pdo = &phw->ado[dsp_index];
1676 u32 timeout;
1677 u32 cache_dirty_flag;
1678 u16 err;
1679
1680 hpios_dsplock_lock(pao);
1681
1682 timeout = TIMEOUT;
1683 do {
1684 cache_dirty_flag =
1685 hpi_read_word((struct dsp_obj *)pdo,
1686 HPI_HIF_ADDR(control_cache_is_dirty));
1687 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout);
1688 if (!timeout) {
1689 err = HPI6000_ERROR_CONTROL_CACHE_PARAMS;
1690 goto unlock;
1691 }
1692
1693 if (cache_dirty_flag) {
1694 /* read the cached controls */
1695 u32 address;
1696 u32 length;
1697
1698 timeout = TIMEOUT;
1699 if (pdo->control_cache_address_on_dsp == 0) {
1700 do {
1701 address =
1702 hpi_read_word((struct dsp_obj *)pdo,
1703 HPI_HIF_ADDR(control_cache_address));
1704
1705 length = hpi_read_word((struct dsp_obj *)pdo,
1706 HPI_HIF_ADDR
1707 (control_cache_size_in_bytes));
1708 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1709 && --timeout);
1710 if (!timeout) {
1711 err = HPI6000_ERROR_CONTROL_CACHE_ADDRLEN;
1712 goto unlock;
1713 }
1714 pdo->control_cache_address_on_dsp = address;
1715 pdo->control_cache_length_on_dsp = length;
1716 } else {
1717 address = pdo->control_cache_address_on_dsp;
1718 length = pdo->control_cache_length_on_dsp;
1719 }
1720
1721 if (hpi6000_dsp_block_read32(pao, dsp_index, address,
1722 (u32 *)&phw->control_cache[0],
1723 length / sizeof(u32))) {
1724 err = HPI6000_ERROR_CONTROL_CACHE_READ;
1725 goto unlock;
1726 }
1727 do {
1728 hpi_write_word((struct dsp_obj *)pdo,
1729 HPI_HIF_ADDR(control_cache_is_dirty), 0);
1730 /* flush the FIFO */
1731 hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd));
1732 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE)
1733 && --timeout);
1734 if (!timeout) {
1735 err = HPI6000_ERROR_CONTROL_CACHE_FLUSH;
1736 goto unlock;
1737 }
1738
1739 }
1740 err = 0;
1741
1742 unlock:
1743 hpios_dsplock_unlock(pao);
1744 return err;
1745 }
1746
1747 /** Get dsp index for multi DSP adapters only */
1748 static u16 get_dsp_index(struct hpi_adapter_obj *pao, struct hpi_message *phm)
1749 {
1750 u16 ret = 0;
1751 switch (phm->object) {
1752 case HPI_OBJ_ISTREAM:
1753 if (phm->obj_index < 2)
1754 ret = 1;
1755 break;
1756 case HPI_OBJ_PROFILE:
1757 ret = phm->obj_index;
1758 break;
1759 default:
1760 break;
1761 }
1762 return ret;
1763 }
1764
1765 /** Complete transaction with DSP
1766
1767 Send message, get response, send or get stream data if any.
1768 */
1769 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
1770 struct hpi_response *phr)
1771 {
1772 u16 error = 0;
1773 u16 dsp_index = 0;
1774 u16 num_dsp = ((struct hpi_hw_obj *)pao->priv)->num_dsp;
1775
1776 if (num_dsp < 2)
1777 dsp_index = 0;
1778 else {
1779 dsp_index = get_dsp_index(pao, phm);
1780
1781 /* is this checked on the DSP anyway? */
1782 if ((phm->function == HPI_ISTREAM_GROUP_ADD)
1783 || (phm->function == HPI_OSTREAM_GROUP_ADD)) {
1784 struct hpi_message hm;
1785 u16 add_index;
1786 hm.obj_index = phm->u.d.u.stream.stream_index;
1787 hm.object = phm->u.d.u.stream.object_type;
1788 add_index = get_dsp_index(pao, &hm);
1789 if (add_index != dsp_index) {
1790 phr->error = HPI_ERROR_NO_INTERDSP_GROUPS;
1791 return;
1792 }
1793 }
1794 }
1795
1796 hpios_dsplock_lock(pao);
1797 error = hpi6000_message_response_sequence(pao, dsp_index, phm, phr);
1798
1799 /* maybe an error response */
1800 if (error) {
1801 /* something failed in the HPI/DSP interface */
1802 phr->error = error;
1803 /* just the header of the response is valid */
1804 phr->size = sizeof(struct hpi_response_header);
1805 goto err;
1806 }
1807
1808 if (phr->error != 0) /* something failed in the DSP */
1809 goto err;
1810
1811 switch (phm->function) {
1812 case HPI_OSTREAM_WRITE:
1813 case HPI_ISTREAM_ANC_WRITE:
1814 error = hpi6000_send_data(pao, dsp_index, phm, phr);
1815 break;
1816 case HPI_ISTREAM_READ:
1817 case HPI_OSTREAM_ANC_READ:
1818 error = hpi6000_get_data(pao, dsp_index, phm, phr);
1819 break;
1820 case HPI_ADAPTER_GET_ASSERT:
1821 phr->u.a.adapter_index = 0; /* dsp 0 default */
1822 if (num_dsp == 2) {
1823 if (!phr->u.a.adapter_type) {
1824 /* no assert from dsp 0, check dsp 1 */
1825 error = hpi6000_message_response_sequence(pao,
1826 1, phm, phr);
1827 phr->u.a.adapter_index = 1;
1828 }
1829 }
1830 }
1831
1832 if (error)
1833 phr->error = error;
1834
1835 err:
1836 hpios_dsplock_unlock(pao);
1837 return;
1838 }
Linux with added FPC-III support