1 /* sound/soc/s3c24xx/s3c-ac97.c
3 * ALSA SoC Audio Layer - S3C AC97 Controller driver
4 * Evolved from s3c2443-ac97.c
6 * Copyright (c) 2010 Samsung Electronics Co. Ltd
7 * Author: Jaswinder Singh <jassi.brar@samsung.com>
8 * Credits: Graeme Gregory, Sean Choi
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
18 #include <linux/delay.h>
19 #include <linux/clk.h>
21 #include <sound/soc.h>
23 #include <plat/regs-ac97.h>
25 #include <plat/audio.h>
30 #define AC_CMD_ADDR(x) (x << 16)
31 #define AC_CMD_DATA(x) (x & 0xffff)
33 struct s3c_ac97_info
{
38 struct completion done
;
40 static struct s3c_ac97_info s3c_ac97
;
42 static struct s3c2410_dma_client s3c_dma_client_out
= {
46 static struct s3c2410_dma_client s3c_dma_client_in
= {
50 static struct s3c2410_dma_client s3c_dma_client_micin
= {
54 static struct s3c_dma_params s3c_ac97_pcm_out
= {
55 .client
= &s3c_dma_client_out
,
59 static struct s3c_dma_params s3c_ac97_pcm_in
= {
60 .client
= &s3c_dma_client_in
,
64 static struct s3c_dma_params s3c_ac97_mic_in
= {
65 .client
= &s3c_dma_client_micin
,
69 static void s3c_ac97_activate(struct snd_ac97
*ac97
)
73 stat
= readl(s3c_ac97
.regs
+ S3C_AC97_GLBSTAT
) & 0x7;
74 if (stat
== S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE
)
75 return; /* Return if already active */
77 INIT_COMPLETION(s3c_ac97
.done
);
79 ac_glbctrl
= readl(s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
80 ac_glbctrl
= S3C_AC97_GLBCTRL_ACLINKON
;
81 writel(ac_glbctrl
, s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
84 ac_glbctrl
|= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE
;
85 writel(ac_glbctrl
, s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
88 ac_glbctrl
= readl(s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
89 ac_glbctrl
|= S3C_AC97_GLBCTRL_CODECREADYIE
;
90 writel(ac_glbctrl
, s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
92 if (!wait_for_completion_timeout(&s3c_ac97
.done
, HZ
))
93 printk(KERN_ERR
"AC97: Unable to activate!");
96 static unsigned short s3c_ac97_read(struct snd_ac97
*ac97
,
99 u32 ac_glbctrl
, ac_codec_cmd
;
100 u32 stat
, addr
, data
;
102 mutex_lock(&s3c_ac97
.lock
);
104 s3c_ac97_activate(ac97
);
106 INIT_COMPLETION(s3c_ac97
.done
);
108 ac_codec_cmd
= readl(s3c_ac97
.regs
+ S3C_AC97_CODEC_CMD
);
109 ac_codec_cmd
= S3C_AC97_CODEC_CMD_READ
| AC_CMD_ADDR(reg
);
110 writel(ac_codec_cmd
, s3c_ac97
.regs
+ S3C_AC97_CODEC_CMD
);
114 ac_glbctrl
= readl(s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
115 ac_glbctrl
|= S3C_AC97_GLBCTRL_CODECREADYIE
;
116 writel(ac_glbctrl
, s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
118 if (!wait_for_completion_timeout(&s3c_ac97
.done
, HZ
))
119 printk(KERN_ERR
"AC97: Unable to read!");
121 stat
= readl(s3c_ac97
.regs
+ S3C_AC97_STAT
);
122 addr
= (stat
>> 16) & 0x7f;
123 data
= (stat
& 0xffff);
126 printk(KERN_ERR
"s3c-ac97: req addr = %02x, rep addr = %02x\n", reg
, addr
);
128 mutex_unlock(&s3c_ac97
.lock
);
130 return (unsigned short)data
;
133 static void s3c_ac97_write(struct snd_ac97
*ac97
, unsigned short reg
,
136 u32 ac_glbctrl
, ac_codec_cmd
;
138 mutex_lock(&s3c_ac97
.lock
);
140 s3c_ac97_activate(ac97
);
142 INIT_COMPLETION(s3c_ac97
.done
);
144 ac_codec_cmd
= readl(s3c_ac97
.regs
+ S3C_AC97_CODEC_CMD
);
145 ac_codec_cmd
= AC_CMD_ADDR(reg
) | AC_CMD_DATA(val
);
146 writel(ac_codec_cmd
, s3c_ac97
.regs
+ S3C_AC97_CODEC_CMD
);
150 ac_glbctrl
= readl(s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
151 ac_glbctrl
|= S3C_AC97_GLBCTRL_CODECREADYIE
;
152 writel(ac_glbctrl
, s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
154 if (!wait_for_completion_timeout(&s3c_ac97
.done
, HZ
))
155 printk(KERN_ERR
"AC97: Unable to write!");
157 ac_codec_cmd
= readl(s3c_ac97
.regs
+ S3C_AC97_CODEC_CMD
);
158 ac_codec_cmd
|= S3C_AC97_CODEC_CMD_READ
;
159 writel(ac_codec_cmd
, s3c_ac97
.regs
+ S3C_AC97_CODEC_CMD
);
161 mutex_unlock(&s3c_ac97
.lock
);
164 static void s3c_ac97_cold_reset(struct snd_ac97
*ac97
)
166 writel(S3C_AC97_GLBCTRL_COLDRESET
,
167 s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
170 writel(0, s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
174 static void s3c_ac97_warm_reset(struct snd_ac97
*ac97
)
178 stat
= readl(s3c_ac97
.regs
+ S3C_AC97_GLBSTAT
) & 0x7;
179 if (stat
== S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE
)
180 return; /* Return if already active */
182 writel(S3C_AC97_GLBCTRL_WARMRESET
, s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
185 writel(0, s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
188 s3c_ac97_activate(ac97
);
191 static irqreturn_t
s3c_ac97_irq(int irq
, void *dev_id
)
193 u32 ac_glbctrl
, ac_glbstat
;
195 ac_glbstat
= readl(s3c_ac97
.regs
+ S3C_AC97_GLBSTAT
);
197 if (ac_glbstat
& S3C_AC97_GLBSTAT_CODECREADY
) {
199 ac_glbctrl
= readl(s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
200 ac_glbctrl
&= ~S3C_AC97_GLBCTRL_CODECREADYIE
;
201 writel(ac_glbctrl
, s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
203 complete(&s3c_ac97
.done
);
206 ac_glbctrl
= readl(s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
207 ac_glbctrl
|= (1<<30); /* Clear interrupt */
208 writel(ac_glbctrl
, s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
213 struct snd_ac97_bus_ops soc_ac97_ops
= {
214 .read
= s3c_ac97_read
,
215 .write
= s3c_ac97_write
,
216 .warm_reset
= s3c_ac97_warm_reset
,
217 .reset
= s3c_ac97_cold_reset
,
219 EXPORT_SYMBOL_GPL(soc_ac97_ops
);
221 static int s3c_ac97_hw_params(struct snd_pcm_substream
*substream
,
222 struct snd_pcm_hw_params
*params
,
223 struct snd_soc_dai
*dai
)
225 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
226 struct snd_soc_dai
*cpu_dai
= rtd
->dai
->cpu_dai
;
227 struct s3c_dma_params
*dma_data
;
229 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
230 dma_data
= &s3c_ac97_pcm_out
;
232 dma_data
= &s3c_ac97_pcm_in
;
234 snd_soc_dai_set_dma_data(cpu_dai
, substream
, dma_data
);
239 static int s3c_ac97_trigger(struct snd_pcm_substream
*substream
, int cmd
,
240 struct snd_soc_dai
*dai
)
243 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
244 struct s3c_dma_params
*dma_data
=
245 snd_soc_dai_get_dma_data(rtd
->dai
->cpu_dai
, substream
);
247 ac_glbctrl
= readl(s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
248 if (substream
->stream
== SNDRV_PCM_STREAM_CAPTURE
)
249 ac_glbctrl
&= ~S3C_AC97_GLBCTRL_PCMINTM_MASK
;
251 ac_glbctrl
&= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK
;
254 case SNDRV_PCM_TRIGGER_START
:
255 case SNDRV_PCM_TRIGGER_RESUME
:
256 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
257 if (substream
->stream
== SNDRV_PCM_STREAM_CAPTURE
)
258 ac_glbctrl
|= S3C_AC97_GLBCTRL_PCMINTM_DMA
;
260 ac_glbctrl
|= S3C_AC97_GLBCTRL_PCMOUTTM_DMA
;
263 case SNDRV_PCM_TRIGGER_STOP
:
264 case SNDRV_PCM_TRIGGER_SUSPEND
:
265 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
269 writel(ac_glbctrl
, s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
271 s3c2410_dma_ctrl(dma_data
->channel
, S3C2410_DMAOP_STARTED
);
276 static int s3c_ac97_hw_mic_params(struct snd_pcm_substream
*substream
,
277 struct snd_pcm_hw_params
*params
,
278 struct snd_soc_dai
*dai
)
280 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
281 struct snd_soc_dai
*cpu_dai
= rtd
->dai
->cpu_dai
;
283 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
286 snd_soc_dai_set_dma_data(cpu_dai
, substream
, &s3c_ac97_mic_in
);
291 static int s3c_ac97_mic_trigger(struct snd_pcm_substream
*substream
,
292 int cmd
, struct snd_soc_dai
*dai
)
295 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
296 struct s3c_dma_params
*dma_data
=
297 snd_soc_dai_get_dma_data(rtd
->dai
->cpu_dai
, substream
);
299 ac_glbctrl
= readl(s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
300 ac_glbctrl
&= ~S3C_AC97_GLBCTRL_MICINTM_MASK
;
303 case SNDRV_PCM_TRIGGER_START
:
304 case SNDRV_PCM_TRIGGER_RESUME
:
305 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
306 ac_glbctrl
|= S3C_AC97_GLBCTRL_MICINTM_DMA
;
309 case SNDRV_PCM_TRIGGER_STOP
:
310 case SNDRV_PCM_TRIGGER_SUSPEND
:
311 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
315 writel(ac_glbctrl
, s3c_ac97
.regs
+ S3C_AC97_GLBCTRL
);
317 s3c2410_dma_ctrl(dma_data
->channel
, S3C2410_DMAOP_STARTED
);
322 static struct snd_soc_dai_ops s3c_ac97_dai_ops
= {
323 .hw_params
= s3c_ac97_hw_params
,
324 .trigger
= s3c_ac97_trigger
,
327 static struct snd_soc_dai_ops s3c_ac97_mic_dai_ops
= {
328 .hw_params
= s3c_ac97_hw_mic_params
,
329 .trigger
= s3c_ac97_mic_trigger
,
332 struct snd_soc_dai s3c_ac97_dai
[] = {
333 [S3C_AC97_DAI_PCM
] = {
335 .id
= S3C_AC97_DAI_PCM
,
338 .stream_name
= "AC97 Playback",
341 .rates
= SNDRV_PCM_RATE_8000_48000
,
342 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,},
344 .stream_name
= "AC97 Capture",
347 .rates
= SNDRV_PCM_RATE_8000_48000
,
348 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,},
349 .ops
= &s3c_ac97_dai_ops
,
351 [S3C_AC97_DAI_MIC
] = {
352 .name
= "s3c-ac97-mic",
353 .id
= S3C_AC97_DAI_MIC
,
356 .stream_name
= "AC97 Mic Capture",
359 .rates
= SNDRV_PCM_RATE_8000_48000
,
360 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,},
361 .ops
= &s3c_ac97_mic_dai_ops
,
364 EXPORT_SYMBOL_GPL(s3c_ac97_dai
);
366 static __devinit
int s3c_ac97_probe(struct platform_device
*pdev
)
368 struct resource
*mem_res
, *dmatx_res
, *dmarx_res
, *dmamic_res
, *irq_res
;
369 struct s3c_audio_pdata
*ac97_pdata
;
372 ac97_pdata
= pdev
->dev
.platform_data
;
373 if (!ac97_pdata
|| !ac97_pdata
->cfg_gpio
) {
374 dev_err(&pdev
->dev
, "cfg_gpio callback not provided!\n");
378 /* Check for availability of necessary resource */
379 dmatx_res
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
381 dev_err(&pdev
->dev
, "Unable to get AC97-TX dma resource\n");
385 dmarx_res
= platform_get_resource(pdev
, IORESOURCE_DMA
, 1);
387 dev_err(&pdev
->dev
, "Unable to get AC97-RX dma resource\n");
391 dmamic_res
= platform_get_resource(pdev
, IORESOURCE_DMA
, 2);
393 dev_err(&pdev
->dev
, "Unable to get AC97-MIC dma resource\n");
397 mem_res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
399 dev_err(&pdev
->dev
, "Unable to get register resource\n");
403 irq_res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
405 dev_err(&pdev
->dev
, "AC97 IRQ not provided!\n");
409 if (!request_mem_region(mem_res
->start
,
410 resource_size(mem_res
), "s3c-ac97")) {
411 dev_err(&pdev
->dev
, "Unable to request register region\n");
415 s3c_ac97_pcm_out
.channel
= dmatx_res
->start
;
416 s3c_ac97_pcm_out
.dma_addr
= mem_res
->start
+ S3C_AC97_PCM_DATA
;
417 s3c_ac97_pcm_in
.channel
= dmarx_res
->start
;
418 s3c_ac97_pcm_in
.dma_addr
= mem_res
->start
+ S3C_AC97_PCM_DATA
;
419 s3c_ac97_mic_in
.channel
= dmamic_res
->start
;
420 s3c_ac97_mic_in
.dma_addr
= mem_res
->start
+ S3C_AC97_MIC_DATA
;
422 init_completion(&s3c_ac97
.done
);
423 mutex_init(&s3c_ac97
.lock
);
425 s3c_ac97
.regs
= ioremap(mem_res
->start
, resource_size(mem_res
));
426 if (s3c_ac97
.regs
== NULL
) {
427 dev_err(&pdev
->dev
, "Unable to ioremap register region\n");
432 s3c_ac97
.ac97_clk
= clk_get(&pdev
->dev
, "ac97");
433 if (IS_ERR(s3c_ac97
.ac97_clk
)) {
434 dev_err(&pdev
->dev
, "s3c-ac97 failed to get ac97_clock\n");
438 clk_enable(s3c_ac97
.ac97_clk
);
440 if (ac97_pdata
->cfg_gpio(pdev
)) {
441 dev_err(&pdev
->dev
, "Unable to configure gpio\n");
446 ret
= request_irq(irq_res
->start
, s3c_ac97_irq
,
447 IRQF_DISABLED
, "AC97", NULL
);
449 printk(KERN_ERR
"s3c-ac97: interrupt request failed.\n");
453 s3c_ac97_dai
[S3C_AC97_DAI_PCM
].dev
= &pdev
->dev
;
454 s3c_ac97_dai
[S3C_AC97_DAI_MIC
].dev
= &pdev
->dev
;
456 ret
= snd_soc_register_dais(s3c_ac97_dai
, ARRAY_SIZE(s3c_ac97_dai
));
463 free_irq(irq_res
->start
, NULL
);
466 clk_disable(s3c_ac97
.ac97_clk
);
467 clk_put(s3c_ac97
.ac97_clk
);
469 iounmap(s3c_ac97
.regs
);
471 release_mem_region(mem_res
->start
, resource_size(mem_res
));
476 static __devexit
int s3c_ac97_remove(struct platform_device
*pdev
)
478 struct resource
*mem_res
, *irq_res
;
480 snd_soc_unregister_dais(s3c_ac97_dai
, ARRAY_SIZE(s3c_ac97_dai
));
482 irq_res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
484 free_irq(irq_res
->start
, NULL
);
486 clk_disable(s3c_ac97
.ac97_clk
);
487 clk_put(s3c_ac97
.ac97_clk
);
489 iounmap(s3c_ac97
.regs
);
491 mem_res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
493 release_mem_region(mem_res
->start
, resource_size(mem_res
));
498 static struct platform_driver s3c_ac97_driver
= {
499 .probe
= s3c_ac97_probe
,
500 .remove
= s3c_ac97_remove
,
503 .owner
= THIS_MODULE
,
507 static int __init
s3c_ac97_init(void)
509 return platform_driver_register(&s3c_ac97_driver
);
511 module_init(s3c_ac97_init
);
513 static void __exit
s3c_ac97_exit(void)
515 platform_driver_unregister(&s3c_ac97_driver
);
517 module_exit(s3c_ac97_exit
);
519 MODULE_AUTHOR("Jaswinder Singh, <jassi.brar@samsung.com>");
520 MODULE_DESCRIPTION("AC97 driver for the Samsung SoC");
521 MODULE_LICENSE("GPL");