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wl1251: use wiphy_dev instead of wl->spi->dev
[linux/fpc-iii.git] / arch / arm / mach-mx3 / clock.c
blob8b14239724c97fe90746878f6c3727f62bdf7066
1 /*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/err.h>
25 #include <linux/io.h>
26
27 #include <asm/clkdev.h>
28 #include <asm/div64.h>
29
30 #include <mach/clock.h>
31 #include <mach/hardware.h>
32 #include <mach/common.h>
33
34 #include "crm_regs.h"
35
36 #define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */
37
38 static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
39 {
40 u32 min_pre, temp_pre, old_err, err;
41
42 if (div >= 512) {
43 *pre = 8;
44 *post = 64;
45 } else if (div >= 64) {
46 min_pre = (div - 1) / 64 + 1;
47 old_err = 8;
48 for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
49 err = div % temp_pre;
50 if (err == 0) {
51 *pre = temp_pre;
52 break;
53 }
54 err = temp_pre - err;
55 if (err < old_err) {
56 old_err = err;
57 *pre = temp_pre;
58 }
59 }
60 *post = (div + *pre - 1) / *pre;
61 } else if (div <= 8) {
62 *pre = div;
63 *post = 1;
64 } else {
65 *pre = 1;
66 *post = div;
67 }
68 }
69
70 static struct clk mcu_pll_clk;
71 static struct clk serial_pll_clk;
72 static struct clk ipg_clk;
73 static struct clk ckih_clk;
74
75 static int cgr_enable(struct clk *clk)
76 {
77 u32 reg;
78
79 if (!clk->enable_reg)
80 return 0;
81
82 reg = __raw_readl(clk->enable_reg);
83 reg |= 3 << clk->enable_shift;
84 __raw_writel(reg, clk->enable_reg);
85
86 return 0;
87 }
88
89 static void cgr_disable(struct clk *clk)
90 {
91 u32 reg;
92
93 if (!clk->enable_reg)
94 return;
95
96 reg = __raw_readl(clk->enable_reg);
97 reg &= ~(3 << clk->enable_shift);
98
99 /* special case for EMI clock */
100 if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8)
101 reg |= (1 << clk->enable_shift);
102
103 __raw_writel(reg, clk->enable_reg);
104 }
105
106 static unsigned long pll_ref_get_rate(void)
107 {
108 unsigned long ccmr;
109 unsigned int prcs;
110
111 ccmr = __raw_readl(MXC_CCM_CCMR);
112 prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
113 if (prcs == 0x1)
114 return CKIL_CLK_FREQ * 1024;
115 else
116 return clk_get_rate(&ckih_clk);
117 }
118
119 static unsigned long usb_pll_get_rate(struct clk *clk)
120 {
121 unsigned long reg;
122
123 reg = __raw_readl(MXC_CCM_UPCTL);
124
125 return mxc_decode_pll(reg, pll_ref_get_rate());
126 }
127
128 static unsigned long serial_pll_get_rate(struct clk *clk)
129 {
130 unsigned long reg;
131
132 reg = __raw_readl(MXC_CCM_SRPCTL);
133
134 return mxc_decode_pll(reg, pll_ref_get_rate());
135 }
136
137 static unsigned long mcu_pll_get_rate(struct clk *clk)
138 {
139 unsigned long reg, ccmr;
140
141 ccmr = __raw_readl(MXC_CCM_CCMR);
142
143 if (!(ccmr & MXC_CCM_CCMR_MPE) || (ccmr & MXC_CCM_CCMR_MDS))
144 return clk_get_rate(&ckih_clk);
145
146 reg = __raw_readl(MXC_CCM_MPCTL);
147
148 return mxc_decode_pll(reg, pll_ref_get_rate());
149 }
150
151 static int usb_pll_enable(struct clk *clk)
152 {
153 u32 reg;
154
155 reg = __raw_readl(MXC_CCM_CCMR);
156 reg |= MXC_CCM_CCMR_UPE;
157 __raw_writel(reg, MXC_CCM_CCMR);
158
159 /* No lock bit on MX31, so using max time from spec */
160 udelay(80);
161
162 return 0;
163 }
164
165 static void usb_pll_disable(struct clk *clk)
166 {
167 u32 reg;
168
169 reg = __raw_readl(MXC_CCM_CCMR);
170 reg &= ~MXC_CCM_CCMR_UPE;
171 __raw_writel(reg, MXC_CCM_CCMR);
172 }
173
174 static int serial_pll_enable(struct clk *clk)
175 {
176 u32 reg;
177
178 reg = __raw_readl(MXC_CCM_CCMR);
179 reg |= MXC_CCM_CCMR_SPE;
180 __raw_writel(reg, MXC_CCM_CCMR);
181
182 /* No lock bit on MX31, so using max time from spec */
183 udelay(80);
184
185 return 0;
186 }
187
188 static void serial_pll_disable(struct clk *clk)
189 {
190 u32 reg;
191
192 reg = __raw_readl(MXC_CCM_CCMR);
193 reg &= ~MXC_CCM_CCMR_SPE;
194 __raw_writel(reg, MXC_CCM_CCMR);
195 }
196
197 #define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off)
198 #define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
199 #define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
200
201 static unsigned long mcu_main_get_rate(struct clk *clk)
202 {
203 u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
204
205 if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL)
206 return clk_get_rate(&serial_pll_clk);
207 else
208 return clk_get_rate(&mcu_pll_clk);
209 }
210
211 static unsigned long ahb_get_rate(struct clk *clk)
212 {
213 unsigned long max_pdf;
214
215 max_pdf = PDR0(MXC_CCM_PDR0_MAX_PODF_MASK,
216 MXC_CCM_PDR0_MAX_PODF_OFFSET);
217 return clk_get_rate(clk->parent) / (max_pdf + 1);
218 }
219
220 static unsigned long ipg_get_rate(struct clk *clk)
221 {
222 unsigned long ipg_pdf;
223
224 ipg_pdf = PDR0(MXC_CCM_PDR0_IPG_PODF_MASK,
225 MXC_CCM_PDR0_IPG_PODF_OFFSET);
226 return clk_get_rate(clk->parent) / (ipg_pdf + 1);
227 }
228
229 static unsigned long nfc_get_rate(struct clk *clk)
230 {
231 unsigned long nfc_pdf;
232
233 nfc_pdf = PDR0(MXC_CCM_PDR0_NFC_PODF_MASK,
234 MXC_CCM_PDR0_NFC_PODF_OFFSET);
235 return clk_get_rate(clk->parent) / (nfc_pdf + 1);
236 }
237
238 static unsigned long hsp_get_rate(struct clk *clk)
239 {
240 unsigned long hsp_pdf;
241
242 hsp_pdf = PDR0(MXC_CCM_PDR0_HSP_PODF_MASK,
243 MXC_CCM_PDR0_HSP_PODF_OFFSET);
244 return clk_get_rate(clk->parent) / (hsp_pdf + 1);
245 }
246
247 static unsigned long usb_get_rate(struct clk *clk)
248 {
249 unsigned long usb_pdf, usb_prepdf;
250
251 usb_pdf = PDR1(MXC_CCM_PDR1_USB_PODF_MASK,
252 MXC_CCM_PDR1_USB_PODF_OFFSET);
253 usb_prepdf = PDR1(MXC_CCM_PDR1_USB_PRDF_MASK,
254 MXC_CCM_PDR1_USB_PRDF_OFFSET);
255 return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
256 }
257
258 static unsigned long csi_get_rate(struct clk *clk)
259 {
260 u32 reg, pre, post;
261
262 reg = __raw_readl(MXC_CCM_PDR0);
263 pre = (reg & MXC_CCM_PDR0_CSI_PRDF_MASK) >>
264 MXC_CCM_PDR0_CSI_PRDF_OFFSET;
265 pre++;
266 post = (reg & MXC_CCM_PDR0_CSI_PODF_MASK) >>
267 MXC_CCM_PDR0_CSI_PODF_OFFSET;
268 post++;
269 return clk_get_rate(clk->parent) / (pre * post);
270 }
271
272 static unsigned long csi_round_rate(struct clk *clk, unsigned long rate)
273 {
274 u32 pre, post, parent = clk_get_rate(clk->parent);
275 u32 div = parent / rate;
276
277 if (parent % rate)
278 div++;
279
280 __calc_pre_post_dividers(div, &pre, &post);
281
282 return parent / (pre * post);
283 }
284
285 static int csi_set_rate(struct clk *clk, unsigned long rate)
286 {
287 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
288
289 div = parent / rate;
290
291 if ((parent / div) != rate)
292 return -EINVAL;
293
294 __calc_pre_post_dividers(div, &pre, &post);
295
296 /* Set CSI clock divider */
297 reg = __raw_readl(MXC_CCM_PDR0) &
298 ~(MXC_CCM_PDR0_CSI_PODF_MASK | MXC_CCM_PDR0_CSI_PRDF_MASK);
299 reg |= (post - 1) << MXC_CCM_PDR0_CSI_PODF_OFFSET;
300 reg |= (pre - 1) << MXC_CCM_PDR0_CSI_PRDF_OFFSET;
301 __raw_writel(reg, MXC_CCM_PDR0);
302
303 return 0;
304 }
305
306 static unsigned long ssi1_get_rate(struct clk *clk)
307 {
308 unsigned long ssi1_pdf, ssi1_prepdf;
309
310 ssi1_pdf = PDR1(MXC_CCM_PDR1_SSI1_PODF_MASK,
311 MXC_CCM_PDR1_SSI1_PODF_OFFSET);
312 ssi1_prepdf = PDR1(MXC_CCM_PDR1_SSI1_PRE_PODF_MASK,
313 MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET);
314 return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
315 }
316
317 static unsigned long ssi2_get_rate(struct clk *clk)
318 {
319 unsigned long ssi2_pdf, ssi2_prepdf;
320
321 ssi2_pdf = PDR1(MXC_CCM_PDR1_SSI2_PODF_MASK,
322 MXC_CCM_PDR1_SSI2_PODF_OFFSET);
323 ssi2_prepdf = PDR1(MXC_CCM_PDR1_SSI2_PRE_PODF_MASK,
324 MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET);
325 return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
326 }
327
328 static unsigned long firi_get_rate(struct clk *clk)
329 {
330 unsigned long firi_pdf, firi_prepdf;
331
332 firi_pdf = PDR1(MXC_CCM_PDR1_FIRI_PODF_MASK,
333 MXC_CCM_PDR1_FIRI_PODF_OFFSET);
334 firi_prepdf = PDR1(MXC_CCM_PDR1_FIRI_PRE_PODF_MASK,
335 MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET);
336 return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
337 }
338
339 static unsigned long firi_round_rate(struct clk *clk, unsigned long rate)
340 {
341 u32 pre, post;
342 u32 parent = clk_get_rate(clk->parent);
343 u32 div = parent / rate;
344
345 if (parent % rate)
346 div++;
347
348 __calc_pre_post_dividers(div, &pre, &post);
349
350 return parent / (pre * post);
351
352 }
353
354 static int firi_set_rate(struct clk *clk, unsigned long rate)
355 {
356 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
357
358 div = parent / rate;
359
360 if ((parent / div) != rate)
361 return -EINVAL;
362
363 __calc_pre_post_dividers(div, &pre, &post);
364
365 /* Set FIRI clock divider */
366 reg = __raw_readl(MXC_CCM_PDR1) &
367 ~(MXC_CCM_PDR1_FIRI_PODF_MASK | MXC_CCM_PDR1_FIRI_PRE_PODF_MASK);
368 reg |= (pre - 1) << MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET;
369 reg |= (post - 1) << MXC_CCM_PDR1_FIRI_PODF_OFFSET;
370 __raw_writel(reg, MXC_CCM_PDR1);
371
372 return 0;
373 }
374
375 static unsigned long mbx_get_rate(struct clk *clk)
376 {
377 return clk_get_rate(clk->parent) / 2;
378 }
379
380 static unsigned long mstick1_get_rate(struct clk *clk)
381 {
382 unsigned long msti_pdf;
383
384 msti_pdf = PDR2(MXC_CCM_PDR2_MST1_PDF_MASK,
385 MXC_CCM_PDR2_MST1_PDF_OFFSET);
386 return clk_get_rate(clk->parent) / (msti_pdf + 1);
387 }
388
389 static unsigned long mstick2_get_rate(struct clk *clk)
390 {
391 unsigned long msti_pdf;
392
393 msti_pdf = PDR2(MXC_CCM_PDR2_MST2_PDF_MASK,
394 MXC_CCM_PDR2_MST2_PDF_OFFSET);
395 return clk_get_rate(clk->parent) / (msti_pdf + 1);
396 }
397
398 static unsigned long ckih_rate;
399
400 static unsigned long clk_ckih_get_rate(struct clk *clk)
401 {
402 return ckih_rate;
403 }
404
405 static struct clk ckih_clk = {
406 .get_rate = clk_ckih_get_rate,
407 };
408
409 static struct clk mcu_pll_clk = {
410 .parent = &ckih_clk,
411 .get_rate = mcu_pll_get_rate,
412 };
413
414 static struct clk mcu_main_clk = {
415 .parent = &mcu_pll_clk,
416 .get_rate = mcu_main_get_rate,
417 };
418
419 static struct clk serial_pll_clk = {
420 .parent = &ckih_clk,
421 .get_rate = serial_pll_get_rate,
422 .enable = serial_pll_enable,
423 .disable = serial_pll_disable,
424 };
425
426 static struct clk usb_pll_clk = {
427 .parent = &ckih_clk,
428 .get_rate = usb_pll_get_rate,
429 .enable = usb_pll_enable,
430 .disable = usb_pll_disable,
431 };
432
433 static struct clk ahb_clk = {
434 .parent = &mcu_main_clk,
435 .get_rate = ahb_get_rate,
436 };
437
438 #define DEFINE_CLOCK(name, i, er, es, gr, s, p) \
439 static struct clk name = { \
440 .id = i, \
441 .enable_reg = er, \
442 .enable_shift = es, \
443 .get_rate = gr, \
444 .enable = cgr_enable, \
445 .disable = cgr_disable, \
446 .secondary = s, \
447 .parent = p, \
448 }
449
450 #define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \
451 static struct clk name = { \
452 .id = i, \
453 .enable_reg = er, \
454 .enable_shift = es, \
455 .get_rate = getsetround##_get_rate, \
456 .set_rate = getsetround##_set_rate, \
457 .round_rate = getsetround##_round_rate, \
458 .enable = cgr_enable, \
459 .disable = cgr_disable, \
460 .secondary = s, \
461 .parent = p, \
462 }
463
464 DEFINE_CLOCK(perclk_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
465
466 DEFINE_CLOCK(sdhc1_clk, 0, MXC_CCM_CGR0, 0, NULL, NULL, &perclk_clk);
467 DEFINE_CLOCK(sdhc2_clk, 1, MXC_CCM_CGR0, 2, NULL, NULL, &perclk_clk);
468 DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CGR0, 4, NULL, NULL, &perclk_clk);
469 DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk);
470 DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk);
471 DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
472 DEFINE_CLOCK(ata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
473 DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, &sdma_clk1, &ahb_clk);
474 DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
475 DEFINE_CLOCK(rng_clk, 0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
476 DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk);
477 DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CGR0, 22, NULL, NULL, &perclk_clk);
478 DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CGR0, 24, ssi1_get_rate, NULL, &serial_pll_clk);
479 DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CGR0, 26, NULL, NULL, &perclk_clk);
480 DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CGR0, 28, NULL, NULL, &perclk_clk);
481 DEFINE_CLOCK(i2c3_clk, 2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk);
482
483 DEFINE_CLOCK(mpeg4_clk, 0, MXC_CCM_CGR1, 0, NULL, NULL, &ahb_clk);
484 DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1, 2, mstick1_get_rate, NULL, &usb_pll_clk);
485 DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1, 4, mstick2_get_rate, NULL, &usb_pll_clk);
486 DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &serial_pll_clk);
487 DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ipg_clk);
488 DEFINE_CLOCK(wdog_clk, 0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
489 DEFINE_CLOCK(pwm_clk, 0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
490 DEFINE_CLOCK(usb_clk2, 0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
491 DEFINE_CLOCK(kpp_clk, 0, MXC_CCM_CGR1, 20, NULL, NULL, &ipg_clk);
492 DEFINE_CLOCK(ipu_clk, 0, MXC_CCM_CGR1, 22, hsp_get_rate, NULL, &mcu_main_clk);
493 DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CGR1, 24, NULL, NULL, &perclk_clk);
494 DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CGR1, 26, NULL, NULL, &perclk_clk);
495 DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CGR1, 28, NULL, NULL, &perclk_clk);
496 DEFINE_CLOCK(owire_clk, 0, MXC_CCM_CGR1, 30, NULL, NULL, &perclk_clk);
497
498 DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CGR2, 0, ssi2_get_rate, NULL, &serial_pll_clk);
499 DEFINE_CLOCK(cspi1_clk, 0, MXC_CCM_CGR2, 2, NULL, NULL, &ipg_clk);
500 DEFINE_CLOCK(cspi2_clk, 1, MXC_CCM_CGR2, 4, NULL, NULL, &ipg_clk);
501 DEFINE_CLOCK(mbx_clk, 0, MXC_CCM_CGR2, 6, mbx_get_rate, NULL, &ahb_clk);
502 DEFINE_CLOCK(emi_clk, 0, MXC_CCM_CGR2, 8, NULL, NULL, &ahb_clk);
503 DEFINE_CLOCK(rtic_clk, 0, MXC_CCM_CGR2, 10, NULL, NULL, &ahb_clk);
504 DEFINE_CLOCK1(firi_clk, 0, MXC_CCM_CGR2, 12, firi, NULL, &usb_pll_clk);
505
506 DEFINE_CLOCK(sdma_clk2, 0, NULL, 0, NULL, NULL, &ipg_clk);
507 DEFINE_CLOCK(usb_clk1, 0, NULL, 0, usb_get_rate, NULL, &usb_pll_clk);
508 DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk);
509 DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
510 DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk);
511
512 #define _REGISTER_CLOCK(d, n, c) \
513 { \
514 .dev_id = d, \
515 .con_id = n, \
516 .clk = &c, \
517 },
518
519 static struct clk_lookup lookups[] = {
520 _REGISTER_CLOCK(NULL, "emi", emi_clk)
521 _REGISTER_CLOCK(NULL, "cspi", cspi1_clk)
522 _REGISTER_CLOCK(NULL, "cspi", cspi2_clk)
523 _REGISTER_CLOCK(NULL, "cspi", cspi3_clk)
524 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
525 _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
526 _REGISTER_CLOCK(NULL, "wdog", wdog_clk)
527 _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
528 _REGISTER_CLOCK(NULL, "epit", epit1_clk)
529 _REGISTER_CLOCK(NULL, "epit", epit2_clk)
530 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
531 _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
532 _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
533 _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
534 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
535 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
536 _REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
537 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
538 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
539 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
540 _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
541 _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
542 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
543 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
544 _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
545 _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
546 _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
547 _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
548 _REGISTER_CLOCK(NULL, "ssi", ssi1_clk)
549 _REGISTER_CLOCK(NULL, "ssi", ssi2_clk)
550 _REGISTER_CLOCK(NULL, "firi", firi_clk)
551 _REGISTER_CLOCK(NULL, "ata", ata_clk)
552 _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
553 _REGISTER_CLOCK(NULL, "rng", rng_clk)
554 _REGISTER_CLOCK(NULL, "sdma_ahb", sdma_clk1)
555 _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
556 _REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
557 _REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
558 _REGISTER_CLOCK(NULL, "scc", scc_clk)
559 _REGISTER_CLOCK(NULL, "iim", iim_clk)
560 _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
561 _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
562 };
563
564 int __init mx31_clocks_init(unsigned long fref)
565 {
566 u32 reg;
567 int i;
568
569 ckih_rate = fref;
570
571 for (i = 0; i < ARRAY_SIZE(lookups); i++)
572 clkdev_add(&lookups[i]);
573
574 /* change the csi_clk parent if necessary */
575 reg = __raw_readl(MXC_CCM_CCMR);
576 if (!(reg & MXC_CCM_CCMR_CSCS))
577 if (clk_set_parent(&csi_clk, &usb_pll_clk))
578 pr_err("%s: error changing csi_clk parent\n", __func__);
579
580
581 /* Turn off all possible clocks */
582 __raw_writel((3 << 4), MXC_CCM_CGR0);
583 __raw_writel(0, MXC_CCM_CGR1);
584 __raw_writel((3 << 8) | (3 << 14) | (3 << 16)|
585 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for
586 MX32, but still required to be set */
587 MXC_CCM_CGR2);
588
589 /*
590 * Before turning off usb_pll make sure ipg_per_clk is generated
591 * by ipg_clk and not usb_pll.
592 */
593 __raw_writel(__raw_readl(MXC_CCM_CCMR) | (1 << 24), MXC_CCM_CCMR);
594
595 usb_pll_disable(&usb_pll_clk);
596
597 pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
598
599 clk_enable(&gpt_clk);
600 clk_enable(&emi_clk);
601 clk_enable(&iim_clk);
602
603 clk_enable(&serial_pll_clk);
604
605 if (mx31_revision() >= CHIP_REV_2_0) {
606 reg = __raw_readl(MXC_CCM_PMCR1);
607 /* No PLL restart on DVFS switch; enable auto EMI handshake */
608 reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
609 __raw_writel(reg, MXC_CCM_PMCR1);
610 }
611
612 mxc_timer_init(&ipg_clk);
613
614 return 0;
615 }
616
Linux with added FPC-III support