wl1251: use wiphy_dev instead of wl->spi->dev
[linux/fpc-iii.git] / arch / arm / mach-s3c2410 / include / mach / dma.h
blobc3a2629e0ded67443455dcb3508fb3842845e473
1 /* arch/arm/mach-s3c2410/include/mach/dma.h
3 * Copyright (C) 2003,2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * Samsung S3C24XX DMA support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ASM_ARCH_DMA_H
14 #define __ASM_ARCH_DMA_H __FILE__
16 #include <plat/dma.h>
17 #include <linux/sysdev.h>
19 #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
21 /* We use `virtual` dma channels to hide the fact we have only a limited
22 * number of DMA channels, and not of all of them (dependant on the device)
23 * can be attached to any DMA source. We therefore let the DMA core handle
24 * the allocation of hardware channels to clients.
27 enum dma_ch {
28 DMACH_XD0,
29 DMACH_XD1,
30 DMACH_SDI,
31 DMACH_SPI0,
32 DMACH_SPI1,
33 DMACH_UART0,
34 DMACH_UART1,
35 DMACH_UART2,
36 DMACH_TIMER,
37 DMACH_I2S_IN,
38 DMACH_I2S_OUT,
39 DMACH_PCM_IN,
40 DMACH_PCM_OUT,
41 DMACH_MIC_IN,
42 DMACH_USB_EP1,
43 DMACH_USB_EP2,
44 DMACH_USB_EP3,
45 DMACH_USB_EP4,
46 DMACH_UART0_SRC2, /* s3c2412 second uart sources */
47 DMACH_UART1_SRC2,
48 DMACH_UART2_SRC2,
49 DMACH_UART3, /* s3c2443 has extra uart */
50 DMACH_UART3_SRC2,
51 DMACH_MAX, /* the end entry */
54 #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
56 /* we have 4 dma channels */
57 #ifndef CONFIG_CPU_S3C2443
58 #define S3C_DMA_CHANNELS (4)
59 #else
60 #define S3C_DMA_CHANNELS (6)
61 #endif
63 /* types */
65 enum s3c2410_dma_state {
66 S3C2410_DMA_IDLE,
67 S3C2410_DMA_RUNNING,
68 S3C2410_DMA_PAUSED
71 /* enum s3c2410_dma_loadst
73 * This represents the state of the DMA engine, wrt to the loaded / running
74 * transfers. Since we don't have any way of knowing exactly the state of
75 * the DMA transfers, we need to know the state to make decisions on wether
76 * we can
78 * S3C2410_DMA_NONE
80 * There are no buffers loaded (the channel should be inactive)
82 * S3C2410_DMA_1LOADED
84 * There is one buffer loaded, however it has not been confirmed to be
85 * loaded by the DMA engine. This may be because the channel is not
86 * yet running, or the DMA driver decided that it was too costly to
87 * sit and wait for it to happen.
89 * S3C2410_DMA_1RUNNING
91 * The buffer has been confirmed running, and not finisged
93 * S3C2410_DMA_1LOADED_1RUNNING
95 * There is a buffer waiting to be loaded by the DMA engine, and one
96 * currently running.
99 enum s3c2410_dma_loadst {
100 S3C2410_DMALOAD_NONE,
101 S3C2410_DMALOAD_1LOADED,
102 S3C2410_DMALOAD_1RUNNING,
103 S3C2410_DMALOAD_1LOADED_1RUNNING,
107 /* flags */
109 #define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
110 * waiting for reloads */
111 #define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
113 /* dma buffer */
115 struct s3c2410_dma_buf;
117 /* s3c2410_dma_buf
119 * internally used buffer structure to describe a queued or running
120 * buffer.
123 struct s3c2410_dma_buf {
124 struct s3c2410_dma_buf *next;
125 int magic; /* magic */
126 int size; /* buffer size in bytes */
127 dma_addr_t data; /* start of DMA data */
128 dma_addr_t ptr; /* where the DMA got to [1] */
129 void *id; /* client's id */
132 /* [1] is this updated for both recv/send modes? */
134 struct s3c2410_dma_stats {
135 unsigned long loads;
136 unsigned long timeout_longest;
137 unsigned long timeout_shortest;
138 unsigned long timeout_avg;
139 unsigned long timeout_failed;
142 struct s3c2410_dma_map;
144 /* struct s3c2410_dma_chan
146 * full state information for each DMA channel
149 struct s3c2410_dma_chan {
150 /* channel state flags and information */
151 unsigned char number; /* number of this dma channel */
152 unsigned char in_use; /* channel allocated */
153 unsigned char irq_claimed; /* irq claimed for channel */
154 unsigned char irq_enabled; /* irq enabled for channel */
155 unsigned char xfer_unit; /* size of an transfer */
157 /* channel state */
159 enum s3c2410_dma_state state;
160 enum s3c2410_dma_loadst load_state;
161 struct s3c2410_dma_client *client;
163 /* channel configuration */
164 enum s3c2410_dmasrc source;
165 enum dma_ch req_ch;
166 unsigned long dev_addr;
167 unsigned long load_timeout;
168 unsigned int flags; /* channel flags */
170 struct s3c24xx_dma_map *map; /* channel hw maps */
172 /* channel's hardware position and configuration */
173 void __iomem *regs; /* channels registers */
174 void __iomem *addr_reg; /* data address register */
175 unsigned int irq; /* channel irq */
176 unsigned long dcon; /* default value of DCON */
178 /* driver handles */
179 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
180 s3c2410_dma_opfn_t op_fn; /* channel op callback */
182 /* stats gathering */
183 struct s3c2410_dma_stats *stats;
184 struct s3c2410_dma_stats stats_store;
186 /* buffer list and information */
187 struct s3c2410_dma_buf *curr; /* current dma buffer */
188 struct s3c2410_dma_buf *next; /* next buffer to load */
189 struct s3c2410_dma_buf *end; /* end of queue */
191 /* system device */
192 struct sys_device dev;
195 typedef unsigned long dma_device_t;
197 #endif /* __ASM_ARCH_DMA_H */