1 /* arch/arm/mach-s3c2410/include/mach/map.h
3 * Copyright (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 - Memory map definitions
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ASM_ARCH_MAP_H
14 #define __ASM_ARCH_MAP_H
16 #include <plat/map-base.h>
19 #define S3C2410_ADDR(x) S3C_ADDR(x)
21 /* USB host controller */
22 #define S3C2410_PA_USBHOST (0x49000000)
25 #define S3C2410_PA_DMA (0x4B000000)
26 #define S3C24XX_SZ_DMA SZ_1M
28 /* Clock and Power management */
29 #define S3C2410_PA_CLKPWR (0x4C000000)
32 #define S3C2410_PA_LCD (0x4D000000)
33 #define S3C24XX_SZ_LCD SZ_1M
35 /* NAND flash controller */
36 #define S3C2410_PA_NAND (0x4E000000)
38 /* IIC hardware controller */
39 #define S3C2410_PA_IIC (0x54000000)
42 #define S3C2410_PA_IIS (0x55000000)
45 #define S3C2410_PA_RTC (0x57000000)
46 #define S3C24XX_SZ_RTC SZ_1M
49 #define S3C2410_PA_ADC (0x58000000)
52 #define S3C2410_PA_SPI (0x59000000)
55 #define S3C2410_PA_SDI (0x5A000000)
58 #define S3C2440_PA_CAMIF (0x4F000000)
59 #define S3C2440_SZ_CAMIF SZ_1M
63 #define S3C2440_PA_AC97 (0x5B000000)
64 #define S3C2440_SZ_AC97 SZ_1M
66 /* S3C2443 High-speed SD/MMC */
67 #define S3C2443_PA_HSMMC (0x4A800000)
68 #define S3C2443_SZ_HSMMC (256)
70 /* physical addresses of all the chip-select areas */
72 #define S3C2410_CS0 (0x00000000)
73 #define S3C2410_CS1 (0x08000000)
74 #define S3C2410_CS2 (0x10000000)
75 #define S3C2410_CS3 (0x18000000)
76 #define S3C2410_CS4 (0x20000000)
77 #define S3C2410_CS5 (0x28000000)
78 #define S3C2410_CS6 (0x30000000)
79 #define S3C2410_CS7 (0x38000000)
81 #define S3C2410_SDRAM_PA (S3C2410_CS6)
83 /* Use a single interface for common resources between S3C24XX cpus */
85 #define S3C24XX_PA_IRQ S3C2410_PA_IRQ
86 #define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
87 #define S3C24XX_PA_DMA S3C2410_PA_DMA
88 #define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
89 #define S3C24XX_PA_LCD S3C2410_PA_LCD
90 #define S3C24XX_PA_UART S3C2410_PA_UART
91 #define S3C24XX_PA_TIMER S3C2410_PA_TIMER
92 #define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
93 #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
94 #define S3C24XX_PA_IIS S3C2410_PA_IIS
95 #define S3C24XX_PA_GPIO S3C2410_PA_GPIO
96 #define S3C24XX_PA_RTC S3C2410_PA_RTC
97 #define S3C24XX_PA_ADC S3C2410_PA_ADC
98 #define S3C24XX_PA_SPI S3C2410_PA_SPI
99 #define S3C24XX_PA_SDI S3C2410_PA_SDI
100 #define S3C24XX_PA_NAND S3C2410_PA_NAND
102 #define S3C_PA_IIC S3C2410_PA_IIC
103 #define S3C_PA_UART S3C24XX_PA_UART
104 #define S3C_PA_USBHOST S3C2410_PA_USBHOST
105 #define S3C_PA_HSMMC0 S3C2443_PA_HSMMC
107 #endif /* __ASM_ARCH_MAP_H */