| blob | 0fe1f8fc348802777a02e42da50c58f56e2a2d9e |
1 /*
2 * linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
3 *
4 * Heavily based on proc-arm926.S
5 * Maintainer: Assaf Hoffman <hoffman@marvell.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
22 #include <linux/linkage.h>
23 #include <linux/init.h>
24 #include <asm/assembler.h>
25 #include <asm/hwcap.h>
26 #include <asm/pgtable-hwdef.h>
27 #include <asm/pgtable.h>
28 #include <asm/page.h>
29 #include <asm/ptrace.h>
30 #include "proc-macros.S"
32 /*
33 * This is the maximum size of an area which will be invalidated
34 * using the single invalidate entry instructions. Anything larger
35 * than this, and we go for the whole cache.
36 *
37 * This value should be chosen such that we choose the cheapest
38 * alternative.
39 */
40 #define CACHE_DLIMIT 16384
42 /*
43 * the cache line size of the I and D cache
44 */
45 #define CACHE_DLINESIZE 32
47 .bss
48 .align 3
49 __cache_params_loc:
50 .space 8
52 .text
53 __cache_params:
54 .word __cache_params_loc
56 /*
57 * cpu_feroceon_proc_init()
58 */
59 ENTRY(cpu_feroceon_proc_init)
60 mrc p15, 0, r0, c0, c0, 1 @ read cache type register
61 ldr r1, __cache_params
62 mov r2, #(16 << 5)
63 tst r0, #(1 << 16) @ get way
64 mov r0, r0, lsr #18 @ get cache size order
65 movne r3, #((4 - 1) << 30) @ 4-way
66 and r0, r0, #0xf
67 moveq r3, #0 @ 1-way
68 mov r2, r2, lsl r0 @ actual cache size
69 movne r2, r2, lsr #2 @ turned into # of sets
70 sub r2, r2, #(1 << 5)
71 stmia r1, {r2, r3}
72 mov pc, lr
74 /*
75 * cpu_feroceon_proc_fin()
76 */
77 ENTRY(cpu_feroceon_proc_fin)
78 stmfd sp!, {lr}
79 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
80 msr cpsr_c, ip
81 bl feroceon_flush_kern_cache_all
83 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
84 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
85 mov r0, #0
86 mcr p15, 1, r0, c15, c9, 0 @ clean L2
87 mcr p15, 0, r0, c7, c10, 4 @ drain WB
88 #endif
90 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
91 bic r0, r0, #0x1000 @ ...i............
92 bic r0, r0, #0x000e @ ............wca.
93 mcr p15, 0, r0, c1, c0, 0 @ disable caches
94 ldmfd sp!, {pc}
96 /*
97 * cpu_feroceon_reset(loc)
98 *
99 * Perform a soft reset of the system. Put the CPU into the
100 * same state as it would be if it had been reset, and branch
101 * to what would be the reset vector.
102 *
103 * loc: location to jump to for soft reset
104 */
105 .align 5
106 ENTRY(cpu_feroceon_reset)
107 mov ip, #0
108 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
109 mcr p15, 0, ip, c7, c10, 4 @ drain WB
110 #ifdef CONFIG_MMU
111 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
112 #endif
113 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
114 bic ip, ip, #0x000f @ ............wcam
115 bic ip, ip, #0x1100 @ ...i...s........
116 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
117 mov pc, r0
119 /*
120 * cpu_feroceon_do_idle()
121 *
122 * Called with IRQs disabled
123 */
124 .align 5
125 ENTRY(cpu_feroceon_do_idle)
126 mov r0, #0
127 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
128 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
129 mov pc, lr
131 /*
132 * flush_user_cache_all()
133 *
134 * Clean and invalidate all cache entries in a particular
135 * address space.
136 */
137 .align 5
138 ENTRY(feroceon_flush_user_cache_all)
139 /* FALLTHROUGH */
141 /*
142 * flush_kern_cache_all()
143 *
144 * Clean and invalidate the entire cache.
145 */
146 ENTRY(feroceon_flush_kern_cache_all)
147 mov r2, #VM_EXEC
149 __flush_whole_cache:
150 ldr r1, __cache_params
151 ldmia r1, {r1, r3}
152 1: orr ip, r1, r3
153 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
154 subs ip, ip, #(1 << 30) @ next way
155 bcs 2b
156 subs r1, r1, #(1 << 5) @ next set
157 bcs 1b
159 tst r2, #VM_EXEC
160 mov ip, #0
161 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
162 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
163 mov pc, lr
165 /*
166 * flush_user_cache_range(start, end, flags)
167 *
168 * Clean and invalidate a range of cache entries in the
169 * specified address range.
170 *
171 * - start - start address (inclusive)
172 * - end - end address (exclusive)
173 * - flags - vm_flags describing address space
174 */
175 .align 5
176 ENTRY(feroceon_flush_user_cache_range)
177 sub r3, r1, r0 @ calculate total size
178 cmp r3, #CACHE_DLIMIT
179 bgt __flush_whole_cache
180 1: tst r2, #VM_EXEC
181 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
182 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
183 add r0, r0, #CACHE_DLINESIZE
184 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
185 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
186 add r0, r0, #CACHE_DLINESIZE
187 cmp r0, r1
188 blo 1b
189 tst r2, #VM_EXEC
190 mov ip, #0
191 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
192 mov pc, lr
194 /*
195 * coherent_kern_range(start, end)
196 *
197 * Ensure coherency between the Icache and the Dcache in the
198 * region described by start, end. If you have non-snooping
199 * Harvard caches, you need to implement this function.
200 *
201 * - start - virtual start address
202 * - end - virtual end address
203 */
204 .align 5
205 ENTRY(feroceon_coherent_kern_range)
206 /* FALLTHROUGH */
208 /*
209 * coherent_user_range(start, end)
210 *
211 * Ensure coherency between the Icache and the Dcache in the
212 * region described by start, end. If you have non-snooping
213 * Harvard caches, you need to implement this function.
214 *
215 * - start - virtual start address
216 * - end - virtual end address
217 */
218 ENTRY(feroceon_coherent_user_range)
219 bic r0, r0, #CACHE_DLINESIZE - 1
220 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
221 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
222 add r0, r0, #CACHE_DLINESIZE
223 cmp r0, r1
224 blo 1b
225 mcr p15, 0, r0, c7, c10, 4 @ drain WB
226 mov pc, lr
228 /*
229 * flush_kern_dcache_page(void *page)
230 *
231 * Ensure no D cache aliasing occurs, either with itself or
232 * the I cache
233 *
234 * - addr - page aligned address
235 */
236 .align 5
237 ENTRY(feroceon_flush_kern_dcache_page)
238 add r1, r0, #PAGE_SZ
239 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
240 add r0, r0, #CACHE_DLINESIZE
241 cmp r0, r1
242 blo 1b
243 mov r0, #0
244 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
245 mcr p15, 0, r0, c7, c10, 4 @ drain WB
246 mov pc, lr
248 .align 5
249 ENTRY(feroceon_range_flush_kern_dcache_page)
250 mrs r2, cpsr
251 add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive
252 orr r3, r2, #PSR_I_BIT
253 msr cpsr_c, r3 @ disable interrupts
254 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
255 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
256 msr cpsr_c, r2 @ restore interrupts
257 mov r0, #0
258 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
259 mcr p15, 0, r0, c7, c10, 4 @ drain WB
260 mov pc, lr
262 /*
263 * dma_inv_range(start, end)
264 *
265 * Invalidate (discard) the specified virtual address range.
266 * May not write back any entries. If 'start' or 'end'
267 * are not cache line aligned, those lines must be written
268 * back.
269 *
270 * - start - virtual start address
271 * - end - virtual end address
272 *
273 * (same as v4wb)
274 */
275 .align 5
276 ENTRY(feroceon_dma_inv_range)
277 tst r0, #CACHE_DLINESIZE - 1
278 bic r0, r0, #CACHE_DLINESIZE - 1
279 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
280 tst r1, #CACHE_DLINESIZE - 1
281 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
282 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
283 add r0, r0, #CACHE_DLINESIZE
284 cmp r0, r1
285 blo 1b
286 mcr p15, 0, r0, c7, c10, 4 @ drain WB
287 mov pc, lr
289 .align 5
290 ENTRY(feroceon_range_dma_inv_range)
291 mrs r2, cpsr
292 tst r0, #CACHE_DLINESIZE - 1
293 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
294 tst r1, #CACHE_DLINESIZE - 1
295 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
296 cmp r1, r0
297 subne r1, r1, #1 @ top address is inclusive
298 orr r3, r2, #PSR_I_BIT
299 msr cpsr_c, r3 @ disable interrupts
300 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
301 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
302 msr cpsr_c, r2 @ restore interrupts
303 mov pc, lr
305 /*
306 * dma_clean_range(start, end)
307 *
308 * Clean the specified virtual address range.
309 *
310 * - start - virtual start address
311 * - end - virtual end address
312 *
313 * (same as v4wb)
314 */
315 .align 5
316 ENTRY(feroceon_dma_clean_range)
317 bic r0, r0, #CACHE_DLINESIZE - 1
318 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
319 add r0, r0, #CACHE_DLINESIZE
320 cmp r0, r1
321 blo 1b
322 mcr p15, 0, r0, c7, c10, 4 @ drain WB
323 mov pc, lr
325 .align 5
326 ENTRY(feroceon_range_dma_clean_range)
327 mrs r2, cpsr
328 cmp r1, r0
329 subne r1, r1, #1 @ top address is inclusive
330 orr r3, r2, #PSR_I_BIT
331 msr cpsr_c, r3 @ disable interrupts
332 mcr p15, 5, r0, c15, c13, 0 @ D clean range start
333 mcr p15, 5, r1, c15, c13, 1 @ D clean range top
334 msr cpsr_c, r2 @ restore interrupts
335 mcr p15, 0, r0, c7, c10, 4 @ drain WB
336 mov pc, lr
338 /*
339 * dma_flush_range(start, end)
340 *
341 * Clean and invalidate the specified virtual address range.
342 *
343 * - start - virtual start address
344 * - end - virtual end address
345 */
346 .align 5
347 ENTRY(feroceon_dma_flush_range)
348 bic r0, r0, #CACHE_DLINESIZE - 1
349 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
350 add r0, r0, #CACHE_DLINESIZE
351 cmp r0, r1
352 blo 1b
353 mcr p15, 0, r0, c7, c10, 4 @ drain WB
354 mov pc, lr
356 .align 5
357 ENTRY(feroceon_range_dma_flush_range)
358 mrs r2, cpsr
359 cmp r1, r0
360 subne r1, r1, #1 @ top address is inclusive
361 orr r3, r2, #PSR_I_BIT
362 msr cpsr_c, r3 @ disable interrupts
363 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
364 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
365 msr cpsr_c, r2 @ restore interrupts
366 mcr p15, 0, r0, c7, c10, 4 @ drain WB
367 mov pc, lr
369 ENTRY(feroceon_cache_fns)
370 .long feroceon_flush_kern_cache_all
371 .long feroceon_flush_user_cache_all
372 .long feroceon_flush_user_cache_range
373 .long feroceon_coherent_kern_range
374 .long feroceon_coherent_user_range
375 .long feroceon_flush_kern_dcache_page
376 .long feroceon_dma_inv_range
377 .long feroceon_dma_clean_range
378 .long feroceon_dma_flush_range
380 ENTRY(feroceon_range_cache_fns)
381 .long feroceon_flush_kern_cache_all
382 .long feroceon_flush_user_cache_all
383 .long feroceon_flush_user_cache_range
384 .long feroceon_coherent_kern_range
385 .long feroceon_coherent_user_range
386 .long feroceon_range_flush_kern_dcache_page
387 .long feroceon_range_dma_inv_range
388 .long feroceon_range_dma_clean_range
389 .long feroceon_range_dma_flush_range
391 .align 5
392 ENTRY(cpu_feroceon_dcache_clean_area)
393 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
394 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
395 mov r2, r0
396 mov r3, r1
397 #endif
398 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
399 add r0, r0, #CACHE_DLINESIZE
400 subs r1, r1, #CACHE_DLINESIZE
401 bhi 1b
402 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
403 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
404 1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry
405 add r2, r2, #CACHE_DLINESIZE
406 subs r3, r3, #CACHE_DLINESIZE
407 bhi 1b
408 #endif
409 mcr p15, 0, r0, c7, c10, 4 @ drain WB
410 mov pc, lr
412 /* =============================== PageTable ============================== */
414 /*
415 * cpu_feroceon_switch_mm(pgd)
416 *
417 * Set the translation base pointer to be as described by pgd.
418 *
419 * pgd: new page tables
420 */
421 .align 5
422 ENTRY(cpu_feroceon_switch_mm)
423 #ifdef CONFIG_MMU
424 /*
425 * Note: we wish to call __flush_whole_cache but we need to preserve
426 * lr to do so. The only way without touching main memory is to
427 * use r2 which is normally used to test the VM_EXEC flag, and
428 * compensate locally for the skipped ops if it is not set.
429 */
430 mov r2, lr @ abuse r2 to preserve lr
431 bl __flush_whole_cache
432 @ if r2 contains the VM_EXEC bit then the next 2 ops are done already
433 tst r2, #VM_EXEC
434 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
435 mcreq p15, 0, ip, c7, c10, 4 @ drain WB
437 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
438 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
439 mov pc, r2
440 #else
441 mov pc, lr
442 #endif
444 /*
445 * cpu_feroceon_set_pte_ext(ptep, pte, ext)
446 *
447 * Set a PTE and flush it out
448 */
449 .align 5
450 ENTRY(cpu_feroceon_set_pte_ext)
451 #ifdef CONFIG_MMU
452 armv3_set_pte_ext wc_disable=0
453 mov r0, r0
454 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
455 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
456 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
457 mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry
458 #endif
459 mcr p15, 0, r0, c7, c10, 4 @ drain WB
460 #endif
461 mov pc, lr
463 __INIT
465 .type __feroceon_setup, #function
466 __feroceon_setup:
467 mov r0, #0
468 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
469 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
470 #ifdef CONFIG_MMU
471 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
472 #endif
474 adr r5, feroceon_crval
475 ldmia r5, {r5, r6}
476 mrc p15, 0, r0, c1, c0 @ get control register v4
477 bic r0, r0, r5
478 orr r0, r0, r6
479 mov pc, lr
480 .size __feroceon_setup, . - __feroceon_setup
482 /*
483 * B
484 * R P
485 * .RVI UFRS BLDP WCAM
486 * .011 .001 ..11 0101
487 *
488 */
489 .type feroceon_crval, #object
490 feroceon_crval:
491 crval clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134
493 __INITDATA
495 /*
496 * Purpose : Function pointers used to access above functions - all calls
497 * come through these
498 */
499 .type feroceon_processor_functions, #object
500 feroceon_processor_functions:
501 .word v5t_early_abort
502 .word pabort_noifar
503 .word cpu_feroceon_proc_init
504 .word cpu_feroceon_proc_fin
505 .word cpu_feroceon_reset
506 .word cpu_feroceon_do_idle
507 .word cpu_feroceon_dcache_clean_area
508 .word cpu_feroceon_switch_mm
509 .word cpu_feroceon_set_pte_ext
510 .size feroceon_processor_functions, . - feroceon_processor_functions
512 .section ".rodata"
514 .type cpu_arch_name, #object
515 cpu_arch_name:
516 .asciz "armv5te"
517 .size cpu_arch_name, . - cpu_arch_name
519 .type cpu_elf_name, #object
520 cpu_elf_name:
521 .asciz "v5"
522 .size cpu_elf_name, . - cpu_elf_name
524 .type cpu_feroceon_name, #object
525 cpu_feroceon_name:
526 .asciz "Feroceon"
527 .size cpu_feroceon_name, . - cpu_feroceon_name
529 .type cpu_88fr531_name, #object
530 cpu_88fr531_name:
531 .asciz "Feroceon 88FR531-vd"
532 .size cpu_88fr531_name, . - cpu_88fr531_name
534 .type cpu_88fr571_name, #object
535 cpu_88fr571_name:
536 .asciz "Feroceon 88FR571-vd"
537 .size cpu_88fr571_name, . - cpu_88fr571_name
539 .type cpu_88fr131_name, #object
540 cpu_88fr131_name:
541 .asciz "Feroceon 88FR131"
542 .size cpu_88fr131_name, . - cpu_88fr131_name
544 .align
546 .section ".proc.info.init", #alloc, #execinstr
548 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
549 .type __feroceon_old_id_proc_info,#object
550 __feroceon_old_id_proc_info:
551 .long 0x41009260
552 .long 0xff00fff0
553 .long PMD_TYPE_SECT | \
554 PMD_SECT_BUFFERABLE | \
555 PMD_SECT_CACHEABLE | \
556 PMD_BIT4 | \
557 PMD_SECT_AP_WRITE | \
558 PMD_SECT_AP_READ
559 .long PMD_TYPE_SECT | \
560 PMD_BIT4 | \
561 PMD_SECT_AP_WRITE | \
562 PMD_SECT_AP_READ
563 b __feroceon_setup
564 .long cpu_arch_name
565 .long cpu_elf_name
566 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
567 .long cpu_feroceon_name
568 .long feroceon_processor_functions
569 .long v4wbi_tlb_fns
570 .long feroceon_user_fns
571 .long feroceon_cache_fns
572 .size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
573 #endif
575 .type __88fr531_proc_info,#object
576 __88fr531_proc_info:
577 .long 0x56055310
578 .long 0xfffffff0
579 .long PMD_TYPE_SECT | \
580 PMD_SECT_BUFFERABLE | \
581 PMD_SECT_CACHEABLE | \
582 PMD_BIT4 | \
583 PMD_SECT_AP_WRITE | \
584 PMD_SECT_AP_READ
585 .long PMD_TYPE_SECT | \
586 PMD_BIT4 | \
587 PMD_SECT_AP_WRITE | \
588 PMD_SECT_AP_READ
589 b __feroceon_setup
590 .long cpu_arch_name
591 .long cpu_elf_name
592 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
593 .long cpu_88fr531_name
594 .long feroceon_processor_functions
595 .long v4wbi_tlb_fns
596 .long feroceon_user_fns
597 .long feroceon_cache_fns
598 .size __88fr531_proc_info, . - __88fr531_proc_info
600 .type __88fr571_proc_info,#object
601 __88fr571_proc_info:
602 .long 0x56155710
603 .long 0xfffffff0
604 .long PMD_TYPE_SECT | \
605 PMD_SECT_BUFFERABLE | \
606 PMD_SECT_CACHEABLE | \
607 PMD_BIT4 | \
608 PMD_SECT_AP_WRITE | \
609 PMD_SECT_AP_READ
610 .long PMD_TYPE_SECT | \
611 PMD_BIT4 | \
612 PMD_SECT_AP_WRITE | \
613 PMD_SECT_AP_READ
614 b __feroceon_setup
615 .long cpu_arch_name
616 .long cpu_elf_name
617 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
618 .long cpu_88fr571_name
619 .long feroceon_processor_functions
620 .long v4wbi_tlb_fns
621 .long feroceon_user_fns
622 .long feroceon_range_cache_fns
623 .size __88fr571_proc_info, . - __88fr571_proc_info
625 .type __88fr131_proc_info,#object
626 __88fr131_proc_info:
627 .long 0x56251310
628 .long 0xfffffff0
629 .long PMD_TYPE_SECT | \
630 PMD_SECT_BUFFERABLE | \
631 PMD_SECT_CACHEABLE | \
632 PMD_BIT4 | \
633 PMD_SECT_AP_WRITE | \
634 PMD_SECT_AP_READ
635 .long PMD_TYPE_SECT | \
636 PMD_BIT4 | \
637 PMD_SECT_AP_WRITE | \
638 PMD_SECT_AP_READ
639 b __feroceon_setup
640 .long cpu_arch_name
641 .long cpu_elf_name
642 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
643 .long cpu_88fr131_name
644 .long feroceon_processor_functions
645 .long v4wbi_tlb_fns
646 .long feroceon_user_fns
647 .long feroceon_range_cache_fns
648 .size __88fr131_proc_info, . - __88fr131_proc_info