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wl1251: use wiphy_dev instead of wl->spi->dev
[linux/fpc-iii.git] / arch / arm / plat-omap / dma.c
blob7677a4a1cef26f0df05e5db328cf7134bd27e0ee
1 /*
2 * linux/arch/arm/plat-omap/dma.c
3 *
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 *
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 *
16 * Support functions for the OMAP internal DMA channels.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/sched.h>
27 #include <linux/spinlock.h>
28 #include <linux/errno.h>
29 #include <linux/interrupt.h>
30 #include <linux/irq.h>
31 #include <linux/io.h>
32
33 #include <asm/system.h>
34 #include <mach/hardware.h>
35 #include <mach/dma.h>
36
37 #include <mach/tc.h>
38
39 #undef DEBUG
40
41 #ifndef CONFIG_ARCH_OMAP1
42 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
43 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
44 };
45
46 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
47 #endif
48
49 #define OMAP_DMA_ACTIVE 0x01
50 #define OMAP_DMA_CCR_EN (1 << 7)
51 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
52
53 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
54
55 static int enable_1510_mode;
56
57 struct omap_dma_lch {
58 int next_lch;
59 int dev_id;
60 u16 saved_csr;
61 u16 enabled_irqs;
62 const char *dev_name;
63 void (*callback)(int lch, u16 ch_status, void *data);
64 void *data;
65
66 #ifndef CONFIG_ARCH_OMAP1
67 /* required for Dynamic chaining */
68 int prev_linked_ch;
69 int next_linked_ch;
70 int state;
71 int chain_id;
72
73 int status;
74 #endif
75 long flags;
76 };
77
78 struct dma_link_info {
79 int *linked_dmach_q;
80 int no_of_lchs_linked;
81
82 int q_count;
83 int q_tail;
84 int q_head;
85
86 int chain_state;
87 int chain_mode;
88
89 };
90
91 static struct dma_link_info *dma_linked_lch;
92
93 #ifndef CONFIG_ARCH_OMAP1
94
95 /* Chain handling macros */
96 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
97 do { \
98 dma_linked_lch[chain_id].q_head = \
99 dma_linked_lch[chain_id].q_tail = \
100 dma_linked_lch[chain_id].q_count = 0; \
101 } while (0)
102 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
103 (dma_linked_lch[chain_id].no_of_lchs_linked == \
104 dma_linked_lch[chain_id].q_count)
105 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
106 do { \
107 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
108 dma_linked_lch[chain_id].q_count) \
109 } while (0)
110 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
111 (0 == dma_linked_lch[chain_id].q_count)
112 #define __OMAP_DMA_CHAIN_INCQ(end) \
113 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
114 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
115 do { \
116 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
117 dma_linked_lch[chain_id].q_count--; \
118 } while (0)
119
120 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
121 do { \
122 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
123 dma_linked_lch[chain_id].q_count++; \
124 } while (0)
125 #endif
126
127 static int dma_lch_count;
128 static int dma_chan_count;
129 static int omap_dma_reserve_channels;
130
131 static spinlock_t dma_chan_lock;
132 static struct omap_dma_lch *dma_chan;
133 static void __iomem *omap_dma_base;
134
135 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
136 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
137 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
138 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
139 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
140 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
141 };
142
143 static inline void disable_lnk(int lch);
144 static void omap_disable_channel_irq(int lch);
145 static inline void omap_enable_channel_irq(int lch);
146
147 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
148 __func__);
149
150 #define dma_read(reg) \
151 ({ \
152 u32 __val; \
153 if (cpu_class_is_omap1()) \
154 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
155 else \
156 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
157 __val; \
158 })
159
160 #define dma_write(val, reg) \
161 ({ \
162 if (cpu_class_is_omap1()) \
163 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
164 else \
165 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
166 })
167
168 #ifdef CONFIG_ARCH_OMAP15XX
169 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
170 int omap_dma_in_1510_mode(void)
171 {
172 return enable_1510_mode;
173 }
174 #else
175 #define omap_dma_in_1510_mode() 0
176 #endif
177
178 #ifdef CONFIG_ARCH_OMAP1
179 static inline int get_gdma_dev(int req)
180 {
181 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
182 int shift = ((req - 1) % 5) * 6;
183
184 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
185 }
186
187 static inline void set_gdma_dev(int req, int dev)
188 {
189 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
190 int shift = ((req - 1) % 5) * 6;
191 u32 l;
192
193 l = omap_readl(reg);
194 l &= ~(0x3f << shift);
195 l |= (dev - 1) << shift;
196 omap_writel(l, reg);
197 }
198 #else
199 #define set_gdma_dev(req, dev) do {} while (0)
200 #endif
201
202 /* Omap1 only */
203 static void clear_lch_regs(int lch)
204 {
205 int i;
206 void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
207
208 for (i = 0; i < 0x2c; i += 2)
209 __raw_writew(0, lch_base + i);
210 }
211
212 void omap_set_dma_priority(int lch, int dst_port, int priority)
213 {
214 unsigned long reg;
215 u32 l;
216
217 if (cpu_class_is_omap1()) {
218 switch (dst_port) {
219 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
220 reg = OMAP_TC_OCPT1_PRIOR;
221 break;
222 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
223 reg = OMAP_TC_OCPT2_PRIOR;
224 break;
225 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
226 reg = OMAP_TC_EMIFF_PRIOR;
227 break;
228 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
229 reg = OMAP_TC_EMIFS_PRIOR;
230 break;
231 default:
232 BUG();
233 return;
234 }
235 l = omap_readl(reg);
236 l &= ~(0xf << 8);
237 l |= (priority & 0xf) << 8;
238 omap_writel(l, reg);
239 }
240
241 if (cpu_class_is_omap2()) {
242 u32 ccr;
243
244 ccr = dma_read(CCR(lch));
245 if (priority)
246 ccr |= (1 << 6);
247 else
248 ccr &= ~(1 << 6);
249 dma_write(ccr, CCR(lch));
250 }
251 }
252 EXPORT_SYMBOL(omap_set_dma_priority);
253
254 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
255 int frame_count, int sync_mode,
256 int dma_trigger, int src_or_dst_synch)
257 {
258 u32 l;
259
260 l = dma_read(CSDP(lch));
261 l &= ~0x03;
262 l |= data_type;
263 dma_write(l, CSDP(lch));
264
265 if (cpu_class_is_omap1()) {
266 u16 ccr;
267
268 ccr = dma_read(CCR(lch));
269 ccr &= ~(1 << 5);
270 if (sync_mode == OMAP_DMA_SYNC_FRAME)
271 ccr |= 1 << 5;
272 dma_write(ccr, CCR(lch));
273
274 ccr = dma_read(CCR2(lch));
275 ccr &= ~(1 << 2);
276 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
277 ccr |= 1 << 2;
278 dma_write(ccr, CCR2(lch));
279 }
280
281 if (cpu_class_is_omap2() && dma_trigger) {
282 u32 val;
283
284 val = dma_read(CCR(lch));
285
286 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
287 val &= ~((3 << 19) | 0x1f);
288 val |= (dma_trigger & ~0x1f) << 14;
289 val |= dma_trigger & 0x1f;
290
291 if (sync_mode & OMAP_DMA_SYNC_FRAME)
292 val |= 1 << 5;
293 else
294 val &= ~(1 << 5);
295
296 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
297 val |= 1 << 18;
298 else
299 val &= ~(1 << 18);
300
301 if (src_or_dst_synch)
302 val |= 1 << 24; /* source synch */
303 else
304 val &= ~(1 << 24); /* dest synch */
305
306 dma_write(val, CCR(lch));
307 }
308
309 dma_write(elem_count, CEN(lch));
310 dma_write(frame_count, CFN(lch));
311 }
312 EXPORT_SYMBOL(omap_set_dma_transfer_params);
313
314 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
315 {
316 BUG_ON(omap_dma_in_1510_mode());
317
318 if (cpu_class_is_omap1()) {
319 u16 w;
320
321 w = dma_read(CCR2(lch));
322 w &= ~0x03;
323
324 switch (mode) {
325 case OMAP_DMA_CONSTANT_FILL:
326 w |= 0x01;
327 break;
328 case OMAP_DMA_TRANSPARENT_COPY:
329 w |= 0x02;
330 break;
331 case OMAP_DMA_COLOR_DIS:
332 break;
333 default:
334 BUG();
335 }
336 dma_write(w, CCR2(lch));
337
338 w = dma_read(LCH_CTRL(lch));
339 w &= ~0x0f;
340 /* Default is channel type 2D */
341 if (mode) {
342 dma_write((u16)color, COLOR_L(lch));
343 dma_write((u16)(color >> 16), COLOR_U(lch));
344 w |= 1; /* Channel type G */
345 }
346 dma_write(w, LCH_CTRL(lch));
347 }
348
349 if (cpu_class_is_omap2()) {
350 u32 val;
351
352 val = dma_read(CCR(lch));
353 val &= ~((1 << 17) | (1 << 16));
354
355 switch (mode) {
356 case OMAP_DMA_CONSTANT_FILL:
357 val |= 1 << 16;
358 break;
359 case OMAP_DMA_TRANSPARENT_COPY:
360 val |= 1 << 17;
361 break;
362 case OMAP_DMA_COLOR_DIS:
363 break;
364 default:
365 BUG();
366 }
367 dma_write(val, CCR(lch));
368
369 color &= 0xffffff;
370 dma_write(color, COLOR(lch));
371 }
372 }
373 EXPORT_SYMBOL(omap_set_dma_color_mode);
374
375 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
376 {
377 if (cpu_class_is_omap2()) {
378 u32 csdp;
379
380 csdp = dma_read(CSDP(lch));
381 csdp &= ~(0x3 << 16);
382 csdp |= (mode << 16);
383 dma_write(csdp, CSDP(lch));
384 }
385 }
386 EXPORT_SYMBOL(omap_set_dma_write_mode);
387
388 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
389 {
390 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
391 u32 l;
392
393 l = dma_read(LCH_CTRL(lch));
394 l &= ~0x7;
395 l |= mode;
396 dma_write(l, LCH_CTRL(lch));
397 }
398 }
399 EXPORT_SYMBOL(omap_set_dma_channel_mode);
400
401 /* Note that src_port is only for omap1 */
402 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
403 unsigned long src_start,
404 int src_ei, int src_fi)
405 {
406 u32 l;
407
408 if (cpu_class_is_omap1()) {
409 u16 w;
410
411 w = dma_read(CSDP(lch));
412 w &= ~(0x1f << 2);
413 w |= src_port << 2;
414 dma_write(w, CSDP(lch));
415 }
416
417 l = dma_read(CCR(lch));
418 l &= ~(0x03 << 12);
419 l |= src_amode << 12;
420 dma_write(l, CCR(lch));
421
422 if (cpu_class_is_omap1()) {
423 dma_write(src_start >> 16, CSSA_U(lch));
424 dma_write((u16)src_start, CSSA_L(lch));
425 }
426
427 if (cpu_class_is_omap2())
428 dma_write(src_start, CSSA(lch));
429
430 dma_write(src_ei, CSEI(lch));
431 dma_write(src_fi, CSFI(lch));
432 }
433 EXPORT_SYMBOL(omap_set_dma_src_params);
434
435 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
436 {
437 omap_set_dma_transfer_params(lch, params->data_type,
438 params->elem_count, params->frame_count,
439 params->sync_mode, params->trigger,
440 params->src_or_dst_synch);
441 omap_set_dma_src_params(lch, params->src_port,
442 params->src_amode, params->src_start,
443 params->src_ei, params->src_fi);
444
445 omap_set_dma_dest_params(lch, params->dst_port,
446 params->dst_amode, params->dst_start,
447 params->dst_ei, params->dst_fi);
448 if (params->read_prio || params->write_prio)
449 omap_dma_set_prio_lch(lch, params->read_prio,
450 params->write_prio);
451 }
452 EXPORT_SYMBOL(omap_set_dma_params);
453
454 void omap_set_dma_src_index(int lch, int eidx, int fidx)
455 {
456 if (cpu_class_is_omap2())
457 return;
458
459 dma_write(eidx, CSEI(lch));
460 dma_write(fidx, CSFI(lch));
461 }
462 EXPORT_SYMBOL(omap_set_dma_src_index);
463
464 void omap_set_dma_src_data_pack(int lch, int enable)
465 {
466 u32 l;
467
468 l = dma_read(CSDP(lch));
469 l &= ~(1 << 6);
470 if (enable)
471 l |= (1 << 6);
472 dma_write(l, CSDP(lch));
473 }
474 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
475
476 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
477 {
478 unsigned int burst = 0;
479 u32 l;
480
481 l = dma_read(CSDP(lch));
482 l &= ~(0x03 << 7);
483
484 switch (burst_mode) {
485 case OMAP_DMA_DATA_BURST_DIS:
486 break;
487 case OMAP_DMA_DATA_BURST_4:
488 if (cpu_class_is_omap2())
489 burst = 0x1;
490 else
491 burst = 0x2;
492 break;
493 case OMAP_DMA_DATA_BURST_8:
494 if (cpu_class_is_omap2()) {
495 burst = 0x2;
496 break;
497 }
498 /* not supported by current hardware on OMAP1
499 * w |= (0x03 << 7);
500 * fall through
501 */
502 case OMAP_DMA_DATA_BURST_16:
503 if (cpu_class_is_omap2()) {
504 burst = 0x3;
505 break;
506 }
507 /* OMAP1 don't support burst 16
508 * fall through
509 */
510 default:
511 BUG();
512 }
513
514 l |= (burst << 7);
515 dma_write(l, CSDP(lch));
516 }
517 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
518
519 /* Note that dest_port is only for OMAP1 */
520 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
521 unsigned long dest_start,
522 int dst_ei, int dst_fi)
523 {
524 u32 l;
525
526 if (cpu_class_is_omap1()) {
527 l = dma_read(CSDP(lch));
528 l &= ~(0x1f << 9);
529 l |= dest_port << 9;
530 dma_write(l, CSDP(lch));
531 }
532
533 l = dma_read(CCR(lch));
534 l &= ~(0x03 << 14);
535 l |= dest_amode << 14;
536 dma_write(l, CCR(lch));
537
538 if (cpu_class_is_omap1()) {
539 dma_write(dest_start >> 16, CDSA_U(lch));
540 dma_write(dest_start, CDSA_L(lch));
541 }
542
543 if (cpu_class_is_omap2())
544 dma_write(dest_start, CDSA(lch));
545
546 dma_write(dst_ei, CDEI(lch));
547 dma_write(dst_fi, CDFI(lch));
548 }
549 EXPORT_SYMBOL(omap_set_dma_dest_params);
550
551 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
552 {
553 if (cpu_class_is_omap2())
554 return;
555
556 dma_write(eidx, CDEI(lch));
557 dma_write(fidx, CDFI(lch));
558 }
559 EXPORT_SYMBOL(omap_set_dma_dest_index);
560
561 void omap_set_dma_dest_data_pack(int lch, int enable)
562 {
563 u32 l;
564
565 l = dma_read(CSDP(lch));
566 l &= ~(1 << 13);
567 if (enable)
568 l |= 1 << 13;
569 dma_write(l, CSDP(lch));
570 }
571 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
572
573 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
574 {
575 unsigned int burst = 0;
576 u32 l;
577
578 l = dma_read(CSDP(lch));
579 l &= ~(0x03 << 14);
580
581 switch (burst_mode) {
582 case OMAP_DMA_DATA_BURST_DIS:
583 break;
584 case OMAP_DMA_DATA_BURST_4:
585 if (cpu_class_is_omap2())
586 burst = 0x1;
587 else
588 burst = 0x2;
589 break;
590 case OMAP_DMA_DATA_BURST_8:
591 if (cpu_class_is_omap2())
592 burst = 0x2;
593 else
594 burst = 0x3;
595 break;
596 case OMAP_DMA_DATA_BURST_16:
597 if (cpu_class_is_omap2()) {
598 burst = 0x3;
599 break;
600 }
601 /* OMAP1 don't support burst 16
602 * fall through
603 */
604 default:
605 printk(KERN_ERR "Invalid DMA burst mode\n");
606 BUG();
607 return;
608 }
609 l |= (burst << 14);
610 dma_write(l, CSDP(lch));
611 }
612 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
613
614 static inline void omap_enable_channel_irq(int lch)
615 {
616 u32 status;
617
618 /* Clear CSR */
619 if (cpu_class_is_omap1())
620 status = dma_read(CSR(lch));
621 else if (cpu_class_is_omap2())
622 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
623
624 /* Enable some nice interrupts. */
625 dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
626 }
627
628 static void omap_disable_channel_irq(int lch)
629 {
630 if (cpu_class_is_omap2())
631 dma_write(0, CICR(lch));
632 }
633
634 void omap_enable_dma_irq(int lch, u16 bits)
635 {
636 dma_chan[lch].enabled_irqs |= bits;
637 }
638 EXPORT_SYMBOL(omap_enable_dma_irq);
639
640 void omap_disable_dma_irq(int lch, u16 bits)
641 {
642 dma_chan[lch].enabled_irqs &= ~bits;
643 }
644 EXPORT_SYMBOL(omap_disable_dma_irq);
645
646 static inline void enable_lnk(int lch)
647 {
648 u32 l;
649
650 l = dma_read(CLNK_CTRL(lch));
651
652 if (cpu_class_is_omap1())
653 l &= ~(1 << 14);
654
655 /* Set the ENABLE_LNK bits */
656 if (dma_chan[lch].next_lch != -1)
657 l = dma_chan[lch].next_lch | (1 << 15);
658
659 #ifndef CONFIG_ARCH_OMAP1
660 if (cpu_class_is_omap2())
661 if (dma_chan[lch].next_linked_ch != -1)
662 l = dma_chan[lch].next_linked_ch | (1 << 15);
663 #endif
664
665 dma_write(l, CLNK_CTRL(lch));
666 }
667
668 static inline void disable_lnk(int lch)
669 {
670 u32 l;
671
672 l = dma_read(CLNK_CTRL(lch));
673
674 /* Disable interrupts */
675 if (cpu_class_is_omap1()) {
676 dma_write(0, CICR(lch));
677 /* Set the STOP_LNK bit */
678 l |= 1 << 14;
679 }
680
681 if (cpu_class_is_omap2()) {
682 omap_disable_channel_irq(lch);
683 /* Clear the ENABLE_LNK bit */
684 l &= ~(1 << 15);
685 }
686
687 dma_write(l, CLNK_CTRL(lch));
688 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
689 }
690
691 static inline void omap2_enable_irq_lch(int lch)
692 {
693 u32 val;
694
695 if (!cpu_class_is_omap2())
696 return;
697
698 val = dma_read(IRQENABLE_L0);
699 val |= 1 << lch;
700 dma_write(val, IRQENABLE_L0);
701 }
702
703 int omap_request_dma(int dev_id, const char *dev_name,
704 void (*callback)(int lch, u16 ch_status, void *data),
705 void *data, int *dma_ch_out)
706 {
707 int ch, free_ch = -1;
708 unsigned long flags;
709 struct omap_dma_lch *chan;
710
711 spin_lock_irqsave(&dma_chan_lock, flags);
712 for (ch = 0; ch < dma_chan_count; ch++) {
713 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
714 free_ch = ch;
715 if (dev_id == 0)
716 break;
717 }
718 }
719 if (free_ch == -1) {
720 spin_unlock_irqrestore(&dma_chan_lock, flags);
721 return -EBUSY;
722 }
723 chan = dma_chan + free_ch;
724 chan->dev_id = dev_id;
725
726 if (cpu_class_is_omap1())
727 clear_lch_regs(free_ch);
728
729 if (cpu_class_is_omap2())
730 omap_clear_dma(free_ch);
731
732 spin_unlock_irqrestore(&dma_chan_lock, flags);
733
734 chan->dev_name = dev_name;
735 chan->callback = callback;
736 chan->data = data;
737 chan->flags = 0;
738
739 #ifndef CONFIG_ARCH_OMAP1
740 if (cpu_class_is_omap2()) {
741 chan->chain_id = -1;
742 chan->next_linked_ch = -1;
743 }
744 #endif
745
746 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
747
748 if (cpu_class_is_omap1())
749 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
750 else if (cpu_class_is_omap2())
751 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
752 OMAP2_DMA_TRANS_ERR_IRQ;
753
754 if (cpu_is_omap16xx()) {
755 /* If the sync device is set, configure it dynamically. */
756 if (dev_id != 0) {
757 set_gdma_dev(free_ch + 1, dev_id);
758 dev_id = free_ch + 1;
759 }
760 /*
761 * Disable the 1510 compatibility mode and set the sync device
762 * id.
763 */
764 dma_write(dev_id | (1 << 10), CCR(free_ch));
765 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
766 dma_write(dev_id, CCR(free_ch));
767 }
768
769 if (cpu_class_is_omap2()) {
770 omap2_enable_irq_lch(free_ch);
771 omap_enable_channel_irq(free_ch);
772 /* Clear the CSR register and IRQ status register */
773 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
774 dma_write(1 << free_ch, IRQSTATUS_L0);
775 }
776
777 *dma_ch_out = free_ch;
778
779 return 0;
780 }
781 EXPORT_SYMBOL(omap_request_dma);
782
783 void omap_free_dma(int lch)
784 {
785 unsigned long flags;
786
787 if (dma_chan[lch].dev_id == -1) {
788 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
789 lch);
790 return;
791 }
792
793 if (cpu_class_is_omap1()) {
794 /* Disable all DMA interrupts for the channel. */
795 dma_write(0, CICR(lch));
796 /* Make sure the DMA transfer is stopped. */
797 dma_write(0, CCR(lch));
798 }
799
800 if (cpu_class_is_omap2()) {
801 u32 val;
802 /* Disable interrupts */
803 val = dma_read(IRQENABLE_L0);
804 val &= ~(1 << lch);
805 dma_write(val, IRQENABLE_L0);
806
807 /* Clear the CSR register and IRQ status register */
808 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
809 dma_write(1 << lch, IRQSTATUS_L0);
810
811 /* Disable all DMA interrupts for the channel. */
812 dma_write(0, CICR(lch));
813
814 /* Make sure the DMA transfer is stopped. */
815 dma_write(0, CCR(lch));
816 omap_clear_dma(lch);
817 }
818
819 spin_lock_irqsave(&dma_chan_lock, flags);
820 dma_chan[lch].dev_id = -1;
821 dma_chan[lch].next_lch = -1;
822 dma_chan[lch].callback = NULL;
823 spin_unlock_irqrestore(&dma_chan_lock, flags);
824 }
825 EXPORT_SYMBOL(omap_free_dma);
826
827 /**
828 * @brief omap_dma_set_global_params : Set global priority settings for dma
829 *
830 * @param arb_rate
831 * @param max_fifo_depth
832 * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
833 * DMA_THREAD_RESERVE_ONET
834 * DMA_THREAD_RESERVE_TWOT
835 * DMA_THREAD_RESERVE_THREET
836 */
837 void
838 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
839 {
840 u32 reg;
841
842 if (!cpu_class_is_omap2()) {
843 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
844 return;
845 }
846
847 if (arb_rate == 0)
848 arb_rate = 1;
849
850 reg = (arb_rate & 0xff) << 16;
851 reg |= (0xff & max_fifo_depth);
852
853 dma_write(reg, GCR);
854 }
855 EXPORT_SYMBOL(omap_dma_set_global_params);
856
857 /**
858 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
859 *
860 * @param lch
861 * @param read_prio - Read priority
862 * @param write_prio - Write priority
863 * Both of the above can be set with one of the following values :
864 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
865 */
866 int
867 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
868 unsigned char write_prio)
869 {
870 u32 l;
871
872 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
873 printk(KERN_ERR "Invalid channel id\n");
874 return -EINVAL;
875 }
876 l = dma_read(CCR(lch));
877 l &= ~((1 << 6) | (1 << 26));
878 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
879 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
880 else
881 l |= ((read_prio & 0x1) << 6);
882
883 dma_write(l, CCR(lch));
884
885 return 0;
886 }
887 EXPORT_SYMBOL(omap_dma_set_prio_lch);
888
889 /*
890 * Clears any DMA state so the DMA engine is ready to restart with new buffers
891 * through omap_start_dma(). Any buffers in flight are discarded.
892 */
893 void omap_clear_dma(int lch)
894 {
895 unsigned long flags;
896
897 local_irq_save(flags);
898
899 if (cpu_class_is_omap1()) {
900 u32 l;
901
902 l = dma_read(CCR(lch));
903 l &= ~OMAP_DMA_CCR_EN;
904 dma_write(l, CCR(lch));
905
906 /* Clear pending interrupts */
907 l = dma_read(CSR(lch));
908 }
909
910 if (cpu_class_is_omap2()) {
911 int i;
912 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
913 for (i = 0; i < 0x44; i += 4)
914 __raw_writel(0, lch_base + i);
915 }
916
917 local_irq_restore(flags);
918 }
919 EXPORT_SYMBOL(omap_clear_dma);
920
921 void omap_start_dma(int lch)
922 {
923 u32 l;
924
925 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
926 int next_lch, cur_lch;
927 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
928
929 dma_chan_link_map[lch] = 1;
930 /* Set the link register of the first channel */
931 enable_lnk(lch);
932
933 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
934 cur_lch = dma_chan[lch].next_lch;
935 do {
936 next_lch = dma_chan[cur_lch].next_lch;
937
938 /* The loop case: we've been here already */
939 if (dma_chan_link_map[cur_lch])
940 break;
941 /* Mark the current channel */
942 dma_chan_link_map[cur_lch] = 1;
943
944 enable_lnk(cur_lch);
945 omap_enable_channel_irq(cur_lch);
946
947 cur_lch = next_lch;
948 } while (next_lch != -1);
949 } else if (cpu_class_is_omap2()) {
950 /* Errata: Need to write lch even if not using chaining */
951 dma_write(lch, CLNK_CTRL(lch));
952 }
953
954 omap_enable_channel_irq(lch);
955
956 l = dma_read(CCR(lch));
957
958 /*
959 * Errata: On ES2.0 BUFFERING disable must be set.
960 * This will always fail on ES1.0
961 */
962 if (cpu_is_omap24xx())
963 l |= OMAP_DMA_CCR_EN;
964
965 l |= OMAP_DMA_CCR_EN;
966 dma_write(l, CCR(lch));
967
968 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
969 }
970 EXPORT_SYMBOL(omap_start_dma);
971
972 void omap_stop_dma(int lch)
973 {
974 u32 l;
975
976 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
977 int next_lch, cur_lch = lch;
978 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
979
980 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
981 do {
982 /* The loop case: we've been here already */
983 if (dma_chan_link_map[cur_lch])
984 break;
985 /* Mark the current channel */
986 dma_chan_link_map[cur_lch] = 1;
987
988 disable_lnk(cur_lch);
989
990 next_lch = dma_chan[cur_lch].next_lch;
991 cur_lch = next_lch;
992 } while (next_lch != -1);
993
994 return;
995 }
996
997 /* Disable all interrupts on the channel */
998 if (cpu_class_is_omap1())
999 dma_write(0, CICR(lch));
1000
1001 l = dma_read(CCR(lch));
1002 l &= ~OMAP_DMA_CCR_EN;
1003 dma_write(l, CCR(lch));
1004
1005 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1006 }
1007 EXPORT_SYMBOL(omap_stop_dma);
1008
1009 /*
1010 * Allows changing the DMA callback function or data. This may be needed if
1011 * the driver shares a single DMA channel for multiple dma triggers.
1012 */
1013 int omap_set_dma_callback(int lch,
1014 void (*callback)(int lch, u16 ch_status, void *data),
1015 void *data)
1016 {
1017 unsigned long flags;
1018
1019 if (lch < 0)
1020 return -ENODEV;
1021
1022 spin_lock_irqsave(&dma_chan_lock, flags);
1023 if (dma_chan[lch].dev_id == -1) {
1024 printk(KERN_ERR "DMA callback for not set for free channel\n");
1025 spin_unlock_irqrestore(&dma_chan_lock, flags);
1026 return -EINVAL;
1027 }
1028 dma_chan[lch].callback = callback;
1029 dma_chan[lch].data = data;
1030 spin_unlock_irqrestore(&dma_chan_lock, flags);
1031
1032 return 0;
1033 }
1034 EXPORT_SYMBOL(omap_set_dma_callback);
1035
1036 /*
1037 * Returns current physical source address for the given DMA channel.
1038 * If the channel is running the caller must disable interrupts prior calling
1039 * this function and process the returned value before re-enabling interrupt to
1040 * prevent races with the interrupt handler. Note that in continuous mode there
1041 * is a chance for CSSA_L register overflow inbetween the two reads resulting
1042 * in incorrect return value.
1043 */
1044 dma_addr_t omap_get_dma_src_pos(int lch)
1045 {
1046 dma_addr_t offset = 0;
1047
1048 if (cpu_is_omap15xx())
1049 offset = dma_read(CPC(lch));
1050 else
1051 offset = dma_read(CSAC(lch));
1052
1053 /*
1054 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1055 * read before the DMA controller finished disabling the channel.
1056 */
1057 if (!cpu_is_omap15xx() && offset == 0)
1058 offset = dma_read(CSAC(lch));
1059
1060 if (cpu_class_is_omap1())
1061 offset |= (dma_read(CSSA_U(lch)) << 16);
1062
1063 return offset;
1064 }
1065 EXPORT_SYMBOL(omap_get_dma_src_pos);
1066
1067 /*
1068 * Returns current physical destination address for the given DMA channel.
1069 * If the channel is running the caller must disable interrupts prior calling
1070 * this function and process the returned value before re-enabling interrupt to
1071 * prevent races with the interrupt handler. Note that in continuous mode there
1072 * is a chance for CDSA_L register overflow inbetween the two reads resulting
1073 * in incorrect return value.
1074 */
1075 dma_addr_t omap_get_dma_dst_pos(int lch)
1076 {
1077 dma_addr_t offset = 0;
1078
1079 if (cpu_is_omap15xx())
1080 offset = dma_read(CPC(lch));
1081 else
1082 offset = dma_read(CDAC(lch));
1083
1084 /*
1085 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1086 * read before the DMA controller finished disabling the channel.
1087 */
1088 if (!cpu_is_omap15xx() && offset == 0)
1089 offset = dma_read(CDAC(lch));
1090
1091 if (cpu_class_is_omap1())
1092 offset |= (dma_read(CDSA_U(lch)) << 16);
1093
1094 return offset;
1095 }
1096 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1097
1098 int omap_get_dma_active_status(int lch)
1099 {
1100 return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1101 }
1102 EXPORT_SYMBOL(omap_get_dma_active_status);
1103
1104 int omap_dma_running(void)
1105 {
1106 int lch;
1107
1108 /* Check if LCD DMA is running */
1109 if (cpu_is_omap16xx())
1110 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1111 return 1;
1112
1113 for (lch = 0; lch < dma_chan_count; lch++)
1114 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1115 return 1;
1116
1117 return 0;
1118 }
1119
1120 /*
1121 * lch_queue DMA will start right after lch_head one is finished.
1122 * For this DMA link to start, you still need to start (see omap_start_dma)
1123 * the first one. That will fire up the entire queue.
1124 */
1125 void omap_dma_link_lch(int lch_head, int lch_queue)
1126 {
1127 if (omap_dma_in_1510_mode()) {
1128 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1129 BUG();
1130 return;
1131 }
1132
1133 if ((dma_chan[lch_head].dev_id == -1) ||
1134 (dma_chan[lch_queue].dev_id == -1)) {
1135 printk(KERN_ERR "omap_dma: trying to link "
1136 "non requested channels\n");
1137 dump_stack();
1138 }
1139
1140 dma_chan[lch_head].next_lch = lch_queue;
1141 }
1142 EXPORT_SYMBOL(omap_dma_link_lch);
1143
1144 /*
1145 * Once the DMA queue is stopped, we can destroy it.
1146 */
1147 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1148 {
1149 if (omap_dma_in_1510_mode()) {
1150 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1151 BUG();
1152 return;
1153 }
1154
1155 if (dma_chan[lch_head].next_lch != lch_queue ||
1156 dma_chan[lch_head].next_lch == -1) {
1157 printk(KERN_ERR "omap_dma: trying to unlink "
1158 "non linked channels\n");
1159 dump_stack();
1160 }
1161
1162 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1163 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1164 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1165 "before unlinking\n");
1166 dump_stack();
1167 }
1168
1169 dma_chan[lch_head].next_lch = -1;
1170 }
1171 EXPORT_SYMBOL(omap_dma_unlink_lch);
1172
1173 /*----------------------------------------------------------------------------*/
1174
1175 #ifndef CONFIG_ARCH_OMAP1
1176 /* Create chain of DMA channesls */
1177 static void create_dma_lch_chain(int lch_head, int lch_queue)
1178 {
1179 u32 l;
1180
1181 /* Check if this is the first link in chain */
1182 if (dma_chan[lch_head].next_linked_ch == -1) {
1183 dma_chan[lch_head].next_linked_ch = lch_queue;
1184 dma_chan[lch_head].prev_linked_ch = lch_queue;
1185 dma_chan[lch_queue].next_linked_ch = lch_head;
1186 dma_chan[lch_queue].prev_linked_ch = lch_head;
1187 }
1188
1189 /* a link exists, link the new channel in circular chain */
1190 else {
1191 dma_chan[lch_queue].next_linked_ch =
1192 dma_chan[lch_head].next_linked_ch;
1193 dma_chan[lch_queue].prev_linked_ch = lch_head;
1194 dma_chan[lch_head].next_linked_ch = lch_queue;
1195 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1196 lch_queue;
1197 }
1198
1199 l = dma_read(CLNK_CTRL(lch_head));
1200 l &= ~(0x1f);
1201 l |= lch_queue;
1202 dma_write(l, CLNK_CTRL(lch_head));
1203
1204 l = dma_read(CLNK_CTRL(lch_queue));
1205 l &= ~(0x1f);
1206 l |= (dma_chan[lch_queue].next_linked_ch);
1207 dma_write(l, CLNK_CTRL(lch_queue));
1208 }
1209
1210 /**
1211 * @brief omap_request_dma_chain : Request a chain of DMA channels
1212 *
1213 * @param dev_id - Device id using the dma channel
1214 * @param dev_name - Device name
1215 * @param callback - Call back function
1216 * @chain_id -
1217 * @no_of_chans - Number of channels requested
1218 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1219 * OMAP_DMA_DYNAMIC_CHAIN
1220 * @params - Channel parameters
1221 *
1222 * @return - Succes : 0
1223 * Failure: -EINVAL/-ENOMEM
1224 */
1225 int omap_request_dma_chain(int dev_id, const char *dev_name,
1226 void (*callback) (int lch, u16 ch_status,
1227 void *data),
1228 int *chain_id, int no_of_chans, int chain_mode,
1229 struct omap_dma_channel_params params)
1230 {
1231 int *channels;
1232 int i, err;
1233
1234 /* Is the chain mode valid ? */
1235 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1236 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1237 printk(KERN_ERR "Invalid chain mode requested\n");
1238 return -EINVAL;
1239 }
1240
1241 if (unlikely((no_of_chans < 1
1242 || no_of_chans > dma_lch_count))) {
1243 printk(KERN_ERR "Invalid Number of channels requested\n");
1244 return -EINVAL;
1245 }
1246
1247 /* Allocate a queue to maintain the status of the channels
1248 * in the chain */
1249 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1250 if (channels == NULL) {
1251 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1252 return -ENOMEM;
1253 }
1254
1255 /* request and reserve DMA channels for the chain */
1256 for (i = 0; i < no_of_chans; i++) {
1257 err = omap_request_dma(dev_id, dev_name,
1258 callback, NULL, &channels[i]);
1259 if (err < 0) {
1260 int j;
1261 for (j = 0; j < i; j++)
1262 omap_free_dma(channels[j]);
1263 kfree(channels);
1264 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1265 return err;
1266 }
1267 dma_chan[channels[i]].prev_linked_ch = -1;
1268 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1269
1270 /*
1271 * Allowing client drivers to set common parameters now,
1272 * so that later only relevant (src_start, dest_start
1273 * and element count) can be set
1274 */
1275 omap_set_dma_params(channels[i], &params);
1276 }
1277
1278 *chain_id = channels[0];
1279 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1280 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1281 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1282 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1283
1284 for (i = 0; i < no_of_chans; i++)
1285 dma_chan[channels[i]].chain_id = *chain_id;
1286
1287 /* Reset the Queue pointers */
1288 OMAP_DMA_CHAIN_QINIT(*chain_id);
1289
1290 /* Set up the chain */
1291 if (no_of_chans == 1)
1292 create_dma_lch_chain(channels[0], channels[0]);
1293 else {
1294 for (i = 0; i < (no_of_chans - 1); i++)
1295 create_dma_lch_chain(channels[i], channels[i + 1]);
1296 }
1297
1298 return 0;
1299 }
1300 EXPORT_SYMBOL(omap_request_dma_chain);
1301
1302 /**
1303 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1304 * params after setting it. Dont do this while dma is running!!
1305 *
1306 * @param chain_id - Chained logical channel id.
1307 * @param params
1308 *
1309 * @return - Success : 0
1310 * Failure : -EINVAL
1311 */
1312 int omap_modify_dma_chain_params(int chain_id,
1313 struct omap_dma_channel_params params)
1314 {
1315 int *channels;
1316 u32 i;
1317
1318 /* Check for input params */
1319 if (unlikely((chain_id < 0
1320 || chain_id >= dma_lch_count))) {
1321 printk(KERN_ERR "Invalid chain id\n");
1322 return -EINVAL;
1323 }
1324
1325 /* Check if the chain exists */
1326 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1327 printk(KERN_ERR "Chain doesn't exists\n");
1328 return -EINVAL;
1329 }
1330 channels = dma_linked_lch[chain_id].linked_dmach_q;
1331
1332 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1333 /*
1334 * Allowing client drivers to set common parameters now,
1335 * so that later only relevant (src_start, dest_start
1336 * and element count) can be set
1337 */
1338 omap_set_dma_params(channels[i], &params);
1339 }
1340
1341 return 0;
1342 }
1343 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1344
1345 /**
1346 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1347 *
1348 * @param chain_id
1349 *
1350 * @return - Success : 0
1351 * Failure : -EINVAL
1352 */
1353 int omap_free_dma_chain(int chain_id)
1354 {
1355 int *channels;
1356 u32 i;
1357
1358 /* Check for input params */
1359 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1360 printk(KERN_ERR "Invalid chain id\n");
1361 return -EINVAL;
1362 }
1363
1364 /* Check if the chain exists */
1365 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1366 printk(KERN_ERR "Chain doesn't exists\n");
1367 return -EINVAL;
1368 }
1369
1370 channels = dma_linked_lch[chain_id].linked_dmach_q;
1371 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1372 dma_chan[channels[i]].next_linked_ch = -1;
1373 dma_chan[channels[i]].prev_linked_ch = -1;
1374 dma_chan[channels[i]].chain_id = -1;
1375 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1376 omap_free_dma(channels[i]);
1377 }
1378
1379 kfree(channels);
1380
1381 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1382 dma_linked_lch[chain_id].chain_mode = -1;
1383 dma_linked_lch[chain_id].chain_state = -1;
1384
1385 return (0);
1386 }
1387 EXPORT_SYMBOL(omap_free_dma_chain);
1388
1389 /**
1390 * @brief omap_dma_chain_status - Check if the chain is in
1391 * active / inactive state.
1392 * @param chain_id
1393 *
1394 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1395 * Failure : -EINVAL
1396 */
1397 int omap_dma_chain_status(int chain_id)
1398 {
1399 /* Check for input params */
1400 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1401 printk(KERN_ERR "Invalid chain id\n");
1402 return -EINVAL;
1403 }
1404
1405 /* Check if the chain exists */
1406 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1407 printk(KERN_ERR "Chain doesn't exists\n");
1408 return -EINVAL;
1409 }
1410 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1411 dma_linked_lch[chain_id].q_count);
1412
1413 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1414 return OMAP_DMA_CHAIN_INACTIVE;
1415
1416 return OMAP_DMA_CHAIN_ACTIVE;
1417 }
1418 EXPORT_SYMBOL(omap_dma_chain_status);
1419
1420 /**
1421 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1422 * set the params and start the transfer.
1423 *
1424 * @param chain_id
1425 * @param src_start - buffer start address
1426 * @param dest_start - Dest address
1427 * @param elem_count
1428 * @param frame_count
1429 * @param callbk_data - channel callback parameter data.
1430 *
1431 * @return - Success : 0
1432 * Failure: -EINVAL/-EBUSY
1433 */
1434 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1435 int elem_count, int frame_count, void *callbk_data)
1436 {
1437 int *channels;
1438 u32 l, lch;
1439 int start_dma = 0;
1440
1441 /*
1442 * if buffer size is less than 1 then there is
1443 * no use of starting the chain
1444 */
1445 if (elem_count < 1) {
1446 printk(KERN_ERR "Invalid buffer size\n");
1447 return -EINVAL;
1448 }
1449
1450 /* Check for input params */
1451 if (unlikely((chain_id < 0
1452 || chain_id >= dma_lch_count))) {
1453 printk(KERN_ERR "Invalid chain id\n");
1454 return -EINVAL;
1455 }
1456
1457 /* Check if the chain exists */
1458 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1459 printk(KERN_ERR "Chain doesn't exist\n");
1460 return -EINVAL;
1461 }
1462
1463 /* Check if all the channels in chain are in use */
1464 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1465 return -EBUSY;
1466
1467 /* Frame count may be negative in case of indexed transfers */
1468 channels = dma_linked_lch[chain_id].linked_dmach_q;
1469
1470 /* Get a free channel */
1471 lch = channels[dma_linked_lch[chain_id].q_tail];
1472
1473 /* Store the callback data */
1474 dma_chan[lch].data = callbk_data;
1475
1476 /* Increment the q_tail */
1477 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1478
1479 /* Set the params to the free channel */
1480 if (src_start != 0)
1481 dma_write(src_start, CSSA(lch));
1482 if (dest_start != 0)
1483 dma_write(dest_start, CDSA(lch));
1484
1485 /* Write the buffer size */
1486 dma_write(elem_count, CEN(lch));
1487 dma_write(frame_count, CFN(lch));
1488
1489 /*
1490 * If the chain is dynamically linked,
1491 * then we may have to start the chain if its not active
1492 */
1493 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1494
1495 /*
1496 * In Dynamic chain, if the chain is not started,
1497 * queue the channel
1498 */
1499 if (dma_linked_lch[chain_id].chain_state ==
1500 DMA_CHAIN_NOTSTARTED) {
1501 /* Enable the link in previous channel */
1502 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1503 DMA_CH_QUEUED)
1504 enable_lnk(dma_chan[lch].prev_linked_ch);
1505 dma_chan[lch].state = DMA_CH_QUEUED;
1506 }
1507
1508 /*
1509 * Chain is already started, make sure its active,
1510 * if not then start the chain
1511 */
1512 else {
1513 start_dma = 1;
1514
1515 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1516 DMA_CH_STARTED) {
1517 enable_lnk(dma_chan[lch].prev_linked_ch);
1518 dma_chan[lch].state = DMA_CH_QUEUED;
1519 start_dma = 0;
1520 if (0 == ((1 << 7) & dma_read(
1521 CCR(dma_chan[lch].prev_linked_ch)))) {
1522 disable_lnk(dma_chan[lch].
1523 prev_linked_ch);
1524 pr_debug("\n prev ch is stopped\n");
1525 start_dma = 1;
1526 }
1527 }
1528
1529 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1530 == DMA_CH_QUEUED) {
1531 enable_lnk(dma_chan[lch].prev_linked_ch);
1532 dma_chan[lch].state = DMA_CH_QUEUED;
1533 start_dma = 0;
1534 }
1535 omap_enable_channel_irq(lch);
1536
1537 l = dma_read(CCR(lch));
1538
1539 if ((0 == (l & (1 << 24))))
1540 l &= ~(1 << 25);
1541 else
1542 l |= (1 << 25);
1543 if (start_dma == 1) {
1544 if (0 == (l & (1 << 7))) {
1545 l |= (1 << 7);
1546 dma_chan[lch].state = DMA_CH_STARTED;
1547 pr_debug("starting %d\n", lch);
1548 dma_write(l, CCR(lch));
1549 } else
1550 start_dma = 0;
1551 } else {
1552 if (0 == (l & (1 << 7)))
1553 dma_write(l, CCR(lch));
1554 }
1555 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1556 }
1557 }
1558
1559 return 0;
1560 }
1561 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1562
1563 /**
1564 * @brief omap_start_dma_chain_transfers - Start the chain
1565 *
1566 * @param chain_id
1567 *
1568 * @return - Success : 0
1569 * Failure : -EINVAL/-EBUSY
1570 */
1571 int omap_start_dma_chain_transfers(int chain_id)
1572 {
1573 int *channels;
1574 u32 l, i;
1575
1576 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1577 printk(KERN_ERR "Invalid chain id\n");
1578 return -EINVAL;
1579 }
1580
1581 channels = dma_linked_lch[chain_id].linked_dmach_q;
1582
1583 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1584 printk(KERN_ERR "Chain is already started\n");
1585 return -EBUSY;
1586 }
1587
1588 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1589 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1590 i++) {
1591 enable_lnk(channels[i]);
1592 omap_enable_channel_irq(channels[i]);
1593 }
1594 } else {
1595 omap_enable_channel_irq(channels[0]);
1596 }
1597
1598 l = dma_read(CCR(channels[0]));
1599 l |= (1 << 7);
1600 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1601 dma_chan[channels[0]].state = DMA_CH_STARTED;
1602
1603 if ((0 == (l & (1 << 24))))
1604 l &= ~(1 << 25);
1605 else
1606 l |= (1 << 25);
1607 dma_write(l, CCR(channels[0]));
1608
1609 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1610
1611 return 0;
1612 }
1613 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1614
1615 /**
1616 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1617 *
1618 * @param chain_id
1619 *
1620 * @return - Success : 0
1621 * Failure : EINVAL
1622 */
1623 int omap_stop_dma_chain_transfers(int chain_id)
1624 {
1625 int *channels;
1626 u32 l, i;
1627 u32 sys_cf;
1628
1629 /* Check for input params */
1630 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1631 printk(KERN_ERR "Invalid chain id\n");
1632 return -EINVAL;
1633 }
1634
1635 /* Check if the chain exists */
1636 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1637 printk(KERN_ERR "Chain doesn't exists\n");
1638 return -EINVAL;
1639 }
1640 channels = dma_linked_lch[chain_id].linked_dmach_q;
1641
1642 /*
1643 * DMA Errata:
1644 * Special programming model needed to disable DMA before end of block
1645 */
1646 sys_cf = dma_read(OCP_SYSCONFIG);
1647 l = sys_cf;
1648 /* Middle mode reg set no Standby */
1649 l &= ~((1 << 12)|(1 << 13));
1650 dma_write(l, OCP_SYSCONFIG);
1651
1652 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1653
1654 /* Stop the Channel transmission */
1655 l = dma_read(CCR(channels[i]));
1656 l &= ~(1 << 7);
1657 dma_write(l, CCR(channels[i]));
1658
1659 /* Disable the link in all the channels */
1660 disable_lnk(channels[i]);
1661 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1662
1663 }
1664 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1665
1666 /* Reset the Queue pointers */
1667 OMAP_DMA_CHAIN_QINIT(chain_id);
1668
1669 /* Errata - put in the old value */
1670 dma_write(sys_cf, OCP_SYSCONFIG);
1671
1672 return 0;
1673 }
1674 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1675
1676 /* Get the index of the ongoing DMA in chain */
1677 /**
1678 * @brief omap_get_dma_chain_index - Get the element and frame index
1679 * of the ongoing DMA in chain
1680 *
1681 * @param chain_id
1682 * @param ei - Element index
1683 * @param fi - Frame index
1684 *
1685 * @return - Success : 0
1686 * Failure : -EINVAL
1687 */
1688 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1689 {
1690 int lch;
1691 int *channels;
1692
1693 /* Check for input params */
1694 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1695 printk(KERN_ERR "Invalid chain id\n");
1696 return -EINVAL;
1697 }
1698
1699 /* Check if the chain exists */
1700 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1701 printk(KERN_ERR "Chain doesn't exists\n");
1702 return -EINVAL;
1703 }
1704 if ((!ei) || (!fi))
1705 return -EINVAL;
1706
1707 channels = dma_linked_lch[chain_id].linked_dmach_q;
1708
1709 /* Get the current channel */
1710 lch = channels[dma_linked_lch[chain_id].q_head];
1711
1712 *ei = dma_read(CCEN(lch));
1713 *fi = dma_read(CCFN(lch));
1714
1715 return 0;
1716 }
1717 EXPORT_SYMBOL(omap_get_dma_chain_index);
1718
1719 /**
1720 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1721 * ongoing DMA in chain
1722 *
1723 * @param chain_id
1724 *
1725 * @return - Success : Destination position
1726 * Failure : -EINVAL
1727 */
1728 int omap_get_dma_chain_dst_pos(int chain_id)
1729 {
1730 int lch;
1731 int *channels;
1732
1733 /* Check for input params */
1734 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1735 printk(KERN_ERR "Invalid chain id\n");
1736 return -EINVAL;
1737 }
1738
1739 /* Check if the chain exists */
1740 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1741 printk(KERN_ERR "Chain doesn't exists\n");
1742 return -EINVAL;
1743 }
1744
1745 channels = dma_linked_lch[chain_id].linked_dmach_q;
1746
1747 /* Get the current channel */
1748 lch = channels[dma_linked_lch[chain_id].q_head];
1749
1750 return dma_read(CDAC(lch));
1751 }
1752 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1753
1754 /**
1755 * @brief omap_get_dma_chain_src_pos - Get the source position
1756 * of the ongoing DMA in chain
1757 * @param chain_id
1758 *
1759 * @return - Success : Destination position
1760 * Failure : -EINVAL
1761 */
1762 int omap_get_dma_chain_src_pos(int chain_id)
1763 {
1764 int lch;
1765 int *channels;
1766
1767 /* Check for input params */
1768 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1769 printk(KERN_ERR "Invalid chain id\n");
1770 return -EINVAL;
1771 }
1772
1773 /* Check if the chain exists */
1774 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1775 printk(KERN_ERR "Chain doesn't exists\n");
1776 return -EINVAL;
1777 }
1778
1779 channels = dma_linked_lch[chain_id].linked_dmach_q;
1780
1781 /* Get the current channel */
1782 lch = channels[dma_linked_lch[chain_id].q_head];
1783
1784 return dma_read(CSAC(lch));
1785 }
1786 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1787 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1788
1789 /*----------------------------------------------------------------------------*/
1790
1791 #ifdef CONFIG_ARCH_OMAP1
1792
1793 static int omap1_dma_handle_ch(int ch)
1794 {
1795 u32 csr;
1796
1797 if (enable_1510_mode && ch >= 6) {
1798 csr = dma_chan[ch].saved_csr;
1799 dma_chan[ch].saved_csr = 0;
1800 } else
1801 csr = dma_read(CSR(ch));
1802 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1803 dma_chan[ch + 6].saved_csr = csr >> 7;
1804 csr &= 0x7f;
1805 }
1806 if ((csr & 0x3f) == 0)
1807 return 0;
1808 if (unlikely(dma_chan[ch].dev_id == -1)) {
1809 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1810 "%d (CSR %04x)\n", ch, csr);
1811 return 0;
1812 }
1813 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1814 printk(KERN_WARNING "DMA timeout with device %d\n",
1815 dma_chan[ch].dev_id);
1816 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1817 printk(KERN_WARNING "DMA synchronization event drop occurred "
1818 "with device %d\n", dma_chan[ch].dev_id);
1819 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1820 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1821 if (likely(dma_chan[ch].callback != NULL))
1822 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1823
1824 return 1;
1825 }
1826
1827 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1828 {
1829 int ch = ((int) dev_id) - 1;
1830 int handled = 0;
1831
1832 for (;;) {
1833 int handled_now = 0;
1834
1835 handled_now += omap1_dma_handle_ch(ch);
1836 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1837 handled_now += omap1_dma_handle_ch(ch + 6);
1838 if (!handled_now)
1839 break;
1840 handled += handled_now;
1841 }
1842
1843 return handled ? IRQ_HANDLED : IRQ_NONE;
1844 }
1845
1846 #else
1847 #define omap1_dma_irq_handler NULL
1848 #endif
1849
1850 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
1851 defined(CONFIG_ARCH_OMAP4)
1852
1853 static int omap2_dma_handle_ch(int ch)
1854 {
1855 u32 status = dma_read(CSR(ch));
1856
1857 if (!status) {
1858 if (printk_ratelimit())
1859 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1860 ch);
1861 dma_write(1 << ch, IRQSTATUS_L0);
1862 return 0;
1863 }
1864 if (unlikely(dma_chan[ch].dev_id == -1)) {
1865 if (printk_ratelimit())
1866 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1867 "channel %d\n", status, ch);
1868 return 0;
1869 }
1870 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1871 printk(KERN_INFO
1872 "DMA synchronization event drop occurred with device "
1873 "%d\n", dma_chan[ch].dev_id);
1874 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1875 printk(KERN_INFO "DMA transaction error with device %d\n",
1876 dma_chan[ch].dev_id);
1877 if (cpu_class_is_omap2()) {
1878 /* Errata: sDMA Channel is not disabled
1879 * after a transaction error. So we explicitely
1880 * disable the channel
1881 */
1882 u32 ccr;
1883
1884 ccr = dma_read(CCR(ch));
1885 ccr &= ~OMAP_DMA_CCR_EN;
1886 dma_write(ccr, CCR(ch));
1887 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1888 }
1889 }
1890 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1891 printk(KERN_INFO "DMA secure error with device %d\n",
1892 dma_chan[ch].dev_id);
1893 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1894 printk(KERN_INFO "DMA misaligned error with device %d\n",
1895 dma_chan[ch].dev_id);
1896
1897 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1898 dma_write(1 << ch, IRQSTATUS_L0);
1899
1900 /* If the ch is not chained then chain_id will be -1 */
1901 if (dma_chan[ch].chain_id != -1) {
1902 int chain_id = dma_chan[ch].chain_id;
1903 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1904 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1905 dma_chan[dma_chan[ch].next_linked_ch].state =
1906 DMA_CH_STARTED;
1907 if (dma_linked_lch[chain_id].chain_mode ==
1908 OMAP_DMA_DYNAMIC_CHAIN)
1909 disable_lnk(ch);
1910
1911 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1912 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1913
1914 status = dma_read(CSR(ch));
1915 }
1916
1917 dma_write(status, CSR(ch));
1918
1919 if (likely(dma_chan[ch].callback != NULL))
1920 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1921
1922 return 0;
1923 }
1924
1925 /* STATUS register count is from 1-32 while our is 0-31 */
1926 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1927 {
1928 u32 val, enable_reg;
1929 int i;
1930
1931 val = dma_read(IRQSTATUS_L0);
1932 if (val == 0) {
1933 if (printk_ratelimit())
1934 printk(KERN_WARNING "Spurious DMA IRQ\n");
1935 return IRQ_HANDLED;
1936 }
1937 enable_reg = dma_read(IRQENABLE_L0);
1938 val &= enable_reg; /* Dispatch only relevant interrupts */
1939 for (i = 0; i < dma_lch_count && val != 0; i++) {
1940 if (val & 1)
1941 omap2_dma_handle_ch(i);
1942 val >>= 1;
1943 }
1944
1945 return IRQ_HANDLED;
1946 }
1947
1948 static struct irqaction omap24xx_dma_irq = {
1949 .name = "DMA",
1950 .handler = omap2_dma_irq_handler,
1951 .flags = IRQF_DISABLED
1952 };
1953
1954 #else
1955 static struct irqaction omap24xx_dma_irq;
1956 #endif
1957
1958 /*----------------------------------------------------------------------------*/
1959
1960 static struct lcd_dma_info {
1961 spinlock_t lock;
1962 int reserved;
1963 void (*callback)(u16 status, void *data);
1964 void *cb_data;
1965
1966 int active;
1967 unsigned long addr, size;
1968 int rotate, data_type, xres, yres;
1969 int vxres;
1970 int mirror;
1971 int xscale, yscale;
1972 int ext_ctrl;
1973 int src_port;
1974 int single_transfer;
1975 } lcd_dma;
1976
1977 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1978 int data_type)
1979 {
1980 lcd_dma.addr = addr;
1981 lcd_dma.data_type = data_type;
1982 lcd_dma.xres = fb_xres;
1983 lcd_dma.yres = fb_yres;
1984 }
1985 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1986
1987 void omap_set_lcd_dma_src_port(int port)
1988 {
1989 lcd_dma.src_port = port;
1990 }
1991
1992 void omap_set_lcd_dma_ext_controller(int external)
1993 {
1994 lcd_dma.ext_ctrl = external;
1995 }
1996 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1997
1998 void omap_set_lcd_dma_single_transfer(int single)
1999 {
2000 lcd_dma.single_transfer = single;
2001 }
2002 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2003
2004 void omap_set_lcd_dma_b1_rotation(int rotate)
2005 {
2006 if (omap_dma_in_1510_mode()) {
2007 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
2008 BUG();
2009 return;
2010 }
2011 lcd_dma.rotate = rotate;
2012 }
2013 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2014
2015 void omap_set_lcd_dma_b1_mirror(int mirror)
2016 {
2017 if (omap_dma_in_1510_mode()) {
2018 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
2019 BUG();
2020 }
2021 lcd_dma.mirror = mirror;
2022 }
2023 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2024
2025 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
2026 {
2027 if (omap_dma_in_1510_mode()) {
2028 printk(KERN_ERR "DMA virtual resulotion is not supported "
2029 "in 1510 mode\n");
2030 BUG();
2031 }
2032 lcd_dma.vxres = vxres;
2033 }
2034 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2035
2036 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2037 {
2038 if (omap_dma_in_1510_mode()) {
2039 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2040 BUG();
2041 }
2042 lcd_dma.xscale = xscale;
2043 lcd_dma.yscale = yscale;
2044 }
2045 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2046
2047 static void set_b1_regs(void)
2048 {
2049 unsigned long top, bottom;
2050 int es;
2051 u16 w;
2052 unsigned long en, fn;
2053 long ei, fi;
2054 unsigned long vxres;
2055 unsigned int xscale, yscale;
2056
2057 switch (lcd_dma.data_type) {
2058 case OMAP_DMA_DATA_TYPE_S8:
2059 es = 1;
2060 break;
2061 case OMAP_DMA_DATA_TYPE_S16:
2062 es = 2;
2063 break;
2064 case OMAP_DMA_DATA_TYPE_S32:
2065 es = 4;
2066 break;
2067 default:
2068 BUG();
2069 return;
2070 }
2071
2072 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2073 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2074 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2075 BUG_ON(vxres < lcd_dma.xres);
2076
2077 #define PIXADDR(x, y) (lcd_dma.addr + \
2078 ((y) * vxres * yscale + (x) * xscale) * es)
2079 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2080
2081 switch (lcd_dma.rotate) {
2082 case 0:
2083 if (!lcd_dma.mirror) {
2084 top = PIXADDR(0, 0);
2085 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2086 /* 1510 DMA requires the bottom address to be 2 more
2087 * than the actual last memory access location. */
2088 if (omap_dma_in_1510_mode() &&
2089 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2090 bottom += 2;
2091 ei = PIXSTEP(0, 0, 1, 0);
2092 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2093 } else {
2094 top = PIXADDR(lcd_dma.xres - 1, 0);
2095 bottom = PIXADDR(0, lcd_dma.yres - 1);
2096 ei = PIXSTEP(1, 0, 0, 0);
2097 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2098 }
2099 en = lcd_dma.xres;
2100 fn = lcd_dma.yres;
2101 break;
2102 case 90:
2103 if (!lcd_dma.mirror) {
2104 top = PIXADDR(0, lcd_dma.yres - 1);
2105 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2106 ei = PIXSTEP(0, 1, 0, 0);
2107 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2108 } else {
2109 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2110 bottom = PIXADDR(0, 0);
2111 ei = PIXSTEP(0, 1, 0, 0);
2112 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2113 }
2114 en = lcd_dma.yres;
2115 fn = lcd_dma.xres;
2116 break;
2117 case 180:
2118 if (!lcd_dma.mirror) {
2119 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2120 bottom = PIXADDR(0, 0);
2121 ei = PIXSTEP(1, 0, 0, 0);
2122 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2123 } else {
2124 top = PIXADDR(0, lcd_dma.yres - 1);
2125 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2126 ei = PIXSTEP(0, 0, 1, 0);
2127 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2128 }
2129 en = lcd_dma.xres;
2130 fn = lcd_dma.yres;
2131 break;
2132 case 270:
2133 if (!lcd_dma.mirror) {
2134 top = PIXADDR(lcd_dma.xres - 1, 0);
2135 bottom = PIXADDR(0, lcd_dma.yres - 1);
2136 ei = PIXSTEP(0, 0, 0, 1);
2137 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2138 } else {
2139 top = PIXADDR(0, 0);
2140 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2141 ei = PIXSTEP(0, 0, 0, 1);
2142 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2143 }
2144 en = lcd_dma.yres;
2145 fn = lcd_dma.xres;
2146 break;
2147 default:
2148 BUG();
2149 return; /* Suppress warning about uninitialized vars */
2150 }
2151
2152 if (omap_dma_in_1510_mode()) {
2153 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2154 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2155 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2156 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2157
2158 return;
2159 }
2160
2161 /* 1610 regs */
2162 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2163 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2164 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2165 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2166
2167 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2168 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2169
2170 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2171 w &= ~0x03;
2172 w |= lcd_dma.data_type;
2173 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2174
2175 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2176 /* Always set the source port as SDRAM for now*/
2177 w &= ~(0x03 << 6);
2178 if (lcd_dma.callback != NULL)
2179 w |= 1 << 1; /* Block interrupt enable */
2180 else
2181 w &= ~(1 << 1);
2182 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2183
2184 if (!(lcd_dma.rotate || lcd_dma.mirror ||
2185 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2186 return;
2187
2188 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2189 /* Set the double-indexed addressing mode */
2190 w |= (0x03 << 12);
2191 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2192
2193 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2194 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2195 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2196 }
2197
2198 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2199 {
2200 u16 w;
2201
2202 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2203 if (unlikely(!(w & (1 << 3)))) {
2204 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2205 return IRQ_NONE;
2206 }
2207 /* Ack the IRQ */
2208 w |= (1 << 3);
2209 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2210 lcd_dma.active = 0;
2211 if (lcd_dma.callback != NULL)
2212 lcd_dma.callback(w, lcd_dma.cb_data);
2213
2214 return IRQ_HANDLED;
2215 }
2216
2217 int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2218 void *data)
2219 {
2220 spin_lock_irq(&lcd_dma.lock);
2221 if (lcd_dma.reserved) {
2222 spin_unlock_irq(&lcd_dma.lock);
2223 printk(KERN_ERR "LCD DMA channel already reserved\n");
2224 BUG();
2225 return -EBUSY;
2226 }
2227 lcd_dma.reserved = 1;
2228 spin_unlock_irq(&lcd_dma.lock);
2229 lcd_dma.callback = callback;
2230 lcd_dma.cb_data = data;
2231 lcd_dma.active = 0;
2232 lcd_dma.single_transfer = 0;
2233 lcd_dma.rotate = 0;
2234 lcd_dma.vxres = 0;
2235 lcd_dma.mirror = 0;
2236 lcd_dma.xscale = 0;
2237 lcd_dma.yscale = 0;
2238 lcd_dma.ext_ctrl = 0;
2239 lcd_dma.src_port = 0;
2240
2241 return 0;
2242 }
2243 EXPORT_SYMBOL(omap_request_lcd_dma);
2244
2245 void omap_free_lcd_dma(void)
2246 {
2247 spin_lock(&lcd_dma.lock);
2248 if (!lcd_dma.reserved) {
2249 spin_unlock(&lcd_dma.lock);
2250 printk(KERN_ERR "LCD DMA is not reserved\n");
2251 BUG();
2252 return;
2253 }
2254 if (!enable_1510_mode)
2255 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2256 OMAP1610_DMA_LCD_CCR);
2257 lcd_dma.reserved = 0;
2258 spin_unlock(&lcd_dma.lock);
2259 }
2260 EXPORT_SYMBOL(omap_free_lcd_dma);
2261
2262 void omap_enable_lcd_dma(void)
2263 {
2264 u16 w;
2265
2266 /*
2267 * Set the Enable bit only if an external controller is
2268 * connected. Otherwise the OMAP internal controller will
2269 * start the transfer when it gets enabled.
2270 */
2271 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2272 return;
2273
2274 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2275 w |= 1 << 8;
2276 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2277
2278 lcd_dma.active = 1;
2279
2280 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2281 w |= 1 << 7;
2282 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2283 }
2284 EXPORT_SYMBOL(omap_enable_lcd_dma);
2285
2286 void omap_setup_lcd_dma(void)
2287 {
2288 BUG_ON(lcd_dma.active);
2289 if (!enable_1510_mode) {
2290 /* Set some reasonable defaults */
2291 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2292 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2293 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2294 }
2295 set_b1_regs();
2296 if (!enable_1510_mode) {
2297 u16 w;
2298
2299 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2300 /*
2301 * If DMA was already active set the end_prog bit to have
2302 * the programmed register set loaded into the active
2303 * register set.
2304 */
2305 w |= 1 << 11; /* End_prog */
2306 if (!lcd_dma.single_transfer)
2307 w |= (3 << 8); /* Auto_init, repeat */
2308 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2309 }
2310 }
2311 EXPORT_SYMBOL(omap_setup_lcd_dma);
2312
2313 void omap_stop_lcd_dma(void)
2314 {
2315 u16 w;
2316
2317 lcd_dma.active = 0;
2318 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2319 return;
2320
2321 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2322 w &= ~(1 << 7);
2323 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2324
2325 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2326 w &= ~(1 << 8);
2327 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2328 }
2329 EXPORT_SYMBOL(omap_stop_lcd_dma);
2330
2331 /*----------------------------------------------------------------------------*/
2332
2333 static int __init omap_init_dma(void)
2334 {
2335 int ch, r;
2336
2337 if (cpu_class_is_omap1()) {
2338 omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
2339 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2340 } else if (cpu_is_omap24xx()) {
2341 omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
2342 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2343 } else if (cpu_is_omap34xx()) {
2344 omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
2345 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2346 } else if (cpu_is_omap44xx()) {
2347 omap_dma_base = IO_ADDRESS(OMAP44XX_DMA4_BASE);
2348 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2349 } else {
2350 pr_err("DMA init failed for unsupported omap\n");
2351 return -ENODEV;
2352 }
2353
2354 if (cpu_class_is_omap2() && omap_dma_reserve_channels
2355 && (omap_dma_reserve_channels <= dma_lch_count))
2356 dma_lch_count = omap_dma_reserve_channels;
2357
2358 dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2359 GFP_KERNEL);
2360 if (!dma_chan)
2361 return -ENOMEM;
2362
2363 if (cpu_class_is_omap2()) {
2364 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2365 dma_lch_count, GFP_KERNEL);
2366 if (!dma_linked_lch) {
2367 kfree(dma_chan);
2368 return -ENOMEM;
2369 }
2370 }
2371
2372 if (cpu_is_omap15xx()) {
2373 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2374 dma_chan_count = 9;
2375 enable_1510_mode = 1;
2376 } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2377 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2378 dma_read(HW_ID));
2379 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2380 (dma_read(CAPS_0_U) << 16) |
2381 dma_read(CAPS_0_L),
2382 (dma_read(CAPS_1_U) << 16) |
2383 dma_read(CAPS_1_L),
2384 dma_read(CAPS_2), dma_read(CAPS_3),
2385 dma_read(CAPS_4));
2386 if (!enable_1510_mode) {
2387 u16 w;
2388
2389 /* Disable OMAP 3.0/3.1 compatibility mode. */
2390 w = dma_read(GSCR);
2391 w |= 1 << 3;
2392 dma_write(w, GSCR);
2393 dma_chan_count = 16;
2394 } else
2395 dma_chan_count = 9;
2396 if (cpu_is_omap16xx()) {
2397 u16 w;
2398
2399 /* this would prevent OMAP sleep */
2400 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2401 w &= ~(1 << 8);
2402 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2403 }
2404 } else if (cpu_class_is_omap2()) {
2405 u8 revision = dma_read(REVISION) & 0xff;
2406 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2407 revision >> 4, revision & 0xf);
2408 dma_chan_count = dma_lch_count;
2409 } else {
2410 dma_chan_count = 0;
2411 return 0;
2412 }
2413
2414 spin_lock_init(&lcd_dma.lock);
2415 spin_lock_init(&dma_chan_lock);
2416
2417 for (ch = 0; ch < dma_chan_count; ch++) {
2418 omap_clear_dma(ch);
2419 dma_chan[ch].dev_id = -1;
2420 dma_chan[ch].next_lch = -1;
2421
2422 if (ch >= 6 && enable_1510_mode)
2423 continue;
2424
2425 if (cpu_class_is_omap1()) {
2426 /*
2427 * request_irq() doesn't like dev_id (ie. ch) being
2428 * zero, so we have to kludge around this.
2429 */
2430 r = request_irq(omap1_dma_irq[ch],
2431 omap1_dma_irq_handler, 0, "DMA",
2432 (void *) (ch + 1));
2433 if (r != 0) {
2434 int i;
2435
2436 printk(KERN_ERR "unable to request IRQ %d "
2437 "for DMA (error %d)\n",
2438 omap1_dma_irq[ch], r);
2439 for (i = 0; i < ch; i++)
2440 free_irq(omap1_dma_irq[i],
2441 (void *) (i + 1));
2442 return r;
2443 }
2444 }
2445 }
2446
2447 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2448 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2449 DMA_DEFAULT_FIFO_DEPTH, 0);
2450
2451 if (cpu_class_is_omap2()) {
2452 int irq;
2453 if (cpu_is_omap44xx())
2454 irq = INT_44XX_SDMA_IRQ0;
2455 else
2456 irq = INT_24XX_SDMA_IRQ0;
2457 setup_irq(irq, &omap24xx_dma_irq);
2458 }
2459
2460 /* Enable smartidle idlemodes and autoidle */
2461 if (cpu_is_omap34xx()) {
2462 u32 v = dma_read(OCP_SYSCONFIG);
2463 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
2464 DMA_SYSCONFIG_SIDLEMODE_MASK |
2465 DMA_SYSCONFIG_AUTOIDLE);
2466 v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2467 DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2468 DMA_SYSCONFIG_AUTOIDLE);
2469 dma_write(v , OCP_SYSCONFIG);
2470 }
2471
2472
2473 /* FIXME: Update LCD DMA to work on 24xx */
2474 if (cpu_class_is_omap1()) {
2475 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2476 "LCD DMA", NULL);
2477 if (r != 0) {
2478 int i;
2479
2480 printk(KERN_ERR "unable to request IRQ for LCD DMA "
2481 "(error %d)\n", r);
2482 for (i = 0; i < dma_chan_count; i++)
2483 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2484 return r;
2485 }
2486 }
2487
2488 return 0;
2489 }
2490
2491 arch_initcall(omap_init_dma);
2492
2493 /*
2494 * Reserve the omap SDMA channels using cmdline bootarg
2495 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2496 */
2497 static int __init omap_dma_cmdline_reserve_ch(char *str)
2498 {
2499 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2500 omap_dma_reserve_channels = 0;
2501 return 1;
2502 }
2503
2504 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2505
2506
Linux with added FPC-III support