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wl1251: use wiphy_dev instead of wl->spi->dev
[linux/fpc-iii.git] / drivers / net / gianfar.c
blob4544da4cf3ce1a406ea186de8dcea9bd669b1d96
1 /*
2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
10 * Maintainer: Kumar Gala
11 *
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
27 *
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
30 *
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
36 *
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
52 * skb.
53 *
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
62 */
63
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
77 #include <linux/mm.h>
78 #include <linux/of_mdio.h>
79 #include <linux/of_platform.h>
80 #include <linux/ip.h>
81 #include <linux/tcp.h>
82 #include <linux/udp.h>
83 #include <linux/in.h>
84
85 #include <asm/io.h>
86 #include <asm/irq.h>
87 #include <asm/uaccess.h>
88 #include <linux/module.h>
89 #include <linux/dma-mapping.h>
90 #include <linux/crc32.h>
91 #include <linux/mii.h>
92 #include <linux/phy.h>
93 #include <linux/phy_fixed.h>
94 #include <linux/of.h>
95
96 #include "gianfar.h"
97 #include "fsl_pq_mdio.h"
98
99 #define TX_TIMEOUT (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
102
103 const char gfar_driver_name[] = "Gianfar Ethernet";
104 const char gfar_driver_version[] = "1.3";
105
106 static int gfar_enet_open(struct net_device *dev);
107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
108 static void gfar_reset_task(struct work_struct *work);
109 static void gfar_timeout(struct net_device *dev);
110 static int gfar_close(struct net_device *dev);
111 struct sk_buff *gfar_new_skb(struct net_device *dev);
112 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
113 struct sk_buff *skb);
114 static int gfar_set_mac_address(struct net_device *dev);
115 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
116 static irqreturn_t gfar_error(int irq, void *dev_id);
117 static irqreturn_t gfar_transmit(int irq, void *dev_id);
118 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
119 static void adjust_link(struct net_device *dev);
120 static void init_registers(struct net_device *dev);
121 static int init_phy(struct net_device *dev);
122 static int gfar_probe(struct of_device *ofdev,
123 const struct of_device_id *match);
124 static int gfar_remove(struct of_device *ofdev);
125 static void free_skb_resources(struct gfar_private *priv);
126 static void gfar_set_multi(struct net_device *dev);
127 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
128 static void gfar_configure_serdes(struct net_device *dev);
129 static int gfar_poll(struct napi_struct *napi, int budget);
130 #ifdef CONFIG_NET_POLL_CONTROLLER
131 static void gfar_netpoll(struct net_device *dev);
132 #endif
133 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
134 static int gfar_clean_tx_ring(struct net_device *dev);
135 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
136 int amount_pull);
137 static void gfar_vlan_rx_register(struct net_device *netdev,
138 struct vlan_group *grp);
139 void gfar_halt(struct net_device *dev);
140 static void gfar_halt_nodisable(struct net_device *dev);
141 void gfar_start(struct net_device *dev);
142 static void gfar_clear_exact_match(struct net_device *dev);
143 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
145
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
149
150 static const struct net_device_ops gfar_netdev_ops = {
151 .ndo_open = gfar_enet_open,
152 .ndo_start_xmit = gfar_start_xmit,
153 .ndo_stop = gfar_close,
154 .ndo_change_mtu = gfar_change_mtu,
155 .ndo_set_multicast_list = gfar_set_multi,
156 .ndo_tx_timeout = gfar_timeout,
157 .ndo_do_ioctl = gfar_ioctl,
158 .ndo_vlan_rx_register = gfar_vlan_rx_register,
159 .ndo_set_mac_address = eth_mac_addr,
160 .ndo_validate_addr = eth_validate_addr,
161 #ifdef CONFIG_NET_POLL_CONTROLLER
162 .ndo_poll_controller = gfar_netpoll,
163 #endif
164 };
165
166 /* Returns 1 if incoming frames use an FCB */
167 static inline int gfar_uses_fcb(struct gfar_private *priv)
168 {
169 return priv->vlgrp || priv->rx_csum_enable;
170 }
171
172 static int gfar_of_init(struct net_device *dev)
173 {
174 const char *model;
175 const char *ctype;
176 const void *mac_addr;
177 u64 addr, size;
178 int err = 0;
179 struct gfar_private *priv = netdev_priv(dev);
180 struct device_node *np = priv->node;
181 const u32 *stash;
182 const u32 *stash_len;
183 const u32 *stash_idx;
184
185 if (!np || !of_device_is_available(np))
186 return -ENODEV;
187
188 /* get a pointer to the register memory */
189 addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
190 priv->regs = ioremap(addr, size);
191
192 if (priv->regs == NULL)
193 return -ENOMEM;
194
195 priv->interruptTransmit = irq_of_parse_and_map(np, 0);
196
197 model = of_get_property(np, "model", NULL);
198
199 /* If we aren't the FEC we have multiple interrupts */
200 if (model && strcasecmp(model, "FEC")) {
201 priv->interruptReceive = irq_of_parse_and_map(np, 1);
202
203 priv->interruptError = irq_of_parse_and_map(np, 2);
204
205 if (priv->interruptTransmit < 0 ||
206 priv->interruptReceive < 0 ||
207 priv->interruptError < 0) {
208 err = -EINVAL;
209 goto err_out;
210 }
211 }
212
213 stash = of_get_property(np, "bd-stash", NULL);
214
215 if(stash) {
216 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
217 priv->bd_stash_en = 1;
218 }
219
220 stash_len = of_get_property(np, "rx-stash-len", NULL);
221
222 if (stash_len)
223 priv->rx_stash_size = *stash_len;
224
225 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
226
227 if (stash_idx)
228 priv->rx_stash_index = *stash_idx;
229
230 if (stash_len || stash_idx)
231 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
232
233 mac_addr = of_get_mac_address(np);
234 if (mac_addr)
235 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
236
237 if (model && !strcasecmp(model, "TSEC"))
238 priv->device_flags =
239 FSL_GIANFAR_DEV_HAS_GIGABIT |
240 FSL_GIANFAR_DEV_HAS_COALESCE |
241 FSL_GIANFAR_DEV_HAS_RMON |
242 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
243 if (model && !strcasecmp(model, "eTSEC"))
244 priv->device_flags =
245 FSL_GIANFAR_DEV_HAS_GIGABIT |
246 FSL_GIANFAR_DEV_HAS_COALESCE |
247 FSL_GIANFAR_DEV_HAS_RMON |
248 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
249 FSL_GIANFAR_DEV_HAS_PADDING |
250 FSL_GIANFAR_DEV_HAS_CSUM |
251 FSL_GIANFAR_DEV_HAS_VLAN |
252 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
253 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
254
255 ctype = of_get_property(np, "phy-connection-type", NULL);
256
257 /* We only care about rgmii-id. The rest are autodetected */
258 if (ctype && !strcmp(ctype, "rgmii-id"))
259 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
260 else
261 priv->interface = PHY_INTERFACE_MODE_MII;
262
263 if (of_get_property(np, "fsl,magic-packet", NULL))
264 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
265
266 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
267
268 /* Find the TBI PHY. If it's not there, we don't support SGMII */
269 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
270
271 return 0;
272
273 err_out:
274 iounmap(priv->regs);
275 return err;
276 }
277
278 /* Ioctl MII Interface */
279 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
280 {
281 struct gfar_private *priv = netdev_priv(dev);
282
283 if (!netif_running(dev))
284 return -EINVAL;
285
286 if (!priv->phydev)
287 return -ENODEV;
288
289 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
290 }
291
292 /* Set up the ethernet device structure, private data,
293 * and anything else we need before we start */
294 static int gfar_probe(struct of_device *ofdev,
295 const struct of_device_id *match)
296 {
297 u32 tempval;
298 struct net_device *dev = NULL;
299 struct gfar_private *priv = NULL;
300 int err = 0;
301 int len_devname;
302
303 /* Create an ethernet device instance */
304 dev = alloc_etherdev(sizeof (*priv));
305
306 if (NULL == dev)
307 return -ENOMEM;
308
309 priv = netdev_priv(dev);
310 priv->ndev = dev;
311 priv->ofdev = ofdev;
312 priv->node = ofdev->node;
313 SET_NETDEV_DEV(dev, &ofdev->dev);
314
315 err = gfar_of_init(dev);
316
317 if (err)
318 goto regs_fail;
319
320 spin_lock_init(&priv->txlock);
321 spin_lock_init(&priv->rxlock);
322 spin_lock_init(&priv->bflock);
323 INIT_WORK(&priv->reset_task, gfar_reset_task);
324
325 dev_set_drvdata(&ofdev->dev, priv);
326
327 /* Stop the DMA engine now, in case it was running before */
328 /* (The firmware could have used it, and left it running). */
329 gfar_halt(dev);
330
331 /* Reset MAC layer */
332 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
333
334 /* We need to delay at least 3 TX clocks */
335 udelay(2);
336
337 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
338 gfar_write(&priv->regs->maccfg1, tempval);
339
340 /* Initialize MACCFG2. */
341 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
342
343 /* Initialize ECNTRL */
344 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
345
346 /* Set the dev->base_addr to the gfar reg region */
347 dev->base_addr = (unsigned long) (priv->regs);
348
349 SET_NETDEV_DEV(dev, &ofdev->dev);
350
351 /* Fill in the dev structure */
352 dev->watchdog_timeo = TX_TIMEOUT;
353 netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
354 dev->mtu = 1500;
355
356 dev->netdev_ops = &gfar_netdev_ops;
357 dev->ethtool_ops = &gfar_ethtool_ops;
358
359 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
360 priv->rx_csum_enable = 1;
361 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
362 } else
363 priv->rx_csum_enable = 0;
364
365 priv->vlgrp = NULL;
366
367 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
368 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
369
370 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
371 priv->extended_hash = 1;
372 priv->hash_width = 9;
373
374 priv->hash_regs[0] = &priv->regs->igaddr0;
375 priv->hash_regs[1] = &priv->regs->igaddr1;
376 priv->hash_regs[2] = &priv->regs->igaddr2;
377 priv->hash_regs[3] = &priv->regs->igaddr3;
378 priv->hash_regs[4] = &priv->regs->igaddr4;
379 priv->hash_regs[5] = &priv->regs->igaddr5;
380 priv->hash_regs[6] = &priv->regs->igaddr6;
381 priv->hash_regs[7] = &priv->regs->igaddr7;
382 priv->hash_regs[8] = &priv->regs->gaddr0;
383 priv->hash_regs[9] = &priv->regs->gaddr1;
384 priv->hash_regs[10] = &priv->regs->gaddr2;
385 priv->hash_regs[11] = &priv->regs->gaddr3;
386 priv->hash_regs[12] = &priv->regs->gaddr4;
387 priv->hash_regs[13] = &priv->regs->gaddr5;
388 priv->hash_regs[14] = &priv->regs->gaddr6;
389 priv->hash_regs[15] = &priv->regs->gaddr7;
390
391 } else {
392 priv->extended_hash = 0;
393 priv->hash_width = 8;
394
395 priv->hash_regs[0] = &priv->regs->gaddr0;
396 priv->hash_regs[1] = &priv->regs->gaddr1;
397 priv->hash_regs[2] = &priv->regs->gaddr2;
398 priv->hash_regs[3] = &priv->regs->gaddr3;
399 priv->hash_regs[4] = &priv->regs->gaddr4;
400 priv->hash_regs[5] = &priv->regs->gaddr5;
401 priv->hash_regs[6] = &priv->regs->gaddr6;
402 priv->hash_regs[7] = &priv->regs->gaddr7;
403 }
404
405 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
406 priv->padding = DEFAULT_PADDING;
407 else
408 priv->padding = 0;
409
410 if (dev->features & NETIF_F_IP_CSUM)
411 dev->hard_header_len += GMAC_FCB_LEN;
412
413 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
414 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
415 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
416 priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
417
418 priv->txcoalescing = DEFAULT_TX_COALESCE;
419 priv->txic = DEFAULT_TXIC;
420 priv->rxcoalescing = DEFAULT_RX_COALESCE;
421 priv->rxic = DEFAULT_RXIC;
422
423 /* Enable most messages by default */
424 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
425
426 /* Carrier starts down, phylib will bring it up */
427 netif_carrier_off(dev);
428
429 err = register_netdev(dev);
430
431 if (err) {
432 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
433 dev->name);
434 goto register_fail;
435 }
436
437 device_init_wakeup(&dev->dev,
438 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
439
440 /* fill out IRQ number and name fields */
441 len_devname = strlen(dev->name);
442 strncpy(&priv->int_name_tx[0], dev->name, len_devname);
443 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
444 strncpy(&priv->int_name_tx[len_devname],
445 "_tx", sizeof("_tx") + 1);
446
447 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
448 strncpy(&priv->int_name_rx[len_devname],
449 "_rx", sizeof("_rx") + 1);
450
451 strncpy(&priv->int_name_er[0], dev->name, len_devname);
452 strncpy(&priv->int_name_er[len_devname],
453 "_er", sizeof("_er") + 1);
454 } else
455 priv->int_name_tx[len_devname] = '\0';
456
457 /* Create all the sysfs files */
458 gfar_init_sysfs(dev);
459
460 /* Print out the device info */
461 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
462
463 /* Even more device info helps when determining which kernel */
464 /* provided which set of benchmarks. */
465 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
466 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
467 dev->name, priv->rx_ring_size, priv->tx_ring_size);
468
469 return 0;
470
471 register_fail:
472 iounmap(priv->regs);
473 regs_fail:
474 if (priv->phy_node)
475 of_node_put(priv->phy_node);
476 if (priv->tbi_node)
477 of_node_put(priv->tbi_node);
478 free_netdev(dev);
479 return err;
480 }
481
482 static int gfar_remove(struct of_device *ofdev)
483 {
484 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
485
486 if (priv->phy_node)
487 of_node_put(priv->phy_node);
488 if (priv->tbi_node)
489 of_node_put(priv->tbi_node);
490
491 dev_set_drvdata(&ofdev->dev, NULL);
492
493 iounmap(priv->regs);
494 free_netdev(priv->ndev);
495
496 return 0;
497 }
498
499 #ifdef CONFIG_PM
500 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
501 {
502 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
503 struct net_device *dev = priv->ndev;
504 unsigned long flags;
505 u32 tempval;
506
507 int magic_packet = priv->wol_en &&
508 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
509
510 netif_device_detach(dev);
511
512 if (netif_running(dev)) {
513 spin_lock_irqsave(&priv->txlock, flags);
514 spin_lock(&priv->rxlock);
515
516 gfar_halt_nodisable(dev);
517
518 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
519 tempval = gfar_read(&priv->regs->maccfg1);
520
521 tempval &= ~MACCFG1_TX_EN;
522
523 if (!magic_packet)
524 tempval &= ~MACCFG1_RX_EN;
525
526 gfar_write(&priv->regs->maccfg1, tempval);
527
528 spin_unlock(&priv->rxlock);
529 spin_unlock_irqrestore(&priv->txlock, flags);
530
531 napi_disable(&priv->napi);
532
533 if (magic_packet) {
534 /* Enable interrupt on Magic Packet */
535 gfar_write(&priv->regs->imask, IMASK_MAG);
536
537 /* Enable Magic Packet mode */
538 tempval = gfar_read(&priv->regs->maccfg2);
539 tempval |= MACCFG2_MPEN;
540 gfar_write(&priv->regs->maccfg2, tempval);
541 } else {
542 phy_stop(priv->phydev);
543 }
544 }
545
546 return 0;
547 }
548
549 static int gfar_resume(struct of_device *ofdev)
550 {
551 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
552 struct net_device *dev = priv->ndev;
553 unsigned long flags;
554 u32 tempval;
555 int magic_packet = priv->wol_en &&
556 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
557
558 if (!netif_running(dev)) {
559 netif_device_attach(dev);
560 return 0;
561 }
562
563 if (!magic_packet && priv->phydev)
564 phy_start(priv->phydev);
565
566 /* Disable Magic Packet mode, in case something
567 * else woke us up.
568 */
569
570 spin_lock_irqsave(&priv->txlock, flags);
571 spin_lock(&priv->rxlock);
572
573 tempval = gfar_read(&priv->regs->maccfg2);
574 tempval &= ~MACCFG2_MPEN;
575 gfar_write(&priv->regs->maccfg2, tempval);
576
577 gfar_start(dev);
578
579 spin_unlock(&priv->rxlock);
580 spin_unlock_irqrestore(&priv->txlock, flags);
581
582 netif_device_attach(dev);
583
584 napi_enable(&priv->napi);
585
586 return 0;
587 }
588 #else
589 #define gfar_suspend NULL
590 #define gfar_resume NULL
591 #endif
592
593 /* Reads the controller's registers to determine what interface
594 * connects it to the PHY.
595 */
596 static phy_interface_t gfar_get_interface(struct net_device *dev)
597 {
598 struct gfar_private *priv = netdev_priv(dev);
599 u32 ecntrl = gfar_read(&priv->regs->ecntrl);
600
601 if (ecntrl & ECNTRL_SGMII_MODE)
602 return PHY_INTERFACE_MODE_SGMII;
603
604 if (ecntrl & ECNTRL_TBI_MODE) {
605 if (ecntrl & ECNTRL_REDUCED_MODE)
606 return PHY_INTERFACE_MODE_RTBI;
607 else
608 return PHY_INTERFACE_MODE_TBI;
609 }
610
611 if (ecntrl & ECNTRL_REDUCED_MODE) {
612 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
613 return PHY_INTERFACE_MODE_RMII;
614 else {
615 phy_interface_t interface = priv->interface;
616
617 /*
618 * This isn't autodetected right now, so it must
619 * be set by the device tree or platform code.
620 */
621 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
622 return PHY_INTERFACE_MODE_RGMII_ID;
623
624 return PHY_INTERFACE_MODE_RGMII;
625 }
626 }
627
628 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
629 return PHY_INTERFACE_MODE_GMII;
630
631 return PHY_INTERFACE_MODE_MII;
632 }
633
634
635 /* Initializes driver's PHY state, and attaches to the PHY.
636 * Returns 0 on success.
637 */
638 static int init_phy(struct net_device *dev)
639 {
640 struct gfar_private *priv = netdev_priv(dev);
641 uint gigabit_support =
642 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
643 SUPPORTED_1000baseT_Full : 0;
644 phy_interface_t interface;
645
646 priv->oldlink = 0;
647 priv->oldspeed = 0;
648 priv->oldduplex = -1;
649
650 interface = gfar_get_interface(dev);
651
652 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
653 interface);
654 if (!priv->phydev)
655 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
656 interface);
657 if (!priv->phydev) {
658 dev_err(&dev->dev, "could not attach to PHY\n");
659 return -ENODEV;
660 }
661
662 if (interface == PHY_INTERFACE_MODE_SGMII)
663 gfar_configure_serdes(dev);
664
665 /* Remove any features not supported by the controller */
666 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
667 priv->phydev->advertising = priv->phydev->supported;
668
669 return 0;
670 }
671
672 /*
673 * Initialize TBI PHY interface for communicating with the
674 * SERDES lynx PHY on the chip. We communicate with this PHY
675 * through the MDIO bus on each controller, treating it as a
676 * "normal" PHY at the address found in the TBIPA register. We assume
677 * that the TBIPA register is valid. Either the MDIO bus code will set
678 * it to a value that doesn't conflict with other PHYs on the bus, or the
679 * value doesn't matter, as there are no other PHYs on the bus.
680 */
681 static void gfar_configure_serdes(struct net_device *dev)
682 {
683 struct gfar_private *priv = netdev_priv(dev);
684 struct phy_device *tbiphy;
685
686 if (!priv->tbi_node) {
687 dev_warn(&dev->dev, "error: SGMII mode requires that the "
688 "device tree specify a tbi-handle\n");
689 return;
690 }
691
692 tbiphy = of_phy_find_device(priv->tbi_node);
693 if (!tbiphy) {
694 dev_err(&dev->dev, "error: Could not get TBI device\n");
695 return;
696 }
697
698 /*
699 * If the link is already up, we must already be ok, and don't need to
700 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
701 * everything for us? Resetting it takes the link down and requires
702 * several seconds for it to come back.
703 */
704 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
705 return;
706
707 /* Single clk mode, mii mode off(for serdes communication) */
708 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
709
710 phy_write(tbiphy, MII_ADVERTISE,
711 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
712 ADVERTISE_1000XPSE_ASYM);
713
714 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
715 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
716 }
717
718 static void init_registers(struct net_device *dev)
719 {
720 struct gfar_private *priv = netdev_priv(dev);
721
722 /* Clear IEVENT */
723 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
724
725 /* Initialize IMASK */
726 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
727
728 /* Init hash registers to zero */
729 gfar_write(&priv->regs->igaddr0, 0);
730 gfar_write(&priv->regs->igaddr1, 0);
731 gfar_write(&priv->regs->igaddr2, 0);
732 gfar_write(&priv->regs->igaddr3, 0);
733 gfar_write(&priv->regs->igaddr4, 0);
734 gfar_write(&priv->regs->igaddr5, 0);
735 gfar_write(&priv->regs->igaddr6, 0);
736 gfar_write(&priv->regs->igaddr7, 0);
737
738 gfar_write(&priv->regs->gaddr0, 0);
739 gfar_write(&priv->regs->gaddr1, 0);
740 gfar_write(&priv->regs->gaddr2, 0);
741 gfar_write(&priv->regs->gaddr3, 0);
742 gfar_write(&priv->regs->gaddr4, 0);
743 gfar_write(&priv->regs->gaddr5, 0);
744 gfar_write(&priv->regs->gaddr6, 0);
745 gfar_write(&priv->regs->gaddr7, 0);
746
747 /* Zero out the rmon mib registers if it has them */
748 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
749 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
750
751 /* Mask off the CAM interrupts */
752 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
753 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
754 }
755
756 /* Initialize the max receive buffer length */
757 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
758
759 /* Initialize the Minimum Frame Length Register */
760 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
761 }
762
763
764 /* Halt the receive and transmit queues */
765 static void gfar_halt_nodisable(struct net_device *dev)
766 {
767 struct gfar_private *priv = netdev_priv(dev);
768 struct gfar __iomem *regs = priv->regs;
769 u32 tempval;
770
771 /* Mask all interrupts */
772 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
773
774 /* Clear all interrupts */
775 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
776
777 /* Stop the DMA, and wait for it to stop */
778 tempval = gfar_read(&priv->regs->dmactrl);
779 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
780 != (DMACTRL_GRS | DMACTRL_GTS)) {
781 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
782 gfar_write(&priv->regs->dmactrl, tempval);
783
784 while (!(gfar_read(&priv->regs->ievent) &
785 (IEVENT_GRSC | IEVENT_GTSC)))
786 cpu_relax();
787 }
788 }
789
790 /* Halt the receive and transmit queues */
791 void gfar_halt(struct net_device *dev)
792 {
793 struct gfar_private *priv = netdev_priv(dev);
794 struct gfar __iomem *regs = priv->regs;
795 u32 tempval;
796
797 gfar_halt_nodisable(dev);
798
799 /* Disable Rx and Tx */
800 tempval = gfar_read(&regs->maccfg1);
801 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
802 gfar_write(&regs->maccfg1, tempval);
803 }
804
805 void stop_gfar(struct net_device *dev)
806 {
807 struct gfar_private *priv = netdev_priv(dev);
808 struct gfar __iomem *regs = priv->regs;
809 unsigned long flags;
810
811 phy_stop(priv->phydev);
812
813 /* Lock it down */
814 spin_lock_irqsave(&priv->txlock, flags);
815 spin_lock(&priv->rxlock);
816
817 gfar_halt(dev);
818
819 spin_unlock(&priv->rxlock);
820 spin_unlock_irqrestore(&priv->txlock, flags);
821
822 /* Free the IRQs */
823 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
824 free_irq(priv->interruptError, dev);
825 free_irq(priv->interruptTransmit, dev);
826 free_irq(priv->interruptReceive, dev);
827 } else {
828 free_irq(priv->interruptTransmit, dev);
829 }
830
831 free_skb_resources(priv);
832
833 dma_free_coherent(&priv->ofdev->dev,
834 sizeof(struct txbd8)*priv->tx_ring_size
835 + sizeof(struct rxbd8)*priv->rx_ring_size,
836 priv->tx_bd_base,
837 gfar_read(&regs->tbase0));
838 }
839
840 /* If there are any tx skbs or rx skbs still around, free them.
841 * Then free tx_skbuff and rx_skbuff */
842 static void free_skb_resources(struct gfar_private *priv)
843 {
844 struct rxbd8 *rxbdp;
845 struct txbd8 *txbdp;
846 int i, j;
847
848 /* Go through all the buffer descriptors and free their data buffers */
849 txbdp = priv->tx_bd_base;
850
851 for (i = 0; i < priv->tx_ring_size; i++) {
852 if (!priv->tx_skbuff[i])
853 continue;
854
855 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
856 txbdp->length, DMA_TO_DEVICE);
857 txbdp->lstatus = 0;
858 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
859 txbdp++;
860 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
861 txbdp->length, DMA_TO_DEVICE);
862 }
863 txbdp++;
864 dev_kfree_skb_any(priv->tx_skbuff[i]);
865 priv->tx_skbuff[i] = NULL;
866 }
867
868 kfree(priv->tx_skbuff);
869
870 rxbdp = priv->rx_bd_base;
871
872 /* rx_skbuff is not guaranteed to be allocated, so only
873 * free it and its contents if it is allocated */
874 if(priv->rx_skbuff != NULL) {
875 for (i = 0; i < priv->rx_ring_size; i++) {
876 if (priv->rx_skbuff[i]) {
877 dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr,
878 priv->rx_buffer_size,
879 DMA_FROM_DEVICE);
880
881 dev_kfree_skb_any(priv->rx_skbuff[i]);
882 priv->rx_skbuff[i] = NULL;
883 }
884
885 rxbdp->lstatus = 0;
886 rxbdp->bufPtr = 0;
887
888 rxbdp++;
889 }
890
891 kfree(priv->rx_skbuff);
892 }
893 }
894
895 void gfar_start(struct net_device *dev)
896 {
897 struct gfar_private *priv = netdev_priv(dev);
898 struct gfar __iomem *regs = priv->regs;
899 u32 tempval;
900
901 /* Enable Rx and Tx in MACCFG1 */
902 tempval = gfar_read(&regs->maccfg1);
903 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
904 gfar_write(&regs->maccfg1, tempval);
905
906 /* Initialize DMACTRL to have WWR and WOP */
907 tempval = gfar_read(&priv->regs->dmactrl);
908 tempval |= DMACTRL_INIT_SETTINGS;
909 gfar_write(&priv->regs->dmactrl, tempval);
910
911 /* Make sure we aren't stopped */
912 tempval = gfar_read(&priv->regs->dmactrl);
913 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
914 gfar_write(&priv->regs->dmactrl, tempval);
915
916 /* Clear THLT/RHLT, so that the DMA starts polling now */
917 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
918 gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
919
920 /* Unmask the interrupts we look for */
921 gfar_write(&regs->imask, IMASK_DEFAULT);
922
923 dev->trans_start = jiffies;
924 }
925
926 /* Bring the controller up and running */
927 int startup_gfar(struct net_device *dev)
928 {
929 struct txbd8 *txbdp;
930 struct rxbd8 *rxbdp;
931 dma_addr_t addr = 0;
932 unsigned long vaddr;
933 int i;
934 struct gfar_private *priv = netdev_priv(dev);
935 struct gfar __iomem *regs = priv->regs;
936 int err = 0;
937 u32 rctrl = 0;
938 u32 tctrl = 0;
939 u32 attrs = 0;
940
941 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
942
943 /* Allocate memory for the buffer descriptors */
944 vaddr = (unsigned long) dma_alloc_coherent(&priv->ofdev->dev,
945 sizeof (struct txbd8) * priv->tx_ring_size +
946 sizeof (struct rxbd8) * priv->rx_ring_size,
947 &addr, GFP_KERNEL);
948
949 if (vaddr == 0) {
950 if (netif_msg_ifup(priv))
951 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
952 dev->name);
953 return -ENOMEM;
954 }
955
956 priv->tx_bd_base = (struct txbd8 *) vaddr;
957
958 /* enet DMA only understands physical addresses */
959 gfar_write(&regs->tbase0, addr);
960
961 /* Start the rx descriptor ring where the tx ring leaves off */
962 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
963 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
964 priv->rx_bd_base = (struct rxbd8 *) vaddr;
965 gfar_write(&regs->rbase0, addr);
966
967 /* Setup the skbuff rings */
968 priv->tx_skbuff =
969 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
970 priv->tx_ring_size, GFP_KERNEL);
971
972 if (NULL == priv->tx_skbuff) {
973 if (netif_msg_ifup(priv))
974 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
975 dev->name);
976 err = -ENOMEM;
977 goto tx_skb_fail;
978 }
979
980 for (i = 0; i < priv->tx_ring_size; i++)
981 priv->tx_skbuff[i] = NULL;
982
983 priv->rx_skbuff =
984 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
985 priv->rx_ring_size, GFP_KERNEL);
986
987 if (NULL == priv->rx_skbuff) {
988 if (netif_msg_ifup(priv))
989 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
990 dev->name);
991 err = -ENOMEM;
992 goto rx_skb_fail;
993 }
994
995 for (i = 0; i < priv->rx_ring_size; i++)
996 priv->rx_skbuff[i] = NULL;
997
998 /* Initialize some variables in our dev structure */
999 priv->num_txbdfree = priv->tx_ring_size;
1000 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
1001 priv->cur_rx = priv->rx_bd_base;
1002 priv->skb_curtx = priv->skb_dirtytx = 0;
1003 priv->skb_currx = 0;
1004
1005 /* Initialize Transmit Descriptor Ring */
1006 txbdp = priv->tx_bd_base;
1007 for (i = 0; i < priv->tx_ring_size; i++) {
1008 txbdp->lstatus = 0;
1009 txbdp->bufPtr = 0;
1010 txbdp++;
1011 }
1012
1013 /* Set the last descriptor in the ring to indicate wrap */
1014 txbdp--;
1015 txbdp->status |= TXBD_WRAP;
1016
1017 rxbdp = priv->rx_bd_base;
1018 for (i = 0; i < priv->rx_ring_size; i++) {
1019 struct sk_buff *skb;
1020
1021 skb = gfar_new_skb(dev);
1022
1023 if (!skb) {
1024 printk(KERN_ERR "%s: Can't allocate RX buffers\n",
1025 dev->name);
1026
1027 goto err_rxalloc_fail;
1028 }
1029
1030 priv->rx_skbuff[i] = skb;
1031
1032 gfar_new_rxbdp(dev, rxbdp, skb);
1033
1034 rxbdp++;
1035 }
1036
1037 /* Set the last descriptor in the ring to wrap */
1038 rxbdp--;
1039 rxbdp->status |= RXBD_WRAP;
1040
1041 /* If the device has multiple interrupts, register for
1042 * them. Otherwise, only register for the one */
1043 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1044 /* Install our interrupt handlers for Error,
1045 * Transmit, and Receive */
1046 if (request_irq(priv->interruptError, gfar_error,
1047 0, priv->int_name_er, dev) < 0) {
1048 if (netif_msg_intr(priv))
1049 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1050 dev->name, priv->interruptError);
1051
1052 err = -1;
1053 goto err_irq_fail;
1054 }
1055
1056 if (request_irq(priv->interruptTransmit, gfar_transmit,
1057 0, priv->int_name_tx, dev) < 0) {
1058 if (netif_msg_intr(priv))
1059 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1060 dev->name, priv->interruptTransmit);
1061
1062 err = -1;
1063
1064 goto tx_irq_fail;
1065 }
1066
1067 if (request_irq(priv->interruptReceive, gfar_receive,
1068 0, priv->int_name_rx, dev) < 0) {
1069 if (netif_msg_intr(priv))
1070 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1071 dev->name, priv->interruptReceive);
1072
1073 err = -1;
1074 goto rx_irq_fail;
1075 }
1076 } else {
1077 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1078 0, priv->int_name_tx, dev) < 0) {
1079 if (netif_msg_intr(priv))
1080 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1081 dev->name, priv->interruptTransmit);
1082
1083 err = -1;
1084 goto err_irq_fail;
1085 }
1086 }
1087
1088 phy_start(priv->phydev);
1089
1090 /* Configure the coalescing support */
1091 gfar_write(&regs->txic, 0);
1092 if (priv->txcoalescing)
1093 gfar_write(&regs->txic, priv->txic);
1094
1095 gfar_write(&regs->rxic, 0);
1096 if (priv->rxcoalescing)
1097 gfar_write(&regs->rxic, priv->rxic);
1098
1099 if (priv->rx_csum_enable)
1100 rctrl |= RCTRL_CHECKSUMMING;
1101
1102 if (priv->extended_hash) {
1103 rctrl |= RCTRL_EXTHASH;
1104
1105 gfar_clear_exact_match(dev);
1106 rctrl |= RCTRL_EMEN;
1107 }
1108
1109 if (priv->padding) {
1110 rctrl &= ~RCTRL_PAL_MASK;
1111 rctrl |= RCTRL_PADDING(priv->padding);
1112 }
1113
1114 /* keep vlan related bits if it's enabled */
1115 if (priv->vlgrp) {
1116 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
1117 tctrl |= TCTRL_VLINS;
1118 }
1119
1120 /* Init rctrl based on our settings */
1121 gfar_write(&priv->regs->rctrl, rctrl);
1122
1123 if (dev->features & NETIF_F_IP_CSUM)
1124 tctrl |= TCTRL_INIT_CSUM;
1125
1126 gfar_write(&priv->regs->tctrl, tctrl);
1127
1128 /* Set the extraction length and index */
1129 attrs = ATTRELI_EL(priv->rx_stash_size) |
1130 ATTRELI_EI(priv->rx_stash_index);
1131
1132 gfar_write(&priv->regs->attreli, attrs);
1133
1134 /* Start with defaults, and add stashing or locking
1135 * depending on the approprate variables */
1136 attrs = ATTR_INIT_SETTINGS;
1137
1138 if (priv->bd_stash_en)
1139 attrs |= ATTR_BDSTASH;
1140
1141 if (priv->rx_stash_size != 0)
1142 attrs |= ATTR_BUFSTASH;
1143
1144 gfar_write(&priv->regs->attr, attrs);
1145
1146 gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1147 gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1148 gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1149
1150 /* Start the controller */
1151 gfar_start(dev);
1152
1153 return 0;
1154
1155 rx_irq_fail:
1156 free_irq(priv->interruptTransmit, dev);
1157 tx_irq_fail:
1158 free_irq(priv->interruptError, dev);
1159 err_irq_fail:
1160 err_rxalloc_fail:
1161 rx_skb_fail:
1162 free_skb_resources(priv);
1163 tx_skb_fail:
1164 dma_free_coherent(&priv->ofdev->dev,
1165 sizeof(struct txbd8)*priv->tx_ring_size
1166 + sizeof(struct rxbd8)*priv->rx_ring_size,
1167 priv->tx_bd_base,
1168 gfar_read(&regs->tbase0));
1169
1170 return err;
1171 }
1172
1173 /* Called when something needs to use the ethernet device */
1174 /* Returns 0 for success. */
1175 static int gfar_enet_open(struct net_device *dev)
1176 {
1177 struct gfar_private *priv = netdev_priv(dev);
1178 int err;
1179
1180 napi_enable(&priv->napi);
1181
1182 skb_queue_head_init(&priv->rx_recycle);
1183
1184 /* Initialize a bunch of registers */
1185 init_registers(dev);
1186
1187 gfar_set_mac_address(dev);
1188
1189 err = init_phy(dev);
1190
1191 if(err) {
1192 napi_disable(&priv->napi);
1193 return err;
1194 }
1195
1196 err = startup_gfar(dev);
1197 if (err) {
1198 napi_disable(&priv->napi);
1199 return err;
1200 }
1201
1202 netif_start_queue(dev);
1203
1204 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1205
1206 return err;
1207 }
1208
1209 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1210 {
1211 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1212
1213 memset(fcb, 0, GMAC_FCB_LEN);
1214
1215 return fcb;
1216 }
1217
1218 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1219 {
1220 u8 flags = 0;
1221
1222 /* If we're here, it's a IP packet with a TCP or UDP
1223 * payload. We set it to checksum, using a pseudo-header
1224 * we provide
1225 */
1226 flags = TXFCB_DEFAULT;
1227
1228 /* Tell the controller what the protocol is */
1229 /* And provide the already calculated phcs */
1230 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1231 flags |= TXFCB_UDP;
1232 fcb->phcs = udp_hdr(skb)->check;
1233 } else
1234 fcb->phcs = tcp_hdr(skb)->check;
1235
1236 /* l3os is the distance between the start of the
1237 * frame (skb->data) and the start of the IP hdr.
1238 * l4os is the distance between the start of the
1239 * l3 hdr and the l4 hdr */
1240 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1241 fcb->l4os = skb_network_header_len(skb);
1242
1243 fcb->flags = flags;
1244 }
1245
1246 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1247 {
1248 fcb->flags |= TXFCB_VLN;
1249 fcb->vlctl = vlan_tx_tag_get(skb);
1250 }
1251
1252 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1253 struct txbd8 *base, int ring_size)
1254 {
1255 struct txbd8 *new_bd = bdp + stride;
1256
1257 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1258 }
1259
1260 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1261 int ring_size)
1262 {
1263 return skip_txbd(bdp, 1, base, ring_size);
1264 }
1265
1266 /* This is called by the kernel when a frame is ready for transmission. */
1267 /* It is pointed to by the dev->hard_start_xmit function pointer */
1268 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1269 {
1270 struct gfar_private *priv = netdev_priv(dev);
1271 struct txfcb *fcb = NULL;
1272 struct txbd8 *txbdp, *txbdp_start, *base;
1273 u32 lstatus;
1274 int i;
1275 u32 bufaddr;
1276 unsigned long flags;
1277 unsigned int nr_frags, length;
1278
1279 base = priv->tx_bd_base;
1280
1281 /* make space for additional header when fcb is needed */
1282 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1283 (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1284 (skb_headroom(skb) < GMAC_FCB_LEN)) {
1285 struct sk_buff *skb_new;
1286
1287 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1288 if (!skb_new) {
1289 dev->stats.tx_errors++;
1290 kfree_skb(skb);
1291 return NETDEV_TX_OK;
1292 }
1293 kfree_skb(skb);
1294 skb = skb_new;
1295 }
1296
1297 /* total number of fragments in the SKB */
1298 nr_frags = skb_shinfo(skb)->nr_frags;
1299
1300 spin_lock_irqsave(&priv->txlock, flags);
1301
1302 /* check if there is space to queue this packet */
1303 if ((nr_frags+1) > priv->num_txbdfree) {
1304 /* no space, stop the queue */
1305 netif_stop_queue(dev);
1306 dev->stats.tx_fifo_errors++;
1307 spin_unlock_irqrestore(&priv->txlock, flags);
1308 return NETDEV_TX_BUSY;
1309 }
1310
1311 /* Update transmit stats */
1312 dev->stats.tx_bytes += skb->len;
1313
1314 txbdp = txbdp_start = priv->cur_tx;
1315
1316 if (nr_frags == 0) {
1317 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1318 } else {
1319 /* Place the fragment addresses and lengths into the TxBDs */
1320 for (i = 0; i < nr_frags; i++) {
1321 /* Point at the next BD, wrapping as needed */
1322 txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1323
1324 length = skb_shinfo(skb)->frags[i].size;
1325
1326 lstatus = txbdp->lstatus | length |
1327 BD_LFLAG(TXBD_READY);
1328
1329 /* Handle the last BD specially */
1330 if (i == nr_frags - 1)
1331 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1332
1333 bufaddr = dma_map_page(&priv->ofdev->dev,
1334 skb_shinfo(skb)->frags[i].page,
1335 skb_shinfo(skb)->frags[i].page_offset,
1336 length,
1337 DMA_TO_DEVICE);
1338
1339 /* set the TxBD length and buffer pointer */
1340 txbdp->bufPtr = bufaddr;
1341 txbdp->lstatus = lstatus;
1342 }
1343
1344 lstatus = txbdp_start->lstatus;
1345 }
1346
1347 /* Set up checksumming */
1348 if (CHECKSUM_PARTIAL == skb->ip_summed) {
1349 fcb = gfar_add_fcb(skb);
1350 lstatus |= BD_LFLAG(TXBD_TOE);
1351 gfar_tx_checksum(skb, fcb);
1352 }
1353
1354 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1355 if (unlikely(NULL == fcb)) {
1356 fcb = gfar_add_fcb(skb);
1357 lstatus |= BD_LFLAG(TXBD_TOE);
1358 }
1359
1360 gfar_tx_vlan(skb, fcb);
1361 }
1362
1363 /* setup the TxBD length and buffer pointer for the first BD */
1364 priv->tx_skbuff[priv->skb_curtx] = skb;
1365 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1366 skb_headlen(skb), DMA_TO_DEVICE);
1367
1368 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1369
1370 /*
1371 * The powerpc-specific eieio() is used, as wmb() has too strong
1372 * semantics (it requires synchronization between cacheable and
1373 * uncacheable mappings, which eieio doesn't provide and which we
1374 * don't need), thus requiring a more expensive sync instruction. At
1375 * some point, the set of architecture-independent barrier functions
1376 * should be expanded to include weaker barriers.
1377 */
1378 eieio();
1379
1380 txbdp_start->lstatus = lstatus;
1381
1382 /* Update the current skb pointer to the next entry we will use
1383 * (wrapping if necessary) */
1384 priv->skb_curtx = (priv->skb_curtx + 1) &
1385 TX_RING_MOD_MASK(priv->tx_ring_size);
1386
1387 priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1388
1389 /* reduce TxBD free count */
1390 priv->num_txbdfree -= (nr_frags + 1);
1391
1392 dev->trans_start = jiffies;
1393
1394 /* If the next BD still needs to be cleaned up, then the bds
1395 are full. We need to tell the kernel to stop sending us stuff. */
1396 if (!priv->num_txbdfree) {
1397 netif_stop_queue(dev);
1398
1399 dev->stats.tx_fifo_errors++;
1400 }
1401
1402 /* Tell the DMA to go go go */
1403 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1404
1405 /* Unlock priv */
1406 spin_unlock_irqrestore(&priv->txlock, flags);
1407
1408 return NETDEV_TX_OK;
1409 }
1410
1411 /* Stops the kernel queue, and halts the controller */
1412 static int gfar_close(struct net_device *dev)
1413 {
1414 struct gfar_private *priv = netdev_priv(dev);
1415
1416 napi_disable(&priv->napi);
1417
1418 skb_queue_purge(&priv->rx_recycle);
1419 cancel_work_sync(&priv->reset_task);
1420 stop_gfar(dev);
1421
1422 /* Disconnect from the PHY */
1423 phy_disconnect(priv->phydev);
1424 priv->phydev = NULL;
1425
1426 netif_stop_queue(dev);
1427
1428 return 0;
1429 }
1430
1431 /* Changes the mac address if the controller is not running. */
1432 static int gfar_set_mac_address(struct net_device *dev)
1433 {
1434 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1435
1436 return 0;
1437 }
1438
1439
1440 /* Enables and disables VLAN insertion/extraction */
1441 static void gfar_vlan_rx_register(struct net_device *dev,
1442 struct vlan_group *grp)
1443 {
1444 struct gfar_private *priv = netdev_priv(dev);
1445 unsigned long flags;
1446 u32 tempval;
1447
1448 spin_lock_irqsave(&priv->rxlock, flags);
1449
1450 priv->vlgrp = grp;
1451
1452 if (grp) {
1453 /* Enable VLAN tag insertion */
1454 tempval = gfar_read(&priv->regs->tctrl);
1455 tempval |= TCTRL_VLINS;
1456
1457 gfar_write(&priv->regs->tctrl, tempval);
1458
1459 /* Enable VLAN tag extraction */
1460 tempval = gfar_read(&priv->regs->rctrl);
1461 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1462 gfar_write(&priv->regs->rctrl, tempval);
1463 } else {
1464 /* Disable VLAN tag insertion */
1465 tempval = gfar_read(&priv->regs->tctrl);
1466 tempval &= ~TCTRL_VLINS;
1467 gfar_write(&priv->regs->tctrl, tempval);
1468
1469 /* Disable VLAN tag extraction */
1470 tempval = gfar_read(&priv->regs->rctrl);
1471 tempval &= ~RCTRL_VLEX;
1472 /* If parse is no longer required, then disable parser */
1473 if (tempval & RCTRL_REQ_PARSER)
1474 tempval |= RCTRL_PRSDEP_INIT;
1475 else
1476 tempval &= ~RCTRL_PRSDEP_INIT;
1477 gfar_write(&priv->regs->rctrl, tempval);
1478 }
1479
1480 gfar_change_mtu(dev, dev->mtu);
1481
1482 spin_unlock_irqrestore(&priv->rxlock, flags);
1483 }
1484
1485 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1486 {
1487 int tempsize, tempval;
1488 struct gfar_private *priv = netdev_priv(dev);
1489 int oldsize = priv->rx_buffer_size;
1490 int frame_size = new_mtu + ETH_HLEN;
1491
1492 if (priv->vlgrp)
1493 frame_size += VLAN_HLEN;
1494
1495 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1496 if (netif_msg_drv(priv))
1497 printk(KERN_ERR "%s: Invalid MTU setting\n",
1498 dev->name);
1499 return -EINVAL;
1500 }
1501
1502 if (gfar_uses_fcb(priv))
1503 frame_size += GMAC_FCB_LEN;
1504
1505 frame_size += priv->padding;
1506
1507 tempsize =
1508 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1509 INCREMENTAL_BUFFER_SIZE;
1510
1511 /* Only stop and start the controller if it isn't already
1512 * stopped, and we changed something */
1513 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1514 stop_gfar(dev);
1515
1516 priv->rx_buffer_size = tempsize;
1517
1518 dev->mtu = new_mtu;
1519
1520 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1521 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1522
1523 /* If the mtu is larger than the max size for standard
1524 * ethernet frames (ie, a jumbo frame), then set maccfg2
1525 * to allow huge frames, and to check the length */
1526 tempval = gfar_read(&priv->regs->maccfg2);
1527
1528 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1529 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1530 else
1531 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1532
1533 gfar_write(&priv->regs->maccfg2, tempval);
1534
1535 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1536 startup_gfar(dev);
1537
1538 return 0;
1539 }
1540
1541 /* gfar_reset_task gets scheduled when a packet has not been
1542 * transmitted after a set amount of time.
1543 * For now, assume that clearing out all the structures, and
1544 * starting over will fix the problem.
1545 */
1546 static void gfar_reset_task(struct work_struct *work)
1547 {
1548 struct gfar_private *priv = container_of(work, struct gfar_private,
1549 reset_task);
1550 struct net_device *dev = priv->ndev;
1551
1552 if (dev->flags & IFF_UP) {
1553 netif_stop_queue(dev);
1554 stop_gfar(dev);
1555 startup_gfar(dev);
1556 netif_start_queue(dev);
1557 }
1558
1559 netif_tx_schedule_all(dev);
1560 }
1561
1562 static void gfar_timeout(struct net_device *dev)
1563 {
1564 struct gfar_private *priv = netdev_priv(dev);
1565
1566 dev->stats.tx_errors++;
1567 schedule_work(&priv->reset_task);
1568 }
1569
1570 /* Interrupt Handler for Transmit complete */
1571 static int gfar_clean_tx_ring(struct net_device *dev)
1572 {
1573 struct gfar_private *priv = netdev_priv(dev);
1574 struct txbd8 *bdp;
1575 struct txbd8 *lbdp = NULL;
1576 struct txbd8 *base = priv->tx_bd_base;
1577 struct sk_buff *skb;
1578 int skb_dirtytx;
1579 int tx_ring_size = priv->tx_ring_size;
1580 int frags = 0;
1581 int i;
1582 int howmany = 0;
1583 u32 lstatus;
1584
1585 bdp = priv->dirty_tx;
1586 skb_dirtytx = priv->skb_dirtytx;
1587
1588 while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1589 frags = skb_shinfo(skb)->nr_frags;
1590 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1591
1592 lstatus = lbdp->lstatus;
1593
1594 /* Only clean completed frames */
1595 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1596 (lstatus & BD_LENGTH_MASK))
1597 break;
1598
1599 dma_unmap_single(&priv->ofdev->dev,
1600 bdp->bufPtr,
1601 bdp->length,
1602 DMA_TO_DEVICE);
1603
1604 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1605 bdp = next_txbd(bdp, base, tx_ring_size);
1606
1607 for (i = 0; i < frags; i++) {
1608 dma_unmap_page(&priv->ofdev->dev,
1609 bdp->bufPtr,
1610 bdp->length,
1611 DMA_TO_DEVICE);
1612 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1613 bdp = next_txbd(bdp, base, tx_ring_size);
1614 }
1615
1616 /*
1617 * If there's room in the queue (limit it to rx_buffer_size)
1618 * we add this skb back into the pool, if it's the right size
1619 */
1620 if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size &&
1621 skb_recycle_check(skb, priv->rx_buffer_size +
1622 RXBUF_ALIGNMENT))
1623 __skb_queue_head(&priv->rx_recycle, skb);
1624 else
1625 dev_kfree_skb_any(skb);
1626
1627 priv->tx_skbuff[skb_dirtytx] = NULL;
1628
1629 skb_dirtytx = (skb_dirtytx + 1) &
1630 TX_RING_MOD_MASK(tx_ring_size);
1631
1632 howmany++;
1633 priv->num_txbdfree += frags + 1;
1634 }
1635
1636 /* If we freed a buffer, we can restart transmission, if necessary */
1637 if (netif_queue_stopped(dev) && priv->num_txbdfree)
1638 netif_wake_queue(dev);
1639
1640 /* Update dirty indicators */
1641 priv->skb_dirtytx = skb_dirtytx;
1642 priv->dirty_tx = bdp;
1643
1644 dev->stats.tx_packets += howmany;
1645
1646 return howmany;
1647 }
1648
1649 static void gfar_schedule_cleanup(struct net_device *dev)
1650 {
1651 struct gfar_private *priv = netdev_priv(dev);
1652 unsigned long flags;
1653
1654 spin_lock_irqsave(&priv->txlock, flags);
1655 spin_lock(&priv->rxlock);
1656
1657 if (napi_schedule_prep(&priv->napi)) {
1658 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1659 __napi_schedule(&priv->napi);
1660 } else {
1661 /*
1662 * Clear IEVENT, so interrupts aren't called again
1663 * because of the packets that have already arrived.
1664 */
1665 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1666 }
1667
1668 spin_unlock(&priv->rxlock);
1669 spin_unlock_irqrestore(&priv->txlock, flags);
1670 }
1671
1672 /* Interrupt Handler for Transmit complete */
1673 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1674 {
1675 gfar_schedule_cleanup((struct net_device *)dev_id);
1676 return IRQ_HANDLED;
1677 }
1678
1679 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1680 struct sk_buff *skb)
1681 {
1682 struct gfar_private *priv = netdev_priv(dev);
1683 u32 lstatus;
1684
1685 bdp->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1686 priv->rx_buffer_size, DMA_FROM_DEVICE);
1687
1688 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1689
1690 if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1691 lstatus |= BD_LFLAG(RXBD_WRAP);
1692
1693 eieio();
1694
1695 bdp->lstatus = lstatus;
1696 }
1697
1698
1699 struct sk_buff * gfar_new_skb(struct net_device *dev)
1700 {
1701 unsigned int alignamount;
1702 struct gfar_private *priv = netdev_priv(dev);
1703 struct sk_buff *skb = NULL;
1704
1705 skb = __skb_dequeue(&priv->rx_recycle);
1706 if (!skb)
1707 skb = netdev_alloc_skb(dev,
1708 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1709
1710 if (!skb)
1711 return NULL;
1712
1713 alignamount = RXBUF_ALIGNMENT -
1714 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1715
1716 /* We need the data buffer to be aligned properly. We will reserve
1717 * as many bytes as needed to align the data properly
1718 */
1719 skb_reserve(skb, alignamount);
1720
1721 return skb;
1722 }
1723
1724 static inline void count_errors(unsigned short status, struct net_device *dev)
1725 {
1726 struct gfar_private *priv = netdev_priv(dev);
1727 struct net_device_stats *stats = &dev->stats;
1728 struct gfar_extra_stats *estats = &priv->extra_stats;
1729
1730 /* If the packet was truncated, none of the other errors
1731 * matter */
1732 if (status & RXBD_TRUNCATED) {
1733 stats->rx_length_errors++;
1734
1735 estats->rx_trunc++;
1736
1737 return;
1738 }
1739 /* Count the errors, if there were any */
1740 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1741 stats->rx_length_errors++;
1742
1743 if (status & RXBD_LARGE)
1744 estats->rx_large++;
1745 else
1746 estats->rx_short++;
1747 }
1748 if (status & RXBD_NONOCTET) {
1749 stats->rx_frame_errors++;
1750 estats->rx_nonoctet++;
1751 }
1752 if (status & RXBD_CRCERR) {
1753 estats->rx_crcerr++;
1754 stats->rx_crc_errors++;
1755 }
1756 if (status & RXBD_OVERRUN) {
1757 estats->rx_overrun++;
1758 stats->rx_crc_errors++;
1759 }
1760 }
1761
1762 irqreturn_t gfar_receive(int irq, void *dev_id)
1763 {
1764 gfar_schedule_cleanup((struct net_device *)dev_id);
1765 return IRQ_HANDLED;
1766 }
1767
1768 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1769 {
1770 /* If valid headers were found, and valid sums
1771 * were verified, then we tell the kernel that no
1772 * checksumming is necessary. Otherwise, it is */
1773 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1774 skb->ip_summed = CHECKSUM_UNNECESSARY;
1775 else
1776 skb->ip_summed = CHECKSUM_NONE;
1777 }
1778
1779
1780 /* gfar_process_frame() -- handle one incoming packet if skb
1781 * isn't NULL. */
1782 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1783 int amount_pull)
1784 {
1785 struct gfar_private *priv = netdev_priv(dev);
1786 struct rxfcb *fcb = NULL;
1787
1788 int ret;
1789
1790 /* fcb is at the beginning if exists */
1791 fcb = (struct rxfcb *)skb->data;
1792
1793 /* Remove the FCB from the skb */
1794 /* Remove the padded bytes, if there are any */
1795 if (amount_pull)
1796 skb_pull(skb, amount_pull);
1797
1798 if (priv->rx_csum_enable)
1799 gfar_rx_checksum(skb, fcb);
1800
1801 /* Tell the skb what kind of packet this is */
1802 skb->protocol = eth_type_trans(skb, dev);
1803
1804 /* Send the packet up the stack */
1805 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1806 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1807 else
1808 ret = netif_receive_skb(skb);
1809
1810 if (NET_RX_DROP == ret)
1811 priv->extra_stats.kernel_dropped++;
1812
1813 return 0;
1814 }
1815
1816 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1817 * until the budget/quota has been reached. Returns the number
1818 * of frames handled
1819 */
1820 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1821 {
1822 struct rxbd8 *bdp, *base;
1823 struct sk_buff *skb;
1824 int pkt_len;
1825 int amount_pull;
1826 int howmany = 0;
1827 struct gfar_private *priv = netdev_priv(dev);
1828
1829 /* Get the first full descriptor */
1830 bdp = priv->cur_rx;
1831 base = priv->rx_bd_base;
1832
1833 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1834 priv->padding;
1835
1836 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1837 struct sk_buff *newskb;
1838 rmb();
1839
1840 /* Add another skb for the future */
1841 newskb = gfar_new_skb(dev);
1842
1843 skb = priv->rx_skbuff[priv->skb_currx];
1844
1845 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
1846 priv->rx_buffer_size, DMA_FROM_DEVICE);
1847
1848 /* We drop the frame if we failed to allocate a new buffer */
1849 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1850 bdp->status & RXBD_ERR)) {
1851 count_errors(bdp->status, dev);
1852
1853 if (unlikely(!newskb))
1854 newskb = skb;
1855 else if (skb) {
1856 /*
1857 * We need to reset ->data to what it
1858 * was before gfar_new_skb() re-aligned
1859 * it to an RXBUF_ALIGNMENT boundary
1860 * before we put the skb back on the
1861 * recycle list.
1862 */
1863 skb->data = skb->head + NET_SKB_PAD;
1864 __skb_queue_head(&priv->rx_recycle, skb);
1865 }
1866 } else {
1867 /* Increment the number of packets */
1868 dev->stats.rx_packets++;
1869 howmany++;
1870
1871 if (likely(skb)) {
1872 pkt_len = bdp->length - ETH_FCS_LEN;
1873 /* Remove the FCS from the packet length */
1874 skb_put(skb, pkt_len);
1875 dev->stats.rx_bytes += pkt_len;
1876
1877 if (in_irq() || irqs_disabled())
1878 printk("Interrupt problem!\n");
1879 gfar_process_frame(dev, skb, amount_pull);
1880
1881 } else {
1882 if (netif_msg_rx_err(priv))
1883 printk(KERN_WARNING
1884 "%s: Missing skb!\n", dev->name);
1885 dev->stats.rx_dropped++;
1886 priv->extra_stats.rx_skbmissing++;
1887 }
1888
1889 }
1890
1891 priv->rx_skbuff[priv->skb_currx] = newskb;
1892
1893 /* Setup the new bdp */
1894 gfar_new_rxbdp(dev, bdp, newskb);
1895
1896 /* Update to the next pointer */
1897 bdp = next_bd(bdp, base, priv->rx_ring_size);
1898
1899 /* update to point at the next skb */
1900 priv->skb_currx =
1901 (priv->skb_currx + 1) &
1902 RX_RING_MOD_MASK(priv->rx_ring_size);
1903 }
1904
1905 /* Update the current rxbd pointer to be the next one */
1906 priv->cur_rx = bdp;
1907
1908 return howmany;
1909 }
1910
1911 static int gfar_poll(struct napi_struct *napi, int budget)
1912 {
1913 struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1914 struct net_device *dev = priv->ndev;
1915 int tx_cleaned = 0;
1916 int rx_cleaned = 0;
1917 unsigned long flags;
1918
1919 /* Clear IEVENT, so interrupts aren't called again
1920 * because of the packets that have already arrived */
1921 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1922
1923 /* If we fail to get the lock, don't bother with the TX BDs */
1924 if (spin_trylock_irqsave(&priv->txlock, flags)) {
1925 tx_cleaned = gfar_clean_tx_ring(dev);
1926 spin_unlock_irqrestore(&priv->txlock, flags);
1927 }
1928
1929 rx_cleaned = gfar_clean_rx_ring(dev, budget);
1930
1931 if (tx_cleaned)
1932 return budget;
1933
1934 if (rx_cleaned < budget) {
1935 napi_complete(napi);
1936
1937 /* Clear the halt bit in RSTAT */
1938 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1939
1940 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1941
1942 /* If we are coalescing interrupts, update the timer */
1943 /* Otherwise, clear it */
1944 if (likely(priv->rxcoalescing)) {
1945 gfar_write(&priv->regs->rxic, 0);
1946 gfar_write(&priv->regs->rxic, priv->rxic);
1947 }
1948 if (likely(priv->txcoalescing)) {
1949 gfar_write(&priv->regs->txic, 0);
1950 gfar_write(&priv->regs->txic, priv->txic);
1951 }
1952 }
1953
1954 return rx_cleaned;
1955 }
1956
1957 #ifdef CONFIG_NET_POLL_CONTROLLER
1958 /*
1959 * Polling 'interrupt' - used by things like netconsole to send skbs
1960 * without having to re-enable interrupts. It's not called while
1961 * the interrupt routine is executing.
1962 */
1963 static void gfar_netpoll(struct net_device *dev)
1964 {
1965 struct gfar_private *priv = netdev_priv(dev);
1966
1967 /* If the device has multiple interrupts, run tx/rx */
1968 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1969 disable_irq(priv->interruptTransmit);
1970 disable_irq(priv->interruptReceive);
1971 disable_irq(priv->interruptError);
1972 gfar_interrupt(priv->interruptTransmit, dev);
1973 enable_irq(priv->interruptError);
1974 enable_irq(priv->interruptReceive);
1975 enable_irq(priv->interruptTransmit);
1976 } else {
1977 disable_irq(priv->interruptTransmit);
1978 gfar_interrupt(priv->interruptTransmit, dev);
1979 enable_irq(priv->interruptTransmit);
1980 }
1981 }
1982 #endif
1983
1984 /* The interrupt handler for devices with one interrupt */
1985 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1986 {
1987 struct net_device *dev = dev_id;
1988 struct gfar_private *priv = netdev_priv(dev);
1989
1990 /* Save ievent for future reference */
1991 u32 events = gfar_read(&priv->regs->ievent);
1992
1993 /* Check for reception */
1994 if (events & IEVENT_RX_MASK)
1995 gfar_receive(irq, dev_id);
1996
1997 /* Check for transmit completion */
1998 if (events & IEVENT_TX_MASK)
1999 gfar_transmit(irq, dev_id);
2000
2001 /* Check for errors */
2002 if (events & IEVENT_ERR_MASK)
2003 gfar_error(irq, dev_id);
2004
2005 return IRQ_HANDLED;
2006 }
2007
2008 /* Called every time the controller might need to be made
2009 * aware of new link state. The PHY code conveys this
2010 * information through variables in the phydev structure, and this
2011 * function converts those variables into the appropriate
2012 * register values, and can bring down the device if needed.
2013 */
2014 static void adjust_link(struct net_device *dev)
2015 {
2016 struct gfar_private *priv = netdev_priv(dev);
2017 struct gfar __iomem *regs = priv->regs;
2018 unsigned long flags;
2019 struct phy_device *phydev = priv->phydev;
2020 int new_state = 0;
2021
2022 spin_lock_irqsave(&priv->txlock, flags);
2023 if (phydev->link) {
2024 u32 tempval = gfar_read(&regs->maccfg2);
2025 u32 ecntrl = gfar_read(&regs->ecntrl);
2026
2027 /* Now we make sure that we can be in full duplex mode.
2028 * If not, we operate in half-duplex mode. */
2029 if (phydev->duplex != priv->oldduplex) {
2030 new_state = 1;
2031 if (!(phydev->duplex))
2032 tempval &= ~(MACCFG2_FULL_DUPLEX);
2033 else
2034 tempval |= MACCFG2_FULL_DUPLEX;
2035
2036 priv->oldduplex = phydev->duplex;
2037 }
2038
2039 if (phydev->speed != priv->oldspeed) {
2040 new_state = 1;
2041 switch (phydev->speed) {
2042 case 1000:
2043 tempval =
2044 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2045
2046 ecntrl &= ~(ECNTRL_R100);
2047 break;
2048 case 100:
2049 case 10:
2050 tempval =
2051 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2052
2053 /* Reduced mode distinguishes
2054 * between 10 and 100 */
2055 if (phydev->speed == SPEED_100)
2056 ecntrl |= ECNTRL_R100;
2057 else
2058 ecntrl &= ~(ECNTRL_R100);
2059 break;
2060 default:
2061 if (netif_msg_link(priv))
2062 printk(KERN_WARNING
2063 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2064 dev->name, phydev->speed);
2065 break;
2066 }
2067
2068 priv->oldspeed = phydev->speed;
2069 }
2070
2071 gfar_write(&regs->maccfg2, tempval);
2072 gfar_write(&regs->ecntrl, ecntrl);
2073
2074 if (!priv->oldlink) {
2075 new_state = 1;
2076 priv->oldlink = 1;
2077 }
2078 } else if (priv->oldlink) {
2079 new_state = 1;
2080 priv->oldlink = 0;
2081 priv->oldspeed = 0;
2082 priv->oldduplex = -1;
2083 }
2084
2085 if (new_state && netif_msg_link(priv))
2086 phy_print_status(phydev);
2087
2088 spin_unlock_irqrestore(&priv->txlock, flags);
2089 }
2090
2091 /* Update the hash table based on the current list of multicast
2092 * addresses we subscribe to. Also, change the promiscuity of
2093 * the device based on the flags (this function is called
2094 * whenever dev->flags is changed */
2095 static void gfar_set_multi(struct net_device *dev)
2096 {
2097 struct dev_mc_list *mc_ptr;
2098 struct gfar_private *priv = netdev_priv(dev);
2099 struct gfar __iomem *regs = priv->regs;
2100 u32 tempval;
2101
2102 if(dev->flags & IFF_PROMISC) {
2103 /* Set RCTRL to PROM */
2104 tempval = gfar_read(&regs->rctrl);
2105 tempval |= RCTRL_PROM;
2106 gfar_write(&regs->rctrl, tempval);
2107 } else {
2108 /* Set RCTRL to not PROM */
2109 tempval = gfar_read(&regs->rctrl);
2110 tempval &= ~(RCTRL_PROM);
2111 gfar_write(&regs->rctrl, tempval);
2112 }
2113
2114 if(dev->flags & IFF_ALLMULTI) {
2115 /* Set the hash to rx all multicast frames */
2116 gfar_write(&regs->igaddr0, 0xffffffff);
2117 gfar_write(&regs->igaddr1, 0xffffffff);
2118 gfar_write(&regs->igaddr2, 0xffffffff);
2119 gfar_write(&regs->igaddr3, 0xffffffff);
2120 gfar_write(&regs->igaddr4, 0xffffffff);
2121 gfar_write(&regs->igaddr5, 0xffffffff);
2122 gfar_write(&regs->igaddr6, 0xffffffff);
2123 gfar_write(&regs->igaddr7, 0xffffffff);
2124 gfar_write(&regs->gaddr0, 0xffffffff);
2125 gfar_write(&regs->gaddr1, 0xffffffff);
2126 gfar_write(&regs->gaddr2, 0xffffffff);
2127 gfar_write(&regs->gaddr3, 0xffffffff);
2128 gfar_write(&regs->gaddr4, 0xffffffff);
2129 gfar_write(&regs->gaddr5, 0xffffffff);
2130 gfar_write(&regs->gaddr6, 0xffffffff);
2131 gfar_write(&regs->gaddr7, 0xffffffff);
2132 } else {
2133 int em_num;
2134 int idx;
2135
2136 /* zero out the hash */
2137 gfar_write(&regs->igaddr0, 0x0);
2138 gfar_write(&regs->igaddr1, 0x0);
2139 gfar_write(&regs->igaddr2, 0x0);
2140 gfar_write(&regs->igaddr3, 0x0);
2141 gfar_write(&regs->igaddr4, 0x0);
2142 gfar_write(&regs->igaddr5, 0x0);
2143 gfar_write(&regs->igaddr6, 0x0);
2144 gfar_write(&regs->igaddr7, 0x0);
2145 gfar_write(&regs->gaddr0, 0x0);
2146 gfar_write(&regs->gaddr1, 0x0);
2147 gfar_write(&regs->gaddr2, 0x0);
2148 gfar_write(&regs->gaddr3, 0x0);
2149 gfar_write(&regs->gaddr4, 0x0);
2150 gfar_write(&regs->gaddr5, 0x0);
2151 gfar_write(&regs->gaddr6, 0x0);
2152 gfar_write(&regs->gaddr7, 0x0);
2153
2154 /* If we have extended hash tables, we need to
2155 * clear the exact match registers to prepare for
2156 * setting them */
2157 if (priv->extended_hash) {
2158 em_num = GFAR_EM_NUM + 1;
2159 gfar_clear_exact_match(dev);
2160 idx = 1;
2161 } else {
2162 idx = 0;
2163 em_num = 0;
2164 }
2165
2166 if(dev->mc_count == 0)
2167 return;
2168
2169 /* Parse the list, and set the appropriate bits */
2170 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2171 if (idx < em_num) {
2172 gfar_set_mac_for_addr(dev, idx,
2173 mc_ptr->dmi_addr);
2174 idx++;
2175 } else
2176 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2177 }
2178 }
2179
2180 return;
2181 }
2182
2183
2184 /* Clears each of the exact match registers to zero, so they
2185 * don't interfere with normal reception */
2186 static void gfar_clear_exact_match(struct net_device *dev)
2187 {
2188 int idx;
2189 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2190
2191 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2192 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2193 }
2194
2195 /* Set the appropriate hash bit for the given addr */
2196 /* The algorithm works like so:
2197 * 1) Take the Destination Address (ie the multicast address), and
2198 * do a CRC on it (little endian), and reverse the bits of the
2199 * result.
2200 * 2) Use the 8 most significant bits as a hash into a 256-entry
2201 * table. The table is controlled through 8 32-bit registers:
2202 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2203 * gaddr7. This means that the 3 most significant bits in the
2204 * hash index which gaddr register to use, and the 5 other bits
2205 * indicate which bit (assuming an IBM numbering scheme, which
2206 * for PowerPC (tm) is usually the case) in the register holds
2207 * the entry. */
2208 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2209 {
2210 u32 tempval;
2211 struct gfar_private *priv = netdev_priv(dev);
2212 u32 result = ether_crc(MAC_ADDR_LEN, addr);
2213 int width = priv->hash_width;
2214 u8 whichbit = (result >> (32 - width)) & 0x1f;
2215 u8 whichreg = result >> (32 - width + 5);
2216 u32 value = (1 << (31-whichbit));
2217
2218 tempval = gfar_read(priv->hash_regs[whichreg]);
2219 tempval |= value;
2220 gfar_write(priv->hash_regs[whichreg], tempval);
2221
2222 return;
2223 }
2224
2225
2226 /* There are multiple MAC Address register pairs on some controllers
2227 * This function sets the numth pair to a given address
2228 */
2229 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2230 {
2231 struct gfar_private *priv = netdev_priv(dev);
2232 int idx;
2233 char tmpbuf[MAC_ADDR_LEN];
2234 u32 tempval;
2235 u32 __iomem *macptr = &priv->regs->macstnaddr1;
2236
2237 macptr += num*2;
2238
2239 /* Now copy it into the mac registers backwards, cuz */
2240 /* little endian is silly */
2241 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2242 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2243
2244 gfar_write(macptr, *((u32 *) (tmpbuf)));
2245
2246 tempval = *((u32 *) (tmpbuf + 4));
2247
2248 gfar_write(macptr+1, tempval);
2249 }
2250
2251 /* GFAR error interrupt handler */
2252 static irqreturn_t gfar_error(int irq, void *dev_id)
2253 {
2254 struct net_device *dev = dev_id;
2255 struct gfar_private *priv = netdev_priv(dev);
2256
2257 /* Save ievent for future reference */
2258 u32 events = gfar_read(&priv->regs->ievent);
2259
2260 /* Clear IEVENT */
2261 gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2262
2263 /* Magic Packet is not an error. */
2264 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2265 (events & IEVENT_MAG))
2266 events &= ~IEVENT_MAG;
2267
2268 /* Hmm... */
2269 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2270 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2271 dev->name, events, gfar_read(&priv->regs->imask));
2272
2273 /* Update the error counters */
2274 if (events & IEVENT_TXE) {
2275 dev->stats.tx_errors++;
2276
2277 if (events & IEVENT_LC)
2278 dev->stats.tx_window_errors++;
2279 if (events & IEVENT_CRL)
2280 dev->stats.tx_aborted_errors++;
2281 if (events & IEVENT_XFUN) {
2282 if (netif_msg_tx_err(priv))
2283 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2284 "packet dropped.\n", dev->name);
2285 dev->stats.tx_dropped++;
2286 priv->extra_stats.tx_underrun++;
2287
2288 /* Reactivate the Tx Queues */
2289 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2290 }
2291 if (netif_msg_tx_err(priv))
2292 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2293 }
2294 if (events & IEVENT_BSY) {
2295 dev->stats.rx_errors++;
2296 priv->extra_stats.rx_bsy++;
2297
2298 gfar_receive(irq, dev_id);
2299
2300 if (netif_msg_rx_err(priv))
2301 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2302 dev->name, gfar_read(&priv->regs->rstat));
2303 }
2304 if (events & IEVENT_BABR) {
2305 dev->stats.rx_errors++;
2306 priv->extra_stats.rx_babr++;
2307
2308 if (netif_msg_rx_err(priv))
2309 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2310 }
2311 if (events & IEVENT_EBERR) {
2312 priv->extra_stats.eberr++;
2313 if (netif_msg_rx_err(priv))
2314 printk(KERN_DEBUG "%s: bus error\n", dev->name);
2315 }
2316 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2317 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2318
2319 if (events & IEVENT_BABT) {
2320 priv->extra_stats.tx_babt++;
2321 if (netif_msg_tx_err(priv))
2322 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2323 }
2324 return IRQ_HANDLED;
2325 }
2326
2327 /* work with hotplug and coldplug */
2328 MODULE_ALIAS("platform:fsl-gianfar");
2329
2330 static struct of_device_id gfar_match[] =
2331 {
2332 {
2333 .type = "network",
2334 .compatible = "gianfar",
2335 },
2336 {},
2337 };
2338
2339 /* Structure for a device driver */
2340 static struct of_platform_driver gfar_driver = {
2341 .name = "fsl-gianfar",
2342 .match_table = gfar_match,
2343
2344 .probe = gfar_probe,
2345 .remove = gfar_remove,
2346 .suspend = gfar_suspend,
2347 .resume = gfar_resume,
2348 };
2349
2350 static int __init gfar_init(void)
2351 {
2352 return of_register_platform_driver(&gfar_driver);
2353 }
2354
2355 static void __exit gfar_exit(void)
2356 {
2357 of_unregister_platform_driver(&gfar_driver);
2358 }
2359
2360 module_init(gfar_init);
2361 module_exit(gfar_exit);
2362
Linux with added FPC-III support