drivers/net/pcmcia/nmclan_cs.c

   1 /* ----------------------------------------------------------------------------
   2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
   3   nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
   4
   5   The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
   6   Access Controller for Ethernet (MACE).  It is essentially the Am2150
   7   PCMCIA Ethernet card contained in the Am2150 Demo Kit.
   8
   9 Written by Roger C. Pao <rpao@paonet.org>
  10   Copyright 1995 Roger C. Pao
  11   Linux 2.5 cleanups Copyright Red Hat 2003
  12
  13   This software may be used and distributed according to the terms of
  14   the GNU General Public License.
  15
  16 Ported to Linux 1.3.* network driver environment by
  17   Matti Aarnio <mea@utu.fi>
  18
  19 References
  20
  21   Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
  22   Am79C940 (MACE) Data Sheet, 1994
  23   Am79C90 (C-LANCE) Data Sheet, 1994
  24   Linux PCMCIA Programmer's Guide v1.17
  25   /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
  26
  27   Eric Mears, New Media Corporation
  28   Tom Pollard, New Media Corporation
  29   Dean Siasoyco, New Media Corporation
  30   Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
  31   Donald Becker <becker@scyld.com>
  32   David Hinds <dahinds@users.sourceforge.net>
  33
  34   The Linux client driver is based on the 3c589_cs.c client driver by
  35   David Hinds.
  36
  37   The Linux network driver outline is based on the 3c589_cs.c driver,
  38   the 8390.c driver, and the example skeleton.c kernel code, which are
  39   by Donald Becker.
  40
  41   The Am2150 network driver hardware interface code is based on the
  42   OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
  43
  44   Special thanks for testing and help in debugging this driver goes
  45   to Ken Lesniak.
  46
  47 -------------------------------------------------------------------------------
  48 Driver Notes and Issues
  49 -------------------------------------------------------------------------------
  50
  51 1. Developed on a Dell 320SLi
  52    PCMCIA Card Services 2.6.2
  53    Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
  54
  55 2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
  56    'insmod pcmcia_core.o io_speed=300'.
  57    This will avoid problems with fast systems which causes rx_framecnt
  58    to return random values.
  59
  60 3. If hot extraction does not work for you, use 'ifconfig eth0 down'
  61    before extraction.
  62
  63 4. There is a bad slow-down problem in this driver.
  64
  65 5. Future: Multicast processing.  In the meantime, do _not_ compile your
  66    kernel with multicast ip enabled.
  67
  68 -------------------------------------------------------------------------------
  69 History
  70 -------------------------------------------------------------------------------
  71 Log: nmclan_cs.c,v
  72  * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk>
  73  * Fixed hang on card eject as we probe it
  74  * Cleaned up to use new style locking.
  75  *
  76  * Revision 0.16  1995/07/01  06:42:17  rpao
  77  * Bug fix: nmclan_reset() called CardServices incorrectly.
  78  *
  79  * Revision 0.15  1995/05/24  08:09:47  rpao
  80  * Re-implement MULTI_TX dev->tbusy handling.
  81  *
  82  * Revision 0.14  1995/05/23  03:19:30  rpao
  83  * Added, in nmclan_config(), "tuple.Attributes = 0;".
  84  * Modified MACE ID check to ignore chip revision level.
  85  * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
  86  *
  87  * Revision 0.13  1995/05/18  05:56:34  rpao
  88  * Statistics changes.
  89  * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
  90  * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT.  Fixes driver lockup.
  91  *
  92  * Revision 0.12  1995/05/14  00:12:23  rpao
  93  * Statistics overhaul.
  94  *
  95
  96 95/05/13 rpao   V0.10a
  97                 Bug fix: MACE statistics counters used wrong I/O ports.
  98                 Bug fix: mace_interrupt() needed to allow statistics to be
  99                 processed without RX or TX interrupts pending.
 100 95/05/11 rpao   V0.10
 101                 Multiple transmit request processing.
 102                 Modified statistics to use MACE counters where possible.
 103 95/05/10 rpao   V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
 104                 *Released
 105 95/05/10 rpao   V0.08
 106                 Bug fix: Make all non-exported functions private by using
 107                 static keyword.
 108                 Bug fix: Test IntrCnt _before_ reading MACE_IR.
 109 95/05/10 rpao   V0.07 Statistics.
 110 95/05/09 rpao   V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
 111
 112 ---------------------------------------------------------------------------- */
 113
 114 #define DRV_NAME        "nmclan_cs"
 115 #define DRV_VERSION     "0.16"
 116
 117
 118 /* ----------------------------------------------------------------------------
 119 Conditional Compilation Options
 120 ---------------------------------------------------------------------------- */
 121
 122 #define MULTI_TX                        0
 123 #define RESET_ON_TIMEOUT                1
 124 #define TX_INTERRUPTABLE                1
 125 #define RESET_XILINX                    0
 126
 127 /* ----------------------------------------------------------------------------
 128 Include Files
 129 ---------------------------------------------------------------------------- */
 130
 131 #include <linux/module.h>
 132 #include <linux/kernel.h>
 133 #include <linux/init.h>
 134 #include <linux/ptrace.h>
 135 #include <linux/slab.h>
 136 #include <linux/string.h>
 137 #include <linux/timer.h>
 138 #include <linux/interrupt.h>
 139 #include <linux/in.h>
 140 #include <linux/delay.h>
 141 #include <linux/ethtool.h>
 142 #include <linux/netdevice.h>
 143 #include <linux/etherdevice.h>
 144 #include <linux/skbuff.h>
 145 #include <linux/if_arp.h>
 146 #include <linux/ioport.h>
 147 #include <linux/bitops.h>
 148
 149 #include <pcmcia/cs_types.h>
 150 #include <pcmcia/cs.h>
 151 #include <pcmcia/cisreg.h>
 152 #include <pcmcia/cistpl.h>
 153 #include <pcmcia/ds.h>
 154
 155 #include <asm/uaccess.h>
 156 #include <asm/io.h>
 157 #include <asm/system.h>
 158
 159 /* ----------------------------------------------------------------------------
 160 Defines
 161 ---------------------------------------------------------------------------- */
 162
 163 #define ETHER_ADDR_LEN                  ETH_ALEN
 164                                         /* 6 bytes in an Ethernet Address */
 165 #define MACE_LADRF_LEN                  8
 166                                         /* 8 bytes in Logical Address Filter */
 167
 168 /* Loop Control Defines */
 169 #define MACE_MAX_IR_ITERATIONS          10
 170 #define MACE_MAX_RX_ITERATIONS          12
 171         /*
 172         TBD: Dean brought this up, and I assumed the hardware would
 173         handle it:
 174
 175         If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
 176         non-zero when the isr exits.  We may not get another interrupt
 177         to process the remaining packets for some time.
 178         */
 179
 180 /*
 181 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
 182 which manages the interface between the MACE and the PCMCIA bus.  It
 183 also includes buffer management for the 32K x 8 SRAM to control up to
 184 four transmit and 12 receive frames at a time.
 185 */
 186 #define AM2150_MAX_TX_FRAMES            4
 187 #define AM2150_MAX_RX_FRAMES            12
 188
 189 /* Am2150 Ethernet Card I/O Mapping */
 190 #define AM2150_RCV                      0x00
 191 #define AM2150_XMT                      0x04
 192 #define AM2150_XMT_SKIP                 0x09
 193 #define AM2150_RCV_NEXT                 0x0A
 194 #define AM2150_RCV_FRAME_COUNT          0x0B
 195 #define AM2150_MACE_BANK                0x0C
 196 #define AM2150_MACE_BASE                0x10
 197
 198 /* MACE Registers */
 199 #define MACE_RCVFIFO                    0
 200 #define MACE_XMTFIFO                    1
 201 #define MACE_XMTFC                      2
 202 #define MACE_XMTFS                      3
 203 #define MACE_XMTRC                      4
 204 #define MACE_RCVFC                      5
 205 #define MACE_RCVFS                      6
 206 #define MACE_FIFOFC                     7
 207 #define MACE_IR                         8
 208 #define MACE_IMR                        9
 209 #define MACE_PR                         10
 210 #define MACE_BIUCC                      11
 211 #define MACE_FIFOCC                     12
 212 #define MACE_MACCC                      13
 213 #define MACE_PLSCC                      14
 214 #define MACE_PHYCC                      15
 215 #define MACE_CHIPIDL                    16
 216 #define MACE_CHIPIDH                    17
 217 #define MACE_IAC                        18
 218 /* Reserved */
 219 #define MACE_LADRF                      20
 220 #define MACE_PADR                       21
 221 /* Reserved */
 222 /* Reserved */
 223 #define MACE_MPC                        24
 224 /* Reserved */
 225 #define MACE_RNTPC                      26
 226 #define MACE_RCVCC                      27
 227 /* Reserved */
 228 #define MACE_UTR                        29
 229 #define MACE_RTR1                       30
 230 #define MACE_RTR2                       31
 231
 232 /* MACE Bit Masks */
 233 #define MACE_XMTRC_EXDEF                0x80
 234 #define MACE_XMTRC_XMTRC                0x0F
 235
 236 #define MACE_XMTFS_XMTSV                0x80
 237 #define MACE_XMTFS_UFLO                 0x40
 238 #define MACE_XMTFS_LCOL                 0x20
 239 #define MACE_XMTFS_MORE                 0x10
 240 #define MACE_XMTFS_ONE                  0x08
 241 #define MACE_XMTFS_DEFER                0x04
 242 #define MACE_XMTFS_LCAR                 0x02
 243 #define MACE_XMTFS_RTRY                 0x01
 244
 245 #define MACE_RCVFS_RCVSTS               0xF000
 246 #define MACE_RCVFS_OFLO                 0x8000
 247 #define MACE_RCVFS_CLSN                 0x4000
 248 #define MACE_RCVFS_FRAM                 0x2000
 249 #define MACE_RCVFS_FCS                  0x1000
 250
 251 #define MACE_FIFOFC_RCVFC               0xF0
 252 #define MACE_FIFOFC_XMTFC               0x0F
 253
 254 #define MACE_IR_JAB                     0x80
 255 #define MACE_IR_BABL                    0x40
 256 #define MACE_IR_CERR                    0x20
 257 #define MACE_IR_RCVCCO                  0x10
 258 #define MACE_IR_RNTPCO                  0x08
 259 #define MACE_IR_MPCO                    0x04
 260 #define MACE_IR_RCVINT                  0x02
 261 #define MACE_IR_XMTINT                  0x01
 262
 263 #define MACE_MACCC_PROM                 0x80
 264 #define MACE_MACCC_DXMT2PD              0x40
 265 #define MACE_MACCC_EMBA                 0x20
 266 #define MACE_MACCC_RESERVED             0x10
 267 #define MACE_MACCC_DRCVPA               0x08
 268 #define MACE_MACCC_DRCVBC               0x04
 269 #define MACE_MACCC_ENXMT                0x02
 270 #define MACE_MACCC_ENRCV                0x01
 271
 272 #define MACE_PHYCC_LNKFL                0x80
 273 #define MACE_PHYCC_DLNKTST              0x40
 274 #define MACE_PHYCC_REVPOL               0x20
 275 #define MACE_PHYCC_DAPC                 0x10
 276 #define MACE_PHYCC_LRT                  0x08
 277 #define MACE_PHYCC_ASEL                 0x04
 278 #define MACE_PHYCC_RWAKE                0x02
 279 #define MACE_PHYCC_AWAKE                0x01
 280
 281 #define MACE_IAC_ADDRCHG                0x80
 282 #define MACE_IAC_PHYADDR                0x04
 283 #define MACE_IAC_LOGADDR                0x02
 284
 285 #define MACE_UTR_RTRE                   0x80
 286 #define MACE_UTR_RTRD                   0x40
 287 #define MACE_UTR_RPA                    0x20
 288 #define MACE_UTR_FCOLL                  0x10
 289 #define MACE_UTR_RCVFCSE                0x08
 290 #define MACE_UTR_LOOP_INCL_MENDEC       0x06
 291 #define MACE_UTR_LOOP_NO_MENDEC         0x04
 292 #define MACE_UTR_LOOP_EXTERNAL          0x02
 293 #define MACE_UTR_LOOP_NONE              0x00
 294 #define MACE_UTR_RESERVED               0x01
 295
 296 /* Switch MACE register bank (only 0 and 1 are valid) */
 297 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
 298
 299 #define MACE_IMR_DEFAULT \
 300   (0xFF - \
 301     ( \
 302       MACE_IR_CERR | \
 303       MACE_IR_RCVCCO | \
 304       MACE_IR_RNTPCO | \
 305       MACE_IR_MPCO | \
 306       MACE_IR_RCVINT | \
 307       MACE_IR_XMTINT \
 308     ) \
 309   )
 310 #undef MACE_IMR_DEFAULT
 311 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
 312
 313 #define TX_TIMEOUT              ((400*HZ)/1000)
 314
 315 /* ----------------------------------------------------------------------------
 316 Type Definitions
 317 ---------------------------------------------------------------------------- */
 318
 319 typedef struct _mace_statistics {
 320     /* MACE_XMTFS */
 321     int xmtsv;
 322     int uflo;
 323     int lcol;
 324     int more;
 325     int one;
 326     int defer;
 327     int lcar;
 328     int rtry;
 329
 330     /* MACE_XMTRC */
 331     int exdef;
 332     int xmtrc;
 333
 334     /* RFS1--Receive Status (RCVSTS) */
 335     int oflo;
 336     int clsn;
 337     int fram;
 338     int fcs;
 339
 340     /* RFS2--Runt Packet Count (RNTPC) */
 341     int rfs_rntpc;
 342
 343     /* RFS3--Receive Collision Count (RCVCC) */
 344     int rfs_rcvcc;
 345
 346     /* MACE_IR */
 347     int jab;
 348     int babl;
 349     int cerr;
 350     int rcvcco;
 351     int rntpco;
 352     int mpco;
 353
 354     /* MACE_MPC */
 355     int mpc;
 356
 357     /* MACE_RNTPC */
 358     int rntpc;
 359
 360     /* MACE_RCVCC */
 361     int rcvcc;
 362 } mace_statistics;
 363
 364 typedef struct _mace_private {
 365         struct pcmcia_device    *p_dev;
 366     dev_node_t node;
 367     struct net_device_stats linux_stats; /* Linux statistics counters */
 368     mace_statistics mace_stats; /* MACE chip statistics counters */
 369
 370     /* restore_multicast_list() state variables */
 371     int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
 372     int multicast_num_addrs;
 373
 374     char tx_free_frames; /* Number of free transmit frame buffers */
 375     char tx_irq_disabled; /* MACE TX interrupt disabled */
 376
 377     spinlock_t bank_lock; /* Must be held if you step off bank 0 */
 378 } mace_private;
 379
 380 /* ----------------------------------------------------------------------------
 381 Private Global Variables
 382 ---------------------------------------------------------------------------- */
 383
 384 #ifdef PCMCIA_DEBUG
 385 static char rcsid[] =
 386 "nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao";
 387 static char *version =
 388 DRV_NAME " " DRV_VERSION " (Roger C. Pao)";
 389 #endif
 390
 391 static const char *if_names[]={
 392     "Auto", "10baseT", "BNC",
 393 };
 394
 395 /* ----------------------------------------------------------------------------
 396 Parameters
 397         These are the parameters that can be set during loading with
 398         'insmod'.
 399 ---------------------------------------------------------------------------- */
 400
 401 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
 402 MODULE_LICENSE("GPL");
 403
 404 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
 405
 406 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
 407 INT_MODULE_PARM(if_port, 0);
 408
 409 #ifdef PCMCIA_DEBUG
 410 INT_MODULE_PARM(pc_debug, PCMCIA_DEBUG);
 411 #define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args)
 412 #else
 413 #define DEBUG(n, args...)
 414 #endif
 415
 416 /* ----------------------------------------------------------------------------
 417 Function Prototypes
 418 ---------------------------------------------------------------------------- */
 419
 420 static int nmclan_config(struct pcmcia_device *link);
 421 static void nmclan_release(struct pcmcia_device *link);
 422
 423 static void nmclan_reset(struct net_device *dev);
 424 static int mace_config(struct net_device *dev, struct ifmap *map);
 425 static int mace_open(struct net_device *dev);
 426 static int mace_close(struct net_device *dev);
 427 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev);
 428 static void mace_tx_timeout(struct net_device *dev);
 429 static irqreturn_t mace_interrupt(int irq, void *dev_id);
 430 static struct net_device_stats *mace_get_stats(struct net_device *dev);
 431 static int mace_rx(struct net_device *dev, unsigned char RxCnt);
 432 static void restore_multicast_list(struct net_device *dev);
 433 static void set_multicast_list(struct net_device *dev);
 434 static const struct ethtool_ops netdev_ethtool_ops;
 435
 436
 437 static void nmclan_detach(struct pcmcia_device *p_dev);
 438
 439 static const struct net_device_ops mace_netdev_ops = {
 440         .ndo_open               = mace_open,
 441         .ndo_stop               = mace_close,
 442         .ndo_start_xmit         = mace_start_xmit,
 443         .ndo_tx_timeout         = mace_tx_timeout,
 444         .ndo_set_config         = mace_config,
 445         .ndo_get_stats          = mace_get_stats,
 446         .ndo_set_multicast_list = set_multicast_list,
 447         .ndo_change_mtu         = eth_change_mtu,
 448         .ndo_set_mac_address    = eth_mac_addr,
 449         .ndo_validate_addr      = eth_validate_addr,
 450 };
 451
 452 /* ----------------------------------------------------------------------------
 453 nmclan_attach
 454         Creates an "instance" of the driver, allocating local data
 455         structures for one device.  The device is registered with Card
 456         Services.
 457 ---------------------------------------------------------------------------- */
 458
 459 static int nmclan_probe(struct pcmcia_device *link)
 460 {
 461     mace_private *lp;
 462     struct net_device *dev;
 463
 464     DEBUG(0, "nmclan_attach()\n");
 465     DEBUG(1, "%s\n", rcsid);
 466
 467     /* Create new ethernet device */
 468     dev = alloc_etherdev(sizeof(mace_private));
 469     if (!dev)
 470             return -ENOMEM;
 471     lp = netdev_priv(dev);
 472     lp->p_dev = link;
 473     link->priv = dev;
 474
 475     spin_lock_init(&lp->bank_lock);
 476     link->io.NumPorts1 = 32;
 477     link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
 478     link->io.IOAddrLines = 5;
 479     link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
 480     link->irq.IRQInfo1 = IRQ_LEVEL_ID;
 481     link->irq.Handler = &mace_interrupt;
 482     link->irq.Instance = dev;
 483     link->conf.Attributes = CONF_ENABLE_IRQ;
 484     link->conf.IntType = INT_MEMORY_AND_IO;
 485     link->conf.ConfigIndex = 1;
 486     link->conf.Present = PRESENT_OPTION;
 487
 488     lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 489
 490     dev->netdev_ops = &mace_netdev_ops;
 491     SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
 492     dev->watchdog_timeo = TX_TIMEOUT;
 493
 494     return nmclan_config(link);
 495 } /* nmclan_attach */
 496
 497 /* ----------------------------------------------------------------------------
 498 nmclan_detach
 499         This deletes a driver "instance".  The device is de-registered
 500         with Card Services.  If it has been released, all local data
 501         structures are freed.  Otherwise, the structures will be freed
 502         when the device is released.
 503 ---------------------------------------------------------------------------- */
 504
 505 static void nmclan_detach(struct pcmcia_device *link)
 506 {
 507     struct net_device *dev = link->priv;
 508
 509     DEBUG(0, "nmclan_detach(0x%p)\n", link);
 510
 511     if (link->dev_node)
 512         unregister_netdev(dev);
 513
 514     nmclan_release(link);
 515
 516     free_netdev(dev);
 517 } /* nmclan_detach */
 518
 519 /* ----------------------------------------------------------------------------
 520 mace_read
 521         Reads a MACE register.  This is bank independent; however, the
 522         caller must ensure that this call is not interruptable.  We are
 523         assuming that during normal operation, the MACE is always in
 524         bank 0.
 525 ---------------------------------------------------------------------------- */
 526 static int mace_read(mace_private *lp, unsigned int ioaddr, int reg)
 527 {
 528   int data = 0xFF;
 529   unsigned long flags;
 530
 531   switch (reg >> 4) {
 532     case 0: /* register 0-15 */
 533       data = inb(ioaddr + AM2150_MACE_BASE + reg);
 534       break;
 535     case 1: /* register 16-31 */
 536       spin_lock_irqsave(&lp->bank_lock, flags);
 537       MACEBANK(1);
 538       data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
 539       MACEBANK(0);
 540       spin_unlock_irqrestore(&lp->bank_lock, flags);
 541       break;
 542   }
 543   return (data & 0xFF);
 544 } /* mace_read */
 545
 546 /* ----------------------------------------------------------------------------
 547 mace_write
 548         Writes to a MACE register.  This is bank independent; however,
 549         the caller must ensure that this call is not interruptable.  We
 550         are assuming that during normal operation, the MACE is always in
 551         bank 0.
 552 ---------------------------------------------------------------------------- */
 553 static void mace_write(mace_private *lp, unsigned int ioaddr, int reg,
 554                        int data)
 555 {
 556   unsigned long flags;
 557
 558   switch (reg >> 4) {
 559     case 0: /* register 0-15 */
 560       outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
 561       break;
 562     case 1: /* register 16-31 */
 563       spin_lock_irqsave(&lp->bank_lock, flags);
 564       MACEBANK(1);
 565       outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
 566       MACEBANK(0);
 567       spin_unlock_irqrestore(&lp->bank_lock, flags);
 568       break;
 569   }
 570 } /* mace_write */
 571
 572 /* ----------------------------------------------------------------------------
 573 mace_init
 574         Resets the MACE chip.
 575 ---------------------------------------------------------------------------- */
 576 static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr)
 577 {
 578   int i;
 579   int ct = 0;
 580
 581   /* MACE Software reset */
 582   mace_write(lp, ioaddr, MACE_BIUCC, 1);
 583   while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
 584     /* Wait for reset bit to be cleared automatically after <= 200ns */;
 585     if(++ct > 500)
 586     {
 587         printk(KERN_ERR "mace: reset failed, card removed ?\n");
 588         return -1;
 589     }
 590     udelay(1);
 591   }
 592   mace_write(lp, ioaddr, MACE_BIUCC, 0);
 593
 594   /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
 595   mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
 596
 597   mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
 598   mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
 599
 600   /*
 601    * Bit 2-1 PORTSEL[1-0] Port Select.
 602    * 00 AUI/10Base-2
 603    * 01 10Base-T
 604    * 10 DAI Port (reserved in Am2150)
 605    * 11 GPSI
 606    * For this card, only the first two are valid.
 607    * So, PLSCC should be set to
 608    * 0x00 for 10Base-2
 609    * 0x02 for 10Base-T
 610    * Or just set ASEL in PHYCC below!
 611    */
 612   switch (if_port) {
 613     case 1:
 614       mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
 615       break;
 616     case 2:
 617       mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
 618       break;
 619     default:
 620       mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
 621       /* ASEL Auto Select.  When set, the PORTSEL[1-0] bits are overridden,
 622          and the MACE device will automatically select the operating media
 623          interface port. */
 624       break;
 625   }
 626
 627   mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
 628   /* Poll ADDRCHG bit */
 629   ct = 0;
 630   while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
 631   {
 632         if(++ ct > 500)
 633         {
 634                 printk(KERN_ERR "mace: ADDRCHG timeout, card removed ?\n");
 635                 return -1;
 636         }
 637   }
 638   /* Set PADR register */
 639   for (i = 0; i < ETHER_ADDR_LEN; i++)
 640     mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
 641
 642   /* MAC Configuration Control Register should be written last */
 643   /* Let set_multicast_list set this. */
 644   /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
 645   mace_write(lp, ioaddr, MACE_MACCC, 0x00);
 646   return 0;
 647 } /* mace_init */
 648
 649 /* ----------------------------------------------------------------------------
 650 nmclan_config
 651         This routine is scheduled to run after a CARD_INSERTION event
 652         is received, to configure the PCMCIA socket, and to make the
 653         ethernet device available to the system.
 654 ---------------------------------------------------------------------------- */
 655
 656 #define CS_CHECK(fn, ret) \
 657   do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
 658
 659 static int nmclan_config(struct pcmcia_device *link)
 660 {
 661   struct net_device *dev = link->priv;
 662   mace_private *lp = netdev_priv(dev);
 663   tuple_t tuple;
 664   u_char buf[64];
 665   int i, last_ret, last_fn;
 666   unsigned int ioaddr;
 667
 668   DEBUG(0, "nmclan_config(0x%p)\n", link);
 669
 670   CS_CHECK(RequestIO, pcmcia_request_io(link, &link->io));
 671   CS_CHECK(RequestIRQ, pcmcia_request_irq(link, &link->irq));
 672   CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link, &link->conf));
 673   dev->irq = link->irq.AssignedIRQ;
 674   dev->base_addr = link->io.BasePort1;
 675
 676   ioaddr = dev->base_addr;
 677
 678   /* Read the ethernet address from the CIS. */
 679   tuple.DesiredTuple = 0x80 /* CISTPL_CFTABLE_ENTRY_MISC */;
 680   tuple.TupleData = buf;
 681   tuple.TupleDataMax = 64;
 682   tuple.TupleOffset = 0;
 683   tuple.Attributes = 0;
 684   CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
 685   CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
 686   memcpy(dev->dev_addr, tuple.TupleData, ETHER_ADDR_LEN);
 687
 688   /* Verify configuration by reading the MACE ID. */
 689   {
 690     char sig[2];
 691
 692     sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
 693     sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
 694     if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
 695       DEBUG(0, "nmclan_cs configured: mace id=%x %x\n",
 696             sig[0], sig[1]);
 697     } else {
 698       printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should"
 699              " be 0x40 0x?9\n", sig[0], sig[1]);
 700       return -ENODEV;
 701     }
 702   }
 703
 704   if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
 705         goto failed;
 706
 707   /* The if_port symbol can be set when the module is loaded */
 708   if (if_port <= 2)
 709     dev->if_port = if_port;
 710   else
 711     printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n");
 712
 713   link->dev_node = &lp->node;
 714   SET_NETDEV_DEV(dev, &handle_to_dev(link));
 715
 716   i = register_netdev(dev);
 717   if (i != 0) {
 718     printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n");
 719     link->dev_node = NULL;
 720     goto failed;
 721   }
 722
 723   strcpy(lp->node.dev_name, dev->name);
 724
 725   printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port,"
 726          " hw_addr %pM\n",
 727          dev->name, dev->base_addr, dev->irq, if_names[dev->if_port],
 728          dev->dev_addr);
 729   return 0;
 730
 731 cs_failed:
 732         cs_error(link, last_fn, last_ret);
 733 failed:
 734         nmclan_release(link);
 735         return -ENODEV;
 736 } /* nmclan_config */
 737
 738 /* ----------------------------------------------------------------------------
 739 nmclan_release
 740         After a card is removed, nmclan_release() will unregister the
 741         net device, and release the PCMCIA configuration.  If the device
 742         is still open, this will be postponed until it is closed.
 743 ---------------------------------------------------------------------------- */
 744 static void nmclan_release(struct pcmcia_device *link)
 745 {
 746         DEBUG(0, "nmclan_release(0x%p)\n", link);
 747         pcmcia_disable_device(link);
 748 }
 749
 750 static int nmclan_suspend(struct pcmcia_device *link)
 751 {
 752         struct net_device *dev = link->priv;
 753
 754         if (link->open)
 755                 netif_device_detach(dev);
 756
 757         return 0;
 758 }
 759
 760 static int nmclan_resume(struct pcmcia_device *link)
 761 {
 762         struct net_device *dev = link->priv;
 763
 764         if (link->open) {
 765                 nmclan_reset(dev);
 766                 netif_device_attach(dev);
 767         }
 768
 769         return 0;
 770 }
 771
 772
 773 /* ----------------------------------------------------------------------------
 774 nmclan_reset
 775         Reset and restore all of the Xilinx and MACE registers.
 776 ---------------------------------------------------------------------------- */
 777 static void nmclan_reset(struct net_device *dev)
 778 {
 779   mace_private *lp = netdev_priv(dev);
 780
 781 #if RESET_XILINX
 782   struct pcmcia_device *link = &lp->link;
 783   conf_reg_t reg;
 784   u_long OrigCorValue;
 785
 786   /* Save original COR value */
 787   reg.Function = 0;
 788   reg.Action = CS_READ;
 789   reg.Offset = CISREG_COR;
 790   reg.Value = 0;
 791   pcmcia_access_configuration_register(link, &reg);
 792   OrigCorValue = reg.Value;
 793
 794   /* Reset Xilinx */
 795   reg.Action = CS_WRITE;
 796   reg.Offset = CISREG_COR;
 797   DEBUG(1, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n",
 798         OrigCorValue);
 799   reg.Value = COR_SOFT_RESET;
 800   pcmcia_access_configuration_register(link, &reg);
 801   /* Need to wait for 20 ms for PCMCIA to finish reset. */
 802
 803   /* Restore original COR configuration index */
 804   reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK);
 805   pcmcia_access_configuration_register(link, &reg);
 806   /* Xilinx is now completely reset along with the MACE chip. */
 807   lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 808
 809 #endif /* #if RESET_XILINX */
 810
 811   /* Xilinx is now completely reset along with the MACE chip. */
 812   lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 813
 814   /* Reinitialize the MACE chip for operation. */
 815   mace_init(lp, dev->base_addr, dev->dev_addr);
 816   mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
 817
 818   /* Restore the multicast list and enable TX and RX. */
 819   restore_multicast_list(dev);
 820 } /* nmclan_reset */
 821
 822 /* ----------------------------------------------------------------------------
 823 mace_config
 824         [Someone tell me what this is supposed to do?  Is if_port a defined
 825         standard?  If so, there should be defines to indicate 1=10Base-T,
 826         2=10Base-2, etc. including limited automatic detection.]
 827 ---------------------------------------------------------------------------- */
 828 static int mace_config(struct net_device *dev, struct ifmap *map)
 829 {
 830   if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
 831     if (map->port <= 2) {
 832       dev->if_port = map->port;
 833       printk(KERN_INFO "%s: switched to %s port\n", dev->name,
 834              if_names[dev->if_port]);
 835     } else
 836       return -EINVAL;
 837   }
 838   return 0;
 839 } /* mace_config */
 840
 841 /* ----------------------------------------------------------------------------
 842 mace_open
 843         Open device driver.
 844 ---------------------------------------------------------------------------- */
 845 static int mace_open(struct net_device *dev)
 846 {
 847   unsigned int ioaddr = dev->base_addr;
 848   mace_private *lp = netdev_priv(dev);
 849   struct pcmcia_device *link = lp->p_dev;
 850
 851   if (!pcmcia_dev_present(link))
 852     return -ENODEV;
 853
 854   link->open++;
 855
 856   MACEBANK(0);
 857
 858   netif_start_queue(dev);
 859   nmclan_reset(dev);
 860
 861   return 0; /* Always succeed */
 862 } /* mace_open */
 863
 864 /* ----------------------------------------------------------------------------
 865 mace_close
 866         Closes device driver.
 867 ---------------------------------------------------------------------------- */
 868 static int mace_close(struct net_device *dev)
 869 {
 870   unsigned int ioaddr = dev->base_addr;
 871   mace_private *lp = netdev_priv(dev);
 872   struct pcmcia_device *link = lp->p_dev;
 873
 874   DEBUG(2, "%s: shutting down ethercard.\n", dev->name);
 875
 876   /* Mask off all interrupts from the MACE chip. */
 877   outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
 878
 879   link->open--;
 880   netif_stop_queue(dev);
 881
 882   return 0;
 883 } /* mace_close */
 884
 885 static void netdev_get_drvinfo(struct net_device *dev,
 886                                struct ethtool_drvinfo *info)
 887 {
 888         strcpy(info->driver, DRV_NAME);
 889         strcpy(info->version, DRV_VERSION);
 890         sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr);
 891 }
 892
 893 #ifdef PCMCIA_DEBUG
 894 static u32 netdev_get_msglevel(struct net_device *dev)
 895 {
 896         return pc_debug;
 897 }
 898
 899 static void netdev_set_msglevel(struct net_device *dev, u32 level)
 900 {
 901         pc_debug = level;
 902 }
 903 #endif /* PCMCIA_DEBUG */
 904
 905 static const struct ethtool_ops netdev_ethtool_ops = {
 906         .get_drvinfo            = netdev_get_drvinfo,
 907 #ifdef PCMCIA_DEBUG
 908         .get_msglevel           = netdev_get_msglevel,
 909         .set_msglevel           = netdev_set_msglevel,
 910 #endif /* PCMCIA_DEBUG */
 911 };
 912
 913 /* ----------------------------------------------------------------------------
 914 mace_start_xmit
 915         This routine begins the packet transmit function.  When completed,
 916         it will generate a transmit interrupt.
 917
 918         According to /usr/src/linux/net/inet/dev.c, if _start_xmit
 919         returns 0, the "packet is now solely the responsibility of the
 920         driver."  If _start_xmit returns non-zero, the "transmission
 921         failed, put skb back into a list."
 922 ---------------------------------------------------------------------------- */
 923
 924 static void mace_tx_timeout(struct net_device *dev)
 925 {
 926   mace_private *lp = netdev_priv(dev);
 927   struct pcmcia_device *link = lp->p_dev;
 928
 929   printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name);
 930 #if RESET_ON_TIMEOUT
 931   printk("resetting card\n");
 932   pcmcia_reset_card(link->socket);
 933 #else /* #if RESET_ON_TIMEOUT */
 934   printk("NOT resetting card\n");
 935 #endif /* #if RESET_ON_TIMEOUT */
 936   dev->trans_start = jiffies;
 937   netif_wake_queue(dev);
 938 }
 939
 940 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev)
 941 {
 942   mace_private *lp = netdev_priv(dev);
 943   unsigned int ioaddr = dev->base_addr;
 944
 945   netif_stop_queue(dev);
 946
 947   DEBUG(3, "%s: mace_start_xmit(length = %ld) called.\n",
 948         dev->name, (long)skb->len);
 949
 950 #if (!TX_INTERRUPTABLE)
 951   /* Disable MACE TX interrupts. */
 952   outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
 953     ioaddr + AM2150_MACE_BASE + MACE_IMR);
 954   lp->tx_irq_disabled=1;
 955 #endif /* #if (!TX_INTERRUPTABLE) */
 956
 957   {
 958     /* This block must not be interrupted by another transmit request!
 959        mace_tx_timeout will take care of timer-based retransmissions from
 960        the upper layers.  The interrupt handler is guaranteed never to
 961        service a transmit interrupt while we are in here.
 962     */
 963
 964     lp->linux_stats.tx_bytes += skb->len;
 965     lp->tx_free_frames--;
 966
 967     /* WARNING: Write the _exact_ number of bytes written in the header! */
 968     /* Put out the word header [must be an outw()] . . . */
 969     outw(skb->len, ioaddr + AM2150_XMT);
 970     /* . . . and the packet [may be any combination of outw() and outb()] */
 971     outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
 972     if (skb->len & 1) {
 973       /* Odd byte transfer */
 974       outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
 975     }
 976
 977     dev->trans_start = jiffies;
 978
 979 #if MULTI_TX
 980     if (lp->tx_free_frames > 0)
 981       netif_start_queue(dev);
 982 #endif /* #if MULTI_TX */
 983   }
 984
 985 #if (!TX_INTERRUPTABLE)
 986   /* Re-enable MACE TX interrupts. */
 987   lp->tx_irq_disabled=0;
 988   outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
 989 #endif /* #if (!TX_INTERRUPTABLE) */
 990
 991   dev_kfree_skb(skb);
 992
 993   return NETDEV_TX_OK;
 994 } /* mace_start_xmit */
 995
 996 /* ----------------------------------------------------------------------------
 997 mace_interrupt
 998         The interrupt handler.
 999 ---------------------------------------------------------------------------- */
1000 static irqreturn_t mace_interrupt(int irq, void *dev_id)
1001 {
1002   struct net_device *dev = (struct net_device *) dev_id;
1003   mace_private *lp = netdev_priv(dev);
1004   unsigned int ioaddr;
1005   int status;
1006   int IntrCnt = MACE_MAX_IR_ITERATIONS;
1007
1008   if (dev == NULL) {
1009     DEBUG(2, "mace_interrupt(): irq 0x%X for unknown device.\n",
1010           irq);
1011     return IRQ_NONE;
1012   }
1013
1014   ioaddr = dev->base_addr;
1015
1016   if (lp->tx_irq_disabled) {
1017     printk(
1018       (lp->tx_irq_disabled?
1019        KERN_NOTICE "%s: Interrupt with tx_irq_disabled "
1020        "[isr=%02X, imr=%02X]\n":
1021        KERN_NOTICE "%s: Re-entering the interrupt handler "
1022        "[isr=%02X, imr=%02X]\n"),
1023       dev->name,
1024       inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
1025       inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)
1026     );
1027     /* WARNING: MACE_IR has been read! */
1028     return IRQ_NONE;
1029   }
1030
1031   if (!netif_device_present(dev)) {
1032     DEBUG(2, "%s: interrupt from dead card\n", dev->name);
1033     return IRQ_NONE;
1034   }
1035
1036   do {
1037     /* WARNING: MACE_IR is a READ/CLEAR port! */
1038     status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
1039
1040     DEBUG(3, "mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
1041
1042     if (status & MACE_IR_RCVINT) {
1043       mace_rx(dev, MACE_MAX_RX_ITERATIONS);
1044     }
1045
1046     if (status & MACE_IR_XMTINT) {
1047       unsigned char fifofc;
1048       unsigned char xmtrc;
1049       unsigned char xmtfs;
1050
1051       fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
1052       if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
1053         lp->linux_stats.tx_errors++;
1054         outb(0xFF, ioaddr + AM2150_XMT_SKIP);
1055       }
1056
1057       /* Transmit Retry Count (XMTRC, reg 4) */
1058       xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
1059       if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
1060       lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
1061
1062       if (
1063         (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
1064         MACE_XMTFS_XMTSV /* Transmit Status Valid */
1065       ) {
1066         lp->mace_stats.xmtsv++;
1067
1068         if (xmtfs & ~MACE_XMTFS_XMTSV) {
1069           if (xmtfs & MACE_XMTFS_UFLO) {
1070             /* Underflow.  Indicates that the Transmit FIFO emptied before
1071                the end of frame was reached. */
1072             lp->mace_stats.uflo++;
1073           }
1074           if (xmtfs & MACE_XMTFS_LCOL) {
1075             /* Late Collision */
1076             lp->mace_stats.lcol++;
1077           }
1078           if (xmtfs & MACE_XMTFS_MORE) {
1079             /* MORE than one retry was needed */
1080             lp->mace_stats.more++;
1081           }
1082           if (xmtfs & MACE_XMTFS_ONE) {
1083             /* Exactly ONE retry occurred */
1084             lp->mace_stats.one++;
1085           }
1086           if (xmtfs & MACE_XMTFS_DEFER) {
1087             /* Transmission was defered */
1088             lp->mace_stats.defer++;
1089           }
1090           if (xmtfs & MACE_XMTFS_LCAR) {
1091             /* Loss of carrier */
1092             lp->mace_stats.lcar++;
1093           }
1094           if (xmtfs & MACE_XMTFS_RTRY) {
1095             /* Retry error: transmit aborted after 16 attempts */
1096             lp->mace_stats.rtry++;
1097           }
1098         } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1099
1100       } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1101
1102       lp->linux_stats.tx_packets++;
1103       lp->tx_free_frames++;
1104       netif_wake_queue(dev);
1105     } /* if (status & MACE_IR_XMTINT) */
1106
1107     if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1108       if (status & MACE_IR_JAB) {
1109         /* Jabber Error.  Excessive transmit duration (20-150ms). */
1110         lp->mace_stats.jab++;
1111       }
1112       if (status & MACE_IR_BABL) {
1113         /* Babble Error.  >1518 bytes transmitted. */
1114         lp->mace_stats.babl++;
1115       }
1116       if (status & MACE_IR_CERR) {
1117         /* Collision Error.  CERR indicates the absence of the
1118            Signal Quality Error Test message after a packet
1119            transmission. */
1120         lp->mace_stats.cerr++;
1121       }
1122       if (status & MACE_IR_RCVCCO) {
1123         /* Receive Collision Count Overflow; */
1124         lp->mace_stats.rcvcco++;
1125       }
1126       if (status & MACE_IR_RNTPCO) {
1127         /* Runt Packet Count Overflow */
1128         lp->mace_stats.rntpco++;
1129       }
1130       if (status & MACE_IR_MPCO) {
1131         /* Missed Packet Count Overflow */
1132         lp->mace_stats.mpco++;
1133       }
1134     } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1135
1136   } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1137
1138   return IRQ_HANDLED;
1139 } /* mace_interrupt */
1140
1141 /* ----------------------------------------------------------------------------
1142 mace_rx
1143         Receives packets.
1144 ---------------------------------------------------------------------------- */
1145 static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1146 {
1147   mace_private *lp = netdev_priv(dev);
1148   unsigned int ioaddr = dev->base_addr;
1149   unsigned char rx_framecnt;
1150   unsigned short rx_status;
1151
1152   while (
1153     ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1154     (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1155     (RxCnt--)
1156   ) {
1157     rx_status = inw(ioaddr + AM2150_RCV);
1158
1159     DEBUG(3, "%s: in mace_rx(), framecnt 0x%X, rx_status"
1160           " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1161
1162     if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1163       lp->linux_stats.rx_errors++;
1164       if (rx_status & MACE_RCVFS_OFLO) {
1165         lp->mace_stats.oflo++;
1166       }
1167       if (rx_status & MACE_RCVFS_CLSN) {
1168         lp->mace_stats.clsn++;
1169       }
1170       if (rx_status & MACE_RCVFS_FRAM) {
1171         lp->mace_stats.fram++;
1172       }
1173       if (rx_status & MACE_RCVFS_FCS) {
1174         lp->mace_stats.fcs++;
1175       }
1176     } else {
1177       short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1178         /* Auto Strip is off, always subtract 4 */
1179       struct sk_buff *skb;
1180
1181       lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1182         /* runt packet count */
1183       lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1184         /* rcv collision count */
1185
1186       DEBUG(3, "    receiving packet size 0x%X rx_status"
1187             " 0x%X.\n", pkt_len, rx_status);
1188
1189       skb = dev_alloc_skb(pkt_len+2);
1190
1191       if (skb != NULL) {
1192         skb_reserve(skb, 2);
1193         insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1194         if (pkt_len & 1)
1195             *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1196         skb->protocol = eth_type_trans(skb, dev);
1197
1198         netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1199
1200         lp->linux_stats.rx_packets++;
1201         lp->linux_stats.rx_bytes += pkt_len;
1202         outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1203         continue;
1204       } else {
1205         DEBUG(1, "%s: couldn't allocate a sk_buff of size"
1206               " %d.\n", dev->name, pkt_len);
1207         lp->linux_stats.rx_dropped++;
1208       }
1209     }
1210     outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1211   } /* while */
1212
1213   return 0;
1214 } /* mace_rx */
1215
1216 /* ----------------------------------------------------------------------------
1217 pr_linux_stats
1218 ---------------------------------------------------------------------------- */
1219 static void pr_linux_stats(struct net_device_stats *pstats)
1220 {
1221   DEBUG(2, "pr_linux_stats\n");
1222   DEBUG(2, " rx_packets=%-7ld        tx_packets=%ld\n",
1223         (long)pstats->rx_packets, (long)pstats->tx_packets);
1224   DEBUG(2, " rx_errors=%-7ld         tx_errors=%ld\n",
1225         (long)pstats->rx_errors, (long)pstats->tx_errors);
1226   DEBUG(2, " rx_dropped=%-7ld        tx_dropped=%ld\n",
1227         (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1228   DEBUG(2, " multicast=%-7ld         collisions=%ld\n",
1229         (long)pstats->multicast, (long)pstats->collisions);
1230
1231   DEBUG(2, " rx_length_errors=%-7ld  rx_over_errors=%ld\n",
1232         (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1233   DEBUG(2, " rx_crc_errors=%-7ld     rx_frame_errors=%ld\n",
1234         (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1235   DEBUG(2, " rx_fifo_errors=%-7ld    rx_missed_errors=%ld\n",
1236         (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1237
1238   DEBUG(2, " tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1239         (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1240   DEBUG(2, " tx_fifo_errors=%-7ld    tx_heartbeat_errors=%ld\n",
1241         (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1242   DEBUG(2, " tx_window_errors=%ld\n",
1243         (long)pstats->tx_window_errors);
1244 } /* pr_linux_stats */
1245
1246 /* ----------------------------------------------------------------------------
1247 pr_mace_stats
1248 ---------------------------------------------------------------------------- */
1249 static void pr_mace_stats(mace_statistics *pstats)
1250 {
1251   DEBUG(2, "pr_mace_stats\n");
1252
1253   DEBUG(2, " xmtsv=%-7d             uflo=%d\n",
1254         pstats->xmtsv, pstats->uflo);
1255   DEBUG(2, " lcol=%-7d              more=%d\n",
1256         pstats->lcol, pstats->more);
1257   DEBUG(2, " one=%-7d               defer=%d\n",
1258         pstats->one, pstats->defer);
1259   DEBUG(2, " lcar=%-7d              rtry=%d\n",
1260         pstats->lcar, pstats->rtry);
1261
1262   /* MACE_XMTRC */
1263   DEBUG(2, " exdef=%-7d             xmtrc=%d\n",
1264         pstats->exdef, pstats->xmtrc);
1265
1266   /* RFS1--Receive Status (RCVSTS) */
1267   DEBUG(2, " oflo=%-7d              clsn=%d\n",
1268         pstats->oflo, pstats->clsn);
1269   DEBUG(2, " fram=%-7d              fcs=%d\n",
1270         pstats->fram, pstats->fcs);
1271
1272   /* RFS2--Runt Packet Count (RNTPC) */
1273   /* RFS3--Receive Collision Count (RCVCC) */
1274   DEBUG(2, " rfs_rntpc=%-7d         rfs_rcvcc=%d\n",
1275         pstats->rfs_rntpc, pstats->rfs_rcvcc);
1276
1277   /* MACE_IR */
1278   DEBUG(2, " jab=%-7d               babl=%d\n",
1279         pstats->jab, pstats->babl);
1280   DEBUG(2, " cerr=%-7d              rcvcco=%d\n",
1281         pstats->cerr, pstats->rcvcco);
1282   DEBUG(2, " rntpco=%-7d            mpco=%d\n",
1283         pstats->rntpco, pstats->mpco);
1284
1285   /* MACE_MPC */
1286   DEBUG(2, " mpc=%d\n", pstats->mpc);
1287
1288   /* MACE_RNTPC */
1289   DEBUG(2, " rntpc=%d\n", pstats->rntpc);
1290
1291   /* MACE_RCVCC */
1292   DEBUG(2, " rcvcc=%d\n", pstats->rcvcc);
1293
1294 } /* pr_mace_stats */
1295
1296 /* ----------------------------------------------------------------------------
1297 update_stats
1298         Update statistics.  We change to register window 1, so this
1299         should be run single-threaded if the device is active. This is
1300         expected to be a rare operation, and it's simpler for the rest
1301         of the driver to assume that window 0 is always valid rather
1302         than use a special window-state variable.
1303
1304         oflo & uflo should _never_ occur since it would mean the Xilinx
1305         was not able to transfer data between the MACE FIFO and the
1306         card's SRAM fast enough.  If this happens, something is
1307         seriously wrong with the hardware.
1308 ---------------------------------------------------------------------------- */
1309 static void update_stats(unsigned int ioaddr, struct net_device *dev)
1310 {
1311   mace_private *lp = netdev_priv(dev);
1312
1313   lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1314   lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1315   lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1316   /* At this point, mace_stats is fully updated for this call.
1317      We may now update the linux_stats. */
1318
1319   /* The MACE has no equivalent for linux_stats field which are commented
1320      out. */
1321
1322   /* lp->linux_stats.multicast; */
1323   lp->linux_stats.collisions =
1324     lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1325     /* Collision: The MACE may retry sending a packet 15 times
1326        before giving up.  The retry count is in XMTRC.
1327        Does each retry constitute a collision?
1328        If so, why doesn't the RCVCC record these collisions? */
1329
1330   /* detailed rx_errors: */
1331   lp->linux_stats.rx_length_errors =
1332     lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1333   /* lp->linux_stats.rx_over_errors */
1334   lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1335   lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1336   lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1337   lp->linux_stats.rx_missed_errors =
1338     lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1339
1340   /* detailed tx_errors */
1341   lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1342   lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1343     /* LCAR usually results from bad cabling. */
1344   lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1345   lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1346   /* lp->linux_stats.tx_window_errors; */
1347
1348   return;
1349 } /* update_stats */
1350
1351 /* ----------------------------------------------------------------------------
1352 mace_get_stats
1353         Gathers ethernet statistics from the MACE chip.
1354 ---------------------------------------------------------------------------- */
1355 static struct net_device_stats *mace_get_stats(struct net_device *dev)
1356 {
1357   mace_private *lp = netdev_priv(dev);
1358
1359   update_stats(dev->base_addr, dev);
1360
1361   DEBUG(1, "%s: updating the statistics.\n", dev->name);
1362   pr_linux_stats(&lp->linux_stats);
1363   pr_mace_stats(&lp->mace_stats);
1364
1365   return &lp->linux_stats;
1366 } /* net_device_stats */
1367
1368 /* ----------------------------------------------------------------------------
1369 updateCRC
1370         Modified from Am79C90 data sheet.
1371 ---------------------------------------------------------------------------- */
1372
1373 #ifdef BROKEN_MULTICAST
1374
1375 static void updateCRC(int *CRC, int bit)
1376 {
1377   int poly[]={
1378     1,1,1,0, 1,1,0,1,
1379     1,0,1,1, 1,0,0,0,
1380     1,0,0,0, 0,0,1,1,
1381     0,0,1,0, 0,0,0,0
1382   }; /* CRC polynomial.  poly[n] = coefficient of the x**n term of the
1383         CRC generator polynomial. */
1384
1385   int j;
1386
1387   /* shift CRC and control bit (CRC[32]) */
1388   for (j = 32; j > 0; j--)
1389     CRC[j] = CRC[j-1];
1390   CRC[0] = 0;
1391
1392   /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1393   if (bit ^ CRC[32])
1394     for (j = 0; j < 32; j++)
1395       CRC[j] ^= poly[j];
1396 } /* updateCRC */
1397
1398 /* ----------------------------------------------------------------------------
1399 BuildLAF
1400         Build logical address filter.
1401         Modified from Am79C90 data sheet.
1402
1403 Input
1404         ladrf: logical address filter (contents initialized to 0)
1405         adr: ethernet address
1406 ---------------------------------------------------------------------------- */
1407 static void BuildLAF(int *ladrf, int *adr)
1408 {
1409   int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1410
1411   int i, byte; /* temporary array indices */
1412   int hashcode; /* the output object */
1413
1414   CRC[32]=0;
1415
1416   for (byte = 0; byte < 6; byte++)
1417     for (i = 0; i < 8; i++)
1418       updateCRC(CRC, (adr[byte] >> i) & 1);
1419
1420   hashcode = 0;
1421   for (i = 0; i < 6; i++)
1422     hashcode = (hashcode << 1) + CRC[i];
1423
1424   byte = hashcode >> 3;
1425   ladrf[byte] |= (1 << (hashcode & 7));
1426
1427 #ifdef PCMCIA_DEBUG
1428   if (pc_debug > 2)
1429     printk(KERN_DEBUG "    adr =%pM\n", adr);
1430   printk(KERN_DEBUG "    hashcode = %d(decimal), ladrf[0:63] =", hashcode);
1431   for (i = 0; i < 8; i++)
1432     printk(KERN_CONT " %02X", ladrf[i]);
1433   printk(KERN_CONT "\n");
1434   }
1435 #endif
1436 } /* BuildLAF */
1437
1438 /* ----------------------------------------------------------------------------
1439 restore_multicast_list
1440         Restores the multicast filter for MACE chip to the last
1441         set_multicast_list() call.
1442
1443 Input
1444         multicast_num_addrs
1445         multicast_ladrf[]
1446 ---------------------------------------------------------------------------- */
1447 static void restore_multicast_list(struct net_device *dev)
1448 {
1449   mace_private *lp = netdev_priv(dev);
1450   int num_addrs = lp->multicast_num_addrs;
1451   int *ladrf = lp->multicast_ladrf;
1452   unsigned int ioaddr = dev->base_addr;
1453   int i;
1454
1455   DEBUG(2, "%s: restoring Rx mode to %d addresses.\n",
1456         dev->name, num_addrs);
1457
1458   if (num_addrs > 0) {
1459
1460     DEBUG(1, "Attempt to restore multicast list detected.\n");
1461
1462     mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1463     /* Poll ADDRCHG bit */
1464     while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1465       ;
1466     /* Set LADRF register */
1467     for (i = 0; i < MACE_LADRF_LEN; i++)
1468       mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1469
1470     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1471     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1472
1473   } else if (num_addrs < 0) {
1474
1475     /* Promiscuous mode: receive all packets */
1476     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1477     mace_write(lp, ioaddr, MACE_MACCC,
1478       MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1479     );
1480
1481   } else {
1482
1483     /* Normal mode */
1484     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1485     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1486
1487   }
1488 } /* restore_multicast_list */
1489
1490 /* ----------------------------------------------------------------------------
1491 set_multicast_list
1492         Set or clear the multicast filter for this adaptor.
1493
1494 Input
1495         num_addrs == -1 Promiscuous mode, receive all packets
1496         num_addrs == 0  Normal mode, clear multicast list
1497         num_addrs > 0   Multicast mode, receive normal and MC packets, and do
1498                         best-effort filtering.
1499 Output
1500         multicast_num_addrs
1501         multicast_ladrf[]
1502 ---------------------------------------------------------------------------- */
1503
1504 static void set_multicast_list(struct net_device *dev)
1505 {
1506   mace_private *lp = netdev_priv(dev);
1507   int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
1508   int i;
1509   struct dev_mc_list *dmi = dev->mc_list;
1510
1511 #ifdef PCMCIA_DEBUG
1512   if (pc_debug > 1) {
1513     static int old;
1514     if (dev->mc_count != old) {
1515       old = dev->mc_count;
1516       DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1517             dev->name, old);
1518     }
1519   }
1520 #endif
1521
1522   /* Set multicast_num_addrs. */
1523   lp->multicast_num_addrs = dev->mc_count;
1524
1525   /* Set multicast_ladrf. */
1526   if (num_addrs > 0) {
1527     /* Calculate multicast logical address filter */
1528     memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1529     for (i = 0; i < dev->mc_count; i++) {
1530       memcpy(adr, dmi->dmi_addr, ETHER_ADDR_LEN);
1531       dmi = dmi->next;
1532       BuildLAF(lp->multicast_ladrf, adr);
1533     }
1534   }
1535
1536   restore_multicast_list(dev);
1537
1538 } /* set_multicast_list */
1539
1540 #endif /* BROKEN_MULTICAST */
1541
1542 static void restore_multicast_list(struct net_device *dev)
1543 {
1544   unsigned int ioaddr = dev->base_addr;
1545   mace_private *lp = netdev_priv(dev);
1546
1547   DEBUG(2, "%s: restoring Rx mode to %d addresses.\n", dev->name,
1548         lp->multicast_num_addrs);
1549
1550   if (dev->flags & IFF_PROMISC) {
1551     /* Promiscuous mode: receive all packets */
1552     mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1553     mace_write(lp, ioaddr, MACE_MACCC,
1554       MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1555     );
1556   } else {
1557     /* Normal mode */
1558     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1559     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1560   }
1561 } /* restore_multicast_list */
1562
1563 static void set_multicast_list(struct net_device *dev)
1564 {
1565   mace_private *lp = netdev_priv(dev);
1566
1567 #ifdef PCMCIA_DEBUG
1568   if (pc_debug > 1) {
1569     static int old;
1570     if (dev->mc_count != old) {
1571       old = dev->mc_count;
1572       DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1573             dev->name, old);
1574     }
1575   }
1576 #endif
1577
1578   lp->multicast_num_addrs = dev->mc_count;
1579   restore_multicast_list(dev);
1580
1581 } /* set_multicast_list */
1582
1583 static struct pcmcia_device_id nmclan_ids[] = {
1584         PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
1585         PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
1586         PCMCIA_DEVICE_NULL,
1587 };
1588 MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1589
1590 static struct pcmcia_driver nmclan_cs_driver = {
1591         .owner          = THIS_MODULE,
1592         .drv            = {
1593                 .name   = "nmclan_cs",
1594         },
1595         .probe          = nmclan_probe,
1596         .remove         = nmclan_detach,
1597         .id_table       = nmclan_ids,
1598         .suspend        = nmclan_suspend,
1599         .resume         = nmclan_resume,
1600 };
1601
1602 static int __init init_nmclan_cs(void)
1603 {
1604         return pcmcia_register_driver(&nmclan_cs_driver);
1605 }
1606
1607 static void __exit exit_nmclan_cs(void)
1608 {
1609         pcmcia_unregister_driver(&nmclan_cs_driver);
1610 }
1611
1612 module_init(init_nmclan_cs);
1613 module_exit(exit_nmclan_cs);