drivers/i2c/busses/i2c-uniphier-f.c

   1 /*
   2  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/i2c.h>
  17 #include <linux/iopoll.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22
  23 #define UNIPHIER_FI2C_CR        0x00    /* control register */
  24 #define     UNIPHIER_FI2C_CR_MST        BIT(3)  /* master mode */
  25 #define     UNIPHIER_FI2C_CR_STA        BIT(2)  /* start condition */
  26 #define     UNIPHIER_FI2C_CR_STO        BIT(1)  /* stop condition */
  27 #define     UNIPHIER_FI2C_CR_NACK       BIT(0)  /* do not return ACK */
  28 #define UNIPHIER_FI2C_DTTX      0x04    /* TX FIFO */
  29 #define     UNIPHIER_FI2C_DTTX_CMD      BIT(8)  /* send command (slave addr) */
  30 #define     UNIPHIER_FI2C_DTTX_RD       BIT(0)  /* read transaction */
  31 #define UNIPHIER_FI2C_DTRX      0x04    /* RX FIFO */
  32 #define UNIPHIER_FI2C_SLAD      0x0c    /* slave address */
  33 #define UNIPHIER_FI2C_CYC       0x10    /* clock cycle control */
  34 #define UNIPHIER_FI2C_LCTL      0x14    /* clock low period control */
  35 #define UNIPHIER_FI2C_SSUT      0x18    /* restart/stop setup time control */
  36 #define UNIPHIER_FI2C_DSUT      0x1c    /* data setup time control */
  37 #define UNIPHIER_FI2C_INT       0x20    /* interrupt status */
  38 #define UNIPHIER_FI2C_IE        0x24    /* interrupt enable */
  39 #define UNIPHIER_FI2C_IC        0x28    /* interrupt clear */
  40 #define     UNIPHIER_FI2C_INT_TE        BIT(9)  /* TX FIFO empty */
  41 #define     UNIPHIER_FI2C_INT_RF        BIT(8)  /* RX FIFO full */
  42 #define     UNIPHIER_FI2C_INT_TC        BIT(7)  /* send complete (STOP) */
  43 #define     UNIPHIER_FI2C_INT_RC        BIT(6)  /* receive complete (STOP) */
  44 #define     UNIPHIER_FI2C_INT_TB        BIT(5)  /* sent specified bytes */
  45 #define     UNIPHIER_FI2C_INT_RB        BIT(4)  /* received specified bytes */
  46 #define     UNIPHIER_FI2C_INT_NA        BIT(2)  /* no ACK */
  47 #define     UNIPHIER_FI2C_INT_AL        BIT(1)  /* arbitration lost */
  48 #define UNIPHIER_FI2C_SR        0x2c    /* status register */
  49 #define     UNIPHIER_FI2C_SR_DB         BIT(12) /* device busy */
  50 #define     UNIPHIER_FI2C_SR_STS        BIT(11) /* stop condition detected */
  51 #define     UNIPHIER_FI2C_SR_BB         BIT(8)  /* bus busy */
  52 #define     UNIPHIER_FI2C_SR_RFF        BIT(3)  /* RX FIFO full */
  53 #define     UNIPHIER_FI2C_SR_RNE        BIT(2)  /* RX FIFO not empty */
  54 #define     UNIPHIER_FI2C_SR_TNF        BIT(1)  /* TX FIFO not full */
  55 #define     UNIPHIER_FI2C_SR_TFE        BIT(0)  /* TX FIFO empty */
  56 #define UNIPHIER_FI2C_RST       0x34    /* reset control */
  57 #define     UNIPHIER_FI2C_RST_TBRST     BIT(2)  /* clear TX FIFO */
  58 #define     UNIPHIER_FI2C_RST_RBRST     BIT(1)  /* clear RX FIFO */
  59 #define     UNIPHIER_FI2C_RST_RST       BIT(0)  /* forcible bus reset */
  60 #define UNIPHIER_FI2C_BM        0x38    /* bus monitor */
  61 #define     UNIPHIER_FI2C_BM_SDAO       BIT(3)  /* output for SDA line */
  62 #define     UNIPHIER_FI2C_BM_SDAS       BIT(2)  /* readback of SDA line */
  63 #define     UNIPHIER_FI2C_BM_SCLO       BIT(1)  /* output for SCL line */
  64 #define     UNIPHIER_FI2C_BM_SCLS       BIT(0)  /* readback of SCL line */
  65 #define UNIPHIER_FI2C_NOISE     0x3c    /* noise filter control */
  66 #define UNIPHIER_FI2C_TBC       0x40    /* TX byte count setting */
  67 #define UNIPHIER_FI2C_RBC       0x44    /* RX byte count setting */
  68 #define UNIPHIER_FI2C_TBCM      0x48    /* TX byte count monitor */
  69 #define UNIPHIER_FI2C_RBCM      0x4c    /* RX byte count monitor */
  70 #define UNIPHIER_FI2C_BRST      0x50    /* bus reset */
  71 #define     UNIPHIER_FI2C_BRST_FOEN     BIT(1)  /* normal operation */
  72 #define     UNIPHIER_FI2C_BRST_RSCL     BIT(0)  /* release SCL */
  73
  74 #define UNIPHIER_FI2C_INT_FAULTS        \
  75                                 (UNIPHIER_FI2C_INT_NA | UNIPHIER_FI2C_INT_AL)
  76 #define UNIPHIER_FI2C_INT_STOP          \
  77                                 (UNIPHIER_FI2C_INT_TC | UNIPHIER_FI2C_INT_RC)
  78
  79 #define UNIPHIER_FI2C_RD                BIT(0)
  80 #define UNIPHIER_FI2C_STOP              BIT(1)
  81 #define UNIPHIER_FI2C_MANUAL_NACK       BIT(2)
  82 #define UNIPHIER_FI2C_BYTE_WISE         BIT(3)
  83 #define UNIPHIER_FI2C_DEFER_STOP_COMP   BIT(4)
  84
  85 #define UNIPHIER_FI2C_DEFAULT_SPEED     100000
  86 #define UNIPHIER_FI2C_MAX_SPEED         400000
  87 #define UNIPHIER_FI2C_FIFO_SIZE         8
  88
  89 struct uniphier_fi2c_priv {
  90         struct completion comp;
  91         struct i2c_adapter adap;
  92         void __iomem *membase;
  93         struct clk *clk;
  94         unsigned int len;
  95         u8 *buf;
  96         u32 enabled_irqs;
  97         int error;
  98         unsigned int flags;
  99         unsigned int busy_cnt;
 100 };
 101
 102 static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv,
 103                                       bool first)
 104 {
 105         int fifo_space = UNIPHIER_FI2C_FIFO_SIZE;
 106
 107         /*
 108          * TX-FIFO stores slave address in it for the first access.
 109          * Decrement the counter.
 110          */
 111         if (first)
 112                 fifo_space--;
 113
 114         while (priv->len) {
 115                 if (fifo_space-- <= 0)
 116                         break;
 117
 118                 dev_dbg(&priv->adap.dev, "write data: %02x\n", *priv->buf);
 119                 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX);
 120                 priv->len--;
 121         }
 122 }
 123
 124 static void uniphier_fi2c_drain_rxfifo(struct uniphier_fi2c_priv *priv)
 125 {
 126         int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ?
 127                                                 1 : UNIPHIER_FI2C_FIFO_SIZE;
 128
 129         while (priv->len) {
 130                 if (fifo_left-- <= 0)
 131                         break;
 132
 133                 *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX);
 134                 dev_dbg(&priv->adap.dev, "read data: %02x\n", priv->buf[-1]);
 135                 priv->len--;
 136         }
 137 }
 138
 139 static void uniphier_fi2c_set_irqs(struct uniphier_fi2c_priv *priv)
 140 {
 141         writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE);
 142 }
 143
 144 static void uniphier_fi2c_clear_irqs(struct uniphier_fi2c_priv *priv)
 145 {
 146         writel(-1, priv->membase + UNIPHIER_FI2C_IC);
 147 }
 148
 149 static void uniphier_fi2c_stop(struct uniphier_fi2c_priv *priv)
 150 {
 151         dev_dbg(&priv->adap.dev, "stop condition\n");
 152
 153         priv->enabled_irqs |= UNIPHIER_FI2C_INT_STOP;
 154         uniphier_fi2c_set_irqs(priv);
 155         writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STO,
 156                priv->membase + UNIPHIER_FI2C_CR);
 157 }
 158
 159 static irqreturn_t uniphier_fi2c_interrupt(int irq, void *dev_id)
 160 {
 161         struct uniphier_fi2c_priv *priv = dev_id;
 162         u32 irq_status;
 163
 164         irq_status = readl(priv->membase + UNIPHIER_FI2C_INT);
 165
 166         dev_dbg(&priv->adap.dev,
 167                 "interrupt: enabled_irqs=%04x, irq_status=%04x\n",
 168                 priv->enabled_irqs, irq_status);
 169
 170         if (irq_status & UNIPHIER_FI2C_INT_STOP)
 171                 goto complete;
 172
 173         if (unlikely(irq_status & UNIPHIER_FI2C_INT_AL)) {
 174                 dev_dbg(&priv->adap.dev, "arbitration lost\n");
 175                 priv->error = -EAGAIN;
 176                 goto complete;
 177         }
 178
 179         if (unlikely(irq_status & UNIPHIER_FI2C_INT_NA)) {
 180                 dev_dbg(&priv->adap.dev, "could not get ACK\n");
 181                 priv->error = -ENXIO;
 182                 if (priv->flags & UNIPHIER_FI2C_RD) {
 183                         /*
 184                          * work around a hardware bug:
 185                          * The receive-completed interrupt is never set even if
 186                          * STOP condition is detected after the address phase
 187                          * of read transaction fails to get ACK.
 188                          * To avoid time-out error, we issue STOP here,
 189                          * but do not wait for its completion.
 190                          * It should be checked after exiting this handler.
 191                          */
 192                         uniphier_fi2c_stop(priv);
 193                         priv->flags |= UNIPHIER_FI2C_DEFER_STOP_COMP;
 194                         goto complete;
 195                 }
 196                 goto stop;
 197         }
 198
 199         if (irq_status & UNIPHIER_FI2C_INT_TE) {
 200                 if (!priv->len)
 201                         goto data_done;
 202
 203                 uniphier_fi2c_fill_txfifo(priv, false);
 204                 goto handled;
 205         }
 206
 207         if (irq_status & (UNIPHIER_FI2C_INT_RF | UNIPHIER_FI2C_INT_RB)) {
 208                 uniphier_fi2c_drain_rxfifo(priv);
 209                 if (!priv->len)
 210                         goto data_done;
 211
 212                 if (unlikely(priv->flags & UNIPHIER_FI2C_MANUAL_NACK)) {
 213                         if (priv->len <= UNIPHIER_FI2C_FIFO_SIZE &&
 214                             !(priv->flags & UNIPHIER_FI2C_BYTE_WISE)) {
 215                                 dev_dbg(&priv->adap.dev,
 216                                         "enable read byte count IRQ\n");
 217                                 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RB;
 218                                 uniphier_fi2c_set_irqs(priv);
 219                                 priv->flags |= UNIPHIER_FI2C_BYTE_WISE;
 220                         }
 221                         if (priv->len <= 1) {
 222                                 dev_dbg(&priv->adap.dev, "set NACK\n");
 223                                 writel(UNIPHIER_FI2C_CR_MST |
 224                                        UNIPHIER_FI2C_CR_NACK,
 225                                        priv->membase + UNIPHIER_FI2C_CR);
 226                         }
 227                 }
 228
 229                 goto handled;
 230         }
 231
 232         return IRQ_NONE;
 233
 234 data_done:
 235         if (priv->flags & UNIPHIER_FI2C_STOP) {
 236 stop:
 237                 uniphier_fi2c_stop(priv);
 238         } else {
 239 complete:
 240                 priv->enabled_irqs = 0;
 241                 uniphier_fi2c_set_irqs(priv);
 242                 complete(&priv->comp);
 243         }
 244
 245 handled:
 246         uniphier_fi2c_clear_irqs(priv);
 247
 248         return IRQ_HANDLED;
 249 }
 250
 251 static void uniphier_fi2c_tx_init(struct uniphier_fi2c_priv *priv, u16 addr)
 252 {
 253         priv->enabled_irqs |= UNIPHIER_FI2C_INT_TE;
 254         /* do not use TX byte counter */
 255         writel(0, priv->membase + UNIPHIER_FI2C_TBC);
 256         /* set slave address */
 257         writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1,
 258                priv->membase + UNIPHIER_FI2C_DTTX);
 259         /* first chunk of data */
 260         uniphier_fi2c_fill_txfifo(priv, true);
 261 }
 262
 263 static void uniphier_fi2c_rx_init(struct uniphier_fi2c_priv *priv, u16 addr)
 264 {
 265         priv->flags |= UNIPHIER_FI2C_RD;
 266
 267         if (likely(priv->len < 256)) {
 268                 /*
 269                  * If possible, use RX byte counter.
 270                  * It can automatically handle NACK for the last byte.
 271                  */
 272                 writel(priv->len, priv->membase + UNIPHIER_FI2C_RBC);
 273                 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF |
 274                                       UNIPHIER_FI2C_INT_RB;
 275         } else {
 276                 /*
 277                  * The byte counter can not count over 256.  In this case,
 278                  * do not use it at all.  Drain data when FIFO gets full,
 279                  * but treat the last portion as a special case.
 280                  */
 281                 writel(0, priv->membase + UNIPHIER_FI2C_RBC);
 282                 priv->flags |= UNIPHIER_FI2C_MANUAL_NACK;
 283                 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF;
 284         }
 285
 286         /* set slave address with RD bit */
 287         writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1,
 288                priv->membase + UNIPHIER_FI2C_DTTX);
 289 }
 290
 291 static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv)
 292 {
 293         writel(UNIPHIER_FI2C_RST_RST, priv->membase + UNIPHIER_FI2C_RST);
 294 }
 295
 296 static void uniphier_fi2c_prepare_operation(struct uniphier_fi2c_priv *priv)
 297 {
 298         writel(UNIPHIER_FI2C_BRST_FOEN | UNIPHIER_FI2C_BRST_RSCL,
 299                priv->membase + UNIPHIER_FI2C_BRST);
 300 }
 301
 302 static void uniphier_fi2c_recover(struct uniphier_fi2c_priv *priv)
 303 {
 304         uniphier_fi2c_reset(priv);
 305         i2c_recover_bus(&priv->adap);
 306 }
 307
 308 static int uniphier_fi2c_master_xfer_one(struct i2c_adapter *adap,
 309                                          struct i2c_msg *msg, bool stop)
 310 {
 311         struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
 312         bool is_read = msg->flags & I2C_M_RD;
 313         unsigned long time_left;
 314
 315         dev_dbg(&adap->dev, "%s: addr=0x%02x, len=%d, stop=%d\n",
 316                 is_read ? "receive" : "transmit", msg->addr, msg->len, stop);
 317
 318         priv->len = msg->len;
 319         priv->buf = msg->buf;
 320         priv->enabled_irqs = UNIPHIER_FI2C_INT_FAULTS;
 321         priv->error = 0;
 322         priv->flags = 0;
 323
 324         if (stop)
 325                 priv->flags |= UNIPHIER_FI2C_STOP;
 326
 327         reinit_completion(&priv->comp);
 328         uniphier_fi2c_clear_irqs(priv);
 329         writel(UNIPHIER_FI2C_RST_TBRST | UNIPHIER_FI2C_RST_RBRST,
 330                priv->membase + UNIPHIER_FI2C_RST);      /* reset TX/RX FIFO */
 331
 332         if (is_read)
 333                 uniphier_fi2c_rx_init(priv, msg->addr);
 334         else
 335                 uniphier_fi2c_tx_init(priv, msg->addr);
 336
 337         uniphier_fi2c_set_irqs(priv);
 338
 339         dev_dbg(&adap->dev, "start condition\n");
 340         writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STA,
 341                priv->membase + UNIPHIER_FI2C_CR);
 342
 343         time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);
 344         if (!time_left) {
 345                 dev_err(&adap->dev, "transaction timeout.\n");
 346                 uniphier_fi2c_recover(priv);
 347                 return -ETIMEDOUT;
 348         }
 349         dev_dbg(&adap->dev, "complete\n");
 350
 351         if (unlikely(priv->flags & UNIPHIER_FI2C_DEFER_STOP_COMP)) {
 352                 u32 status;
 353                 int ret;
 354
 355                 ret = readl_poll_timeout(priv->membase + UNIPHIER_FI2C_SR,
 356                                          status,
 357                                          (status & UNIPHIER_FI2C_SR_STS) &&
 358                                          !(status & UNIPHIER_FI2C_SR_BB),
 359                                          1, 20);
 360                 if (ret) {
 361                         dev_err(&adap->dev,
 362                                 "stop condition was not completed.\n");
 363                         uniphier_fi2c_recover(priv);
 364                         return ret;
 365                 }
 366         }
 367
 368         return priv->error;
 369 }
 370
 371 static int uniphier_fi2c_check_bus_busy(struct i2c_adapter *adap)
 372 {
 373         struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
 374
 375         if (readl(priv->membase + UNIPHIER_FI2C_SR) & UNIPHIER_FI2C_SR_DB) {
 376                 if (priv->busy_cnt++ > 3) {
 377                         /*
 378                          * If bus busy continues too long, it is probably
 379                          * in a wrong state.  Try bus recovery.
 380                          */
 381                         uniphier_fi2c_recover(priv);
 382                         priv->busy_cnt = 0;
 383                 }
 384
 385                 return -EAGAIN;
 386         }
 387
 388         priv->busy_cnt = 0;
 389         return 0;
 390 }
 391
 392 static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap,
 393                                      struct i2c_msg *msgs, int num)
 394 {
 395         struct i2c_msg *msg, *emsg = msgs + num;
 396         int ret;
 397
 398         ret = uniphier_fi2c_check_bus_busy(adap);
 399         if (ret)
 400                 return ret;
 401
 402         for (msg = msgs; msg < emsg; msg++) {
 403                 /* If next message is read, skip the stop condition */
 404                 bool stop = !(msg + 1 < emsg && msg[1].flags & I2C_M_RD);
 405                 /* but, force it if I2C_M_STOP is set */
 406                 if (msg->flags & I2C_M_STOP)
 407                         stop = true;
 408
 409                 ret = uniphier_fi2c_master_xfer_one(adap, msg, stop);
 410                 if (ret)
 411                         return ret;
 412         }
 413
 414         return num;
 415 }
 416
 417 static u32 uniphier_fi2c_functionality(struct i2c_adapter *adap)
 418 {
 419         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 420 }
 421
 422 static const struct i2c_algorithm uniphier_fi2c_algo = {
 423         .master_xfer = uniphier_fi2c_master_xfer,
 424         .functionality = uniphier_fi2c_functionality,
 425 };
 426
 427 static int uniphier_fi2c_get_scl(struct i2c_adapter *adap)
 428 {
 429         struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
 430
 431         return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &
 432                                                         UNIPHIER_FI2C_BM_SCLS);
 433 }
 434
 435 static void uniphier_fi2c_set_scl(struct i2c_adapter *adap, int val)
 436 {
 437         struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
 438
 439         writel(val ? UNIPHIER_FI2C_BRST_RSCL : 0,
 440                priv->membase + UNIPHIER_FI2C_BRST);
 441 }
 442
 443 static int uniphier_fi2c_get_sda(struct i2c_adapter *adap)
 444 {
 445         struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
 446
 447         return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &
 448                                                         UNIPHIER_FI2C_BM_SDAS);
 449 }
 450
 451 static void uniphier_fi2c_unprepare_recovery(struct i2c_adapter *adap)
 452 {
 453         uniphier_fi2c_prepare_operation(i2c_get_adapdata(adap));
 454 }
 455
 456 static struct i2c_bus_recovery_info uniphier_fi2c_bus_recovery_info = {
 457         .recover_bus = i2c_generic_scl_recovery,
 458         .get_scl = uniphier_fi2c_get_scl,
 459         .set_scl = uniphier_fi2c_set_scl,
 460         .get_sda = uniphier_fi2c_get_sda,
 461         .unprepare_recovery = uniphier_fi2c_unprepare_recovery,
 462 };
 463
 464 static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv,
 465                                   u32 bus_speed, unsigned long clk_rate)
 466 {
 467         u32 tmp;
 468
 469         tmp = readl(priv->membase + UNIPHIER_FI2C_CR);
 470         tmp |= UNIPHIER_FI2C_CR_MST;
 471         writel(tmp, priv->membase + UNIPHIER_FI2C_CR);
 472
 473         uniphier_fi2c_reset(priv);
 474
 475         tmp = clk_rate / bus_speed;
 476
 477         writel(tmp, priv->membase + UNIPHIER_FI2C_CYC);
 478         writel(tmp / 2, priv->membase + UNIPHIER_FI2C_LCTL);
 479         writel(tmp / 2, priv->membase + UNIPHIER_FI2C_SSUT);
 480         writel(tmp / 16, priv->membase + UNIPHIER_FI2C_DSUT);
 481
 482         uniphier_fi2c_prepare_operation(priv);
 483 }
 484
 485 static int uniphier_fi2c_probe(struct platform_device *pdev)
 486 {
 487         struct device *dev = &pdev->dev;
 488         struct uniphier_fi2c_priv *priv;
 489         struct resource *regs;
 490         u32 bus_speed;
 491         unsigned long clk_rate;
 492         int irq, ret;
 493
 494         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 495         if (!priv)
 496                 return -ENOMEM;
 497
 498         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 499         priv->membase = devm_ioremap_resource(dev, regs);
 500         if (IS_ERR(priv->membase))
 501                 return PTR_ERR(priv->membase);
 502
 503         irq = platform_get_irq(pdev, 0);
 504         if (irq < 0) {
 505                 dev_err(dev, "failed to get IRQ number\n");
 506                 return irq;
 507         }
 508
 509         if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed))
 510                 bus_speed = UNIPHIER_FI2C_DEFAULT_SPEED;
 511
 512         if (!bus_speed || bus_speed > UNIPHIER_FI2C_MAX_SPEED) {
 513                 dev_err(dev, "invalid clock-frequency %d\n", bus_speed);
 514                 return -EINVAL;
 515         }
 516
 517         priv->clk = devm_clk_get(dev, NULL);
 518         if (IS_ERR(priv->clk)) {
 519                 dev_err(dev, "failed to get clock\n");
 520                 return PTR_ERR(priv->clk);
 521         }
 522
 523         ret = clk_prepare_enable(priv->clk);
 524         if (ret)
 525                 return ret;
 526
 527         clk_rate = clk_get_rate(priv->clk);
 528         if (!clk_rate) {
 529                 dev_err(dev, "input clock rate should not be zero\n");
 530                 ret = -EINVAL;
 531                 goto err;
 532         }
 533
 534         init_completion(&priv->comp);
 535         priv->adap.owner = THIS_MODULE;
 536         priv->adap.algo = &uniphier_fi2c_algo;
 537         priv->adap.dev.parent = dev;
 538         priv->adap.dev.of_node = dev->of_node;
 539         strlcpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name));
 540         priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info;
 541         i2c_set_adapdata(&priv->adap, priv);
 542         platform_set_drvdata(pdev, priv);
 543
 544         uniphier_fi2c_hw_init(priv, bus_speed, clk_rate);
 545
 546         ret = devm_request_irq(dev, irq, uniphier_fi2c_interrupt, 0,
 547                                pdev->name, priv);
 548         if (ret) {
 549                 dev_err(dev, "failed to request irq %d\n", irq);
 550                 goto err;
 551         }
 552
 553         ret = i2c_add_adapter(&priv->adap);
 554 err:
 555         if (ret)
 556                 clk_disable_unprepare(priv->clk);
 557
 558         return ret;
 559 }
 560
 561 static int uniphier_fi2c_remove(struct platform_device *pdev)
 562 {
 563         struct uniphier_fi2c_priv *priv = platform_get_drvdata(pdev);
 564
 565         i2c_del_adapter(&priv->adap);
 566         clk_disable_unprepare(priv->clk);
 567
 568         return 0;
 569 }
 570
 571 static const struct of_device_id uniphier_fi2c_match[] = {
 572         { .compatible = "socionext,uniphier-fi2c" },
 573         { /* sentinel */ }
 574 };
 575 MODULE_DEVICE_TABLE(of, uniphier_fi2c_match);
 576
 577 static struct platform_driver uniphier_fi2c_drv = {
 578         .probe  = uniphier_fi2c_probe,
 579         .remove = uniphier_fi2c_remove,
 580         .driver = {
 581                 .name  = "uniphier-fi2c",
 582                 .of_match_table = uniphier_fi2c_match,
 583         },
 584 };
 585 module_platform_driver(uniphier_fi2c_drv);
 586
 587 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
 588 MODULE_DESCRIPTION("UniPhier FIFO-builtin I2C bus driver");
 589 MODULE_LICENSE("GPL");