drivers/mcb/mcb-internal.h

   1 #ifndef __MCB_INTERNAL
   2 #define __MCB_INTERNAL
   3
   4 #include <linux/types.h>
   5
   6 #define PCI_VENDOR_ID_MEN               0x1a88
   7 #define PCI_DEVICE_ID_MEN_CHAMELEON     0x4d45
   8 #define CHAMELEONV2_MAGIC               0xabce
   9 #define CHAM_HEADER_SIZE                0x200
  10
  11 enum chameleon_descriptor_type {
  12         CHAMELEON_DTYPE_GENERAL = 0x0,
  13         CHAMELEON_DTYPE_BRIDGE = 0x1,
  14         CHAMELEON_DTYPE_CPU = 0x2,
  15         CHAMELEON_DTYPE_BAR = 0x3,
  16         CHAMELEON_DTYPE_END = 0xf,
  17 };
  18
  19 enum chameleon_bus_type {
  20         CHAMELEON_BUS_WISHBONE,
  21         CHAMELEON_BUS_AVALON,
  22         CHAMELEON_BUS_LPC,
  23         CHAMELEON_BUS_ISA,
  24 };
  25
  26 /**
  27  * struct chameleon_fpga_header
  28  *
  29  * @revision:   Revison of Chameleon table in FPGA
  30  * @model:      Chameleon table model ASCII char
  31  * @minor:      Revision minor
  32  * @bus_type:   Bus type (usually %CHAMELEON_BUS_WISHBONE)
  33  * @magic:      Chameleon header magic number (0xabce for version 2)
  34  * @reserved:   Reserved
  35  * @filename:   Filename of FPGA bitstream
  36  */
  37 struct chameleon_fpga_header {
  38         u8 revision;
  39         char model;
  40         u8 minor;
  41         u8 bus_type;
  42         u16 magic;
  43         u16 reserved;
  44         /* This one has no '\0' at the end!!! */
  45         char filename[CHAMELEON_FILENAME_LEN];
  46 } __packed;
  47 #define HEADER_MAGIC_OFFSET 0x4
  48
  49 /**
  50  * struct chameleon_gdd - Chameleon General Device Descriptor
  51  *
  52  * @irq:        the position in the FPGA's IRQ controller vector
  53  * @rev:        the revision of the variant's implementation
  54  * @var:        the variant of the IP core
  55  * @dev:        the device  the IP core is
  56  * @dtype:      device descriptor type
  57  * @bar:        BAR offset that must be added to module offset
  58  * @inst:       the instance number of the device, 0 is first instance
  59  * @group:      the group the device belongs to (0 = no group)
  60  * @reserved:   reserved
  61  * @offset:     beginning of the address window of desired module
  62  * @size:       size of the module's address window
  63  */
  64 struct chameleon_gdd {
  65         __le32 reg1;
  66         __le32 reg2;
  67         __le32 offset;
  68         __le32 size;
  69
  70 } __packed;
  71
  72 /* GDD Register 1 fields */
  73 #define GDD_IRQ(x) ((x) & 0x1f)
  74 #define GDD_REV(x) (((x) >> 5) & 0x3f)
  75 #define GDD_VAR(x) (((x) >> 11) & 0x3f)
  76 #define GDD_DEV(x) (((x) >> 18) & 0x3ff)
  77 #define GDD_DTY(x) (((x) >> 28) & 0xf)
  78
  79 /* GDD Register 2 fields */
  80 #define GDD_BAR(x) ((x) & 0x7)
  81 #define GDD_INS(x) (((x) >> 3) & 0x3f)
  82 #define GDD_GRP(x) (((x) >> 9) & 0x3f)
  83
  84 /**
  85  * struct chameleon_bdd - Chameleon Bridge Device Descriptor
  86  *
  87  * @irq:        the position in the FPGA's IRQ controller vector
  88  * @rev:        the revision of the variant's implementation
  89  * @var:        the variant of the IP core
  90  * @dev:        the device  the IP core is
  91  * @dtype:      device descriptor type
  92  * @bar:        BAR offset that must be added to module offset
  93  * @inst:       the instance number of the device, 0 is first instance
  94  * @dbar:       destination bar from the bus _behind_ the bridge
  95  * @chamoff:    offset within the BAR of the source bus
  96  * @offset:
  97  * @size:
  98  */
  99 struct chameleon_bdd {
 100         unsigned int irq:6;
 101         unsigned int rev:6;
 102         unsigned int var:6;
 103         unsigned int dev:10;
 104         unsigned int dtype:4;
 105         unsigned int bar:3;
 106         unsigned int inst:6;
 107         unsigned int dbar:3;
 108         unsigned int group:6;
 109         unsigned int reserved:14;
 110         u32 chamoff;
 111         u32 offset;
 112         u32 size;
 113 } __packed;
 114
 115 struct chameleon_bar {
 116         u32 addr;
 117         u32 size;
 118 };
 119
 120 #define BAR_CNT(x) ((x) & 0x07)
 121 #define CHAMELEON_BAR_MAX       6
 122 #define BAR_DESC_SIZE(x)        ((x) * sizeof(struct chameleon_bar) + sizeof(__le32))
 123
 124 int chameleon_parse_cells(struct mcb_bus *bus, phys_addr_t mapbase,
 125                           void __iomem *base);
 126
 127 #endif