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hwrng: core - Don't use a stack buffer in add_early_randomness()
[linux/fpc-iii.git] / drivers / media / pci / cx23885 / cx23885-cards.c
blob99ba8d6328f0f1b0baddd34936fe586593882bc4
1 /*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/delay.h>
22 #include <media/drv-intf/cx25840.h>
23 #include <linux/firmware.h>
24 #include <misc/altera.h>
25
26 #include "cx23885.h"
27 #include "tuner-xc2028.h"
28 #include "netup-eeprom.h"
29 #include "netup-init.h"
30 #include "altera-ci.h"
31 #include "xc4000.h"
32 #include "xc5000.h"
33 #include "cx23888-ir.h"
34
35 static unsigned int netup_card_rev = 4;
36 module_param(netup_card_rev, int, 0644);
37 MODULE_PARM_DESC(netup_card_rev,
38 "NetUP Dual DVB-T/C CI card revision");
39 static unsigned int enable_885_ir;
40 module_param(enable_885_ir, int, 0644);
41 MODULE_PARM_DESC(enable_885_ir,
42 "Enable integrated IR controller for supported\n"
43 "\t\t CX2388[57] boards that are wired for it:\n"
44 "\t\t\tHVR-1250 (reported safe)\n"
45 "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n"
46 "\t\t\tTeVii S470 (reported unsafe)\n"
47 "\t\t This can cause an interrupt storm with some cards.\n"
48 "\t\t Default: 0 [Disabled]");
49
50 /* ------------------------------------------------------------------ */
51 /* board config info */
52
53 struct cx23885_board cx23885_boards[] = {
54 [CX23885_BOARD_UNKNOWN] = {
55 .name = "UNKNOWN/GENERIC",
56 /* Ensure safe default for unknown boards */
57 .clk_freq = 0,
58 .input = {{
59 .type = CX23885_VMUX_COMPOSITE1,
60 .vmux = 0,
61 }, {
62 .type = CX23885_VMUX_COMPOSITE2,
63 .vmux = 1,
64 }, {
65 .type = CX23885_VMUX_COMPOSITE3,
66 .vmux = 2,
67 }, {
68 .type = CX23885_VMUX_COMPOSITE4,
69 .vmux = 3,
70 } },
71 },
72 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
73 .name = "Hauppauge WinTV-HVR1800lp",
74 .portc = CX23885_MPEG_DVB,
75 .input = {{
76 .type = CX23885_VMUX_TELEVISION,
77 .vmux = 0,
78 .gpio0 = 0xff00,
79 }, {
80 .type = CX23885_VMUX_DEBUG,
81 .vmux = 0,
82 .gpio0 = 0xff01,
83 }, {
84 .type = CX23885_VMUX_COMPOSITE1,
85 .vmux = 1,
86 .gpio0 = 0xff02,
87 }, {
88 .type = CX23885_VMUX_SVIDEO,
89 .vmux = 2,
90 .gpio0 = 0xff02,
91 } },
92 },
93 [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
94 .name = "Hauppauge WinTV-HVR1800",
95 .porta = CX23885_ANALOG_VIDEO,
96 .portb = CX23885_MPEG_ENCODER,
97 .portc = CX23885_MPEG_DVB,
98 .tuner_type = TUNER_PHILIPS_TDA8290,
99 .tuner_addr = 0x42, /* 0x84 >> 1 */
100 .tuner_bus = 1,
101 .input = {{
102 .type = CX23885_VMUX_TELEVISION,
103 .vmux = CX25840_VIN7_CH3 |
104 CX25840_VIN5_CH2 |
105 CX25840_VIN2_CH1,
106 .amux = CX25840_AUDIO8,
107 .gpio0 = 0,
108 }, {
109 .type = CX23885_VMUX_COMPOSITE1,
110 .vmux = CX25840_VIN7_CH3 |
111 CX25840_VIN4_CH2 |
112 CX25840_VIN6_CH1,
113 .amux = CX25840_AUDIO7,
114 .gpio0 = 0,
115 }, {
116 .type = CX23885_VMUX_SVIDEO,
117 .vmux = CX25840_VIN7_CH3 |
118 CX25840_VIN4_CH2 |
119 CX25840_VIN8_CH1 |
120 CX25840_SVIDEO_ON,
121 .amux = CX25840_AUDIO7,
122 .gpio0 = 0,
123 } },
124 },
125 [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
126 .name = "Hauppauge WinTV-HVR1250",
127 .porta = CX23885_ANALOG_VIDEO,
128 .portc = CX23885_MPEG_DVB,
129 #ifdef MT2131_NO_ANALOG_SUPPORT_YET
130 .tuner_type = TUNER_PHILIPS_TDA8290,
131 .tuner_addr = 0x42, /* 0x84 >> 1 */
132 .tuner_bus = 1,
133 #endif
134 .force_bff = 1,
135 .input = {{
136 #ifdef MT2131_NO_ANALOG_SUPPORT_YET
137 .type = CX23885_VMUX_TELEVISION,
138 .vmux = CX25840_VIN7_CH3 |
139 CX25840_VIN5_CH2 |
140 CX25840_VIN2_CH1,
141 .amux = CX25840_AUDIO8,
142 .gpio0 = 0xff00,
143 }, {
144 #endif
145 .type = CX23885_VMUX_COMPOSITE1,
146 .vmux = CX25840_VIN7_CH3 |
147 CX25840_VIN4_CH2 |
148 CX25840_VIN6_CH1,
149 .amux = CX25840_AUDIO7,
150 .gpio0 = 0xff02,
151 }, {
152 .type = CX23885_VMUX_SVIDEO,
153 .vmux = CX25840_VIN7_CH3 |
154 CX25840_VIN4_CH2 |
155 CX25840_VIN8_CH1 |
156 CX25840_SVIDEO_ON,
157 .amux = CX25840_AUDIO7,
158 .gpio0 = 0xff02,
159 } },
160 },
161 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
162 .name = "DViCO FusionHDTV5 Express",
163 .portb = CX23885_MPEG_DVB,
164 },
165 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
166 .name = "Hauppauge WinTV-HVR1500Q",
167 .portc = CX23885_MPEG_DVB,
168 },
169 [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
170 .name = "Hauppauge WinTV-HVR1500",
171 .porta = CX23885_ANALOG_VIDEO,
172 .portc = CX23885_MPEG_DVB,
173 .tuner_type = TUNER_XC2028,
174 .tuner_addr = 0x61, /* 0xc2 >> 1 */
175 .input = {{
176 .type = CX23885_VMUX_TELEVISION,
177 .vmux = CX25840_VIN7_CH3 |
178 CX25840_VIN5_CH2 |
179 CX25840_VIN2_CH1,
180 .gpio0 = 0,
181 }, {
182 .type = CX23885_VMUX_COMPOSITE1,
183 .vmux = CX25840_VIN7_CH3 |
184 CX25840_VIN4_CH2 |
185 CX25840_VIN6_CH1,
186 .gpio0 = 0,
187 }, {
188 .type = CX23885_VMUX_SVIDEO,
189 .vmux = CX25840_VIN7_CH3 |
190 CX25840_VIN4_CH2 |
191 CX25840_VIN8_CH1 |
192 CX25840_SVIDEO_ON,
193 .gpio0 = 0,
194 } },
195 },
196 [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
197 .name = "Hauppauge WinTV-HVR1200",
198 .portc = CX23885_MPEG_DVB,
199 },
200 [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
201 .name = "Hauppauge WinTV-HVR1700",
202 .portc = CX23885_MPEG_DVB,
203 },
204 [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
205 .name = "Hauppauge WinTV-HVR1400",
206 .portc = CX23885_MPEG_DVB,
207 },
208 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
209 .name = "DViCO FusionHDTV7 Dual Express",
210 .portb = CX23885_MPEG_DVB,
211 .portc = CX23885_MPEG_DVB,
212 },
213 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
214 .name = "DViCO FusionHDTV DVB-T Dual Express",
215 .portb = CX23885_MPEG_DVB,
216 .portc = CX23885_MPEG_DVB,
217 },
218 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
219 .name = "Leadtek Winfast PxDVR3200 H",
220 .portc = CX23885_MPEG_DVB,
221 },
222 [CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200] = {
223 .name = "Leadtek Winfast PxPVR2200",
224 .porta = CX23885_ANALOG_VIDEO,
225 .tuner_type = TUNER_XC2028,
226 .tuner_addr = 0x61,
227 .tuner_bus = 1,
228 .input = {{
229 .type = CX23885_VMUX_TELEVISION,
230 .vmux = CX25840_VIN2_CH1 |
231 CX25840_VIN5_CH2,
232 .amux = CX25840_AUDIO8,
233 .gpio0 = 0x704040,
234 }, {
235 .type = CX23885_VMUX_COMPOSITE1,
236 .vmux = CX25840_COMPOSITE1,
237 .amux = CX25840_AUDIO7,
238 .gpio0 = 0x704040,
239 }, {
240 .type = CX23885_VMUX_SVIDEO,
241 .vmux = CX25840_SVIDEO_LUMA3 |
242 CX25840_SVIDEO_CHROMA4,
243 .amux = CX25840_AUDIO7,
244 .gpio0 = 0x704040,
245 }, {
246 .type = CX23885_VMUX_COMPONENT,
247 .vmux = CX25840_VIN7_CH1 |
248 CX25840_VIN6_CH2 |
249 CX25840_VIN8_CH3 |
250 CX25840_COMPONENT_ON,
251 .amux = CX25840_AUDIO7,
252 .gpio0 = 0x704040,
253 } },
254 },
255 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
256 .name = "Leadtek Winfast PxDVR3200 H XC4000",
257 .porta = CX23885_ANALOG_VIDEO,
258 .portc = CX23885_MPEG_DVB,
259 .tuner_type = TUNER_XC4000,
260 .tuner_addr = 0x61,
261 .radio_type = UNSET,
262 .radio_addr = ADDR_UNSET,
263 .input = {{
264 .type = CX23885_VMUX_TELEVISION,
265 .vmux = CX25840_VIN2_CH1 |
266 CX25840_VIN5_CH2 |
267 CX25840_NONE0_CH3,
268 }, {
269 .type = CX23885_VMUX_COMPOSITE1,
270 .vmux = CX25840_COMPOSITE1,
271 }, {
272 .type = CX23885_VMUX_SVIDEO,
273 .vmux = CX25840_SVIDEO_LUMA3 |
274 CX25840_SVIDEO_CHROMA4,
275 }, {
276 .type = CX23885_VMUX_COMPONENT,
277 .vmux = CX25840_VIN7_CH1 |
278 CX25840_VIN6_CH2 |
279 CX25840_VIN8_CH3 |
280 CX25840_COMPONENT_ON,
281 } },
282 },
283 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
284 .name = "Compro VideoMate E650F",
285 .portc = CX23885_MPEG_DVB,
286 },
287 [CX23885_BOARD_TBS_6920] = {
288 .name = "TurboSight TBS 6920",
289 .portb = CX23885_MPEG_DVB,
290 },
291 [CX23885_BOARD_TBS_6980] = {
292 .name = "TurboSight TBS 6980",
293 .portb = CX23885_MPEG_DVB,
294 .portc = CX23885_MPEG_DVB,
295 },
296 [CX23885_BOARD_TBS_6981] = {
297 .name = "TurboSight TBS 6981",
298 .portb = CX23885_MPEG_DVB,
299 .portc = CX23885_MPEG_DVB,
300 },
301 [CX23885_BOARD_TEVII_S470] = {
302 .name = "TeVii S470",
303 .portb = CX23885_MPEG_DVB,
304 },
305 [CX23885_BOARD_DVBWORLD_2005] = {
306 .name = "DVBWorld DVB-S2 2005",
307 .portb = CX23885_MPEG_DVB,
308 },
309 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
310 .ci_type = 1,
311 .name = "NetUP Dual DVB-S2 CI",
312 .portb = CX23885_MPEG_DVB,
313 .portc = CX23885_MPEG_DVB,
314 },
315 [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
316 .name = "Hauppauge WinTV-HVR1270",
317 .portc = CX23885_MPEG_DVB,
318 },
319 [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
320 .name = "Hauppauge WinTV-HVR1275",
321 .portc = CX23885_MPEG_DVB,
322 },
323 [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
324 .name = "Hauppauge WinTV-HVR1255",
325 .porta = CX23885_ANALOG_VIDEO,
326 .portc = CX23885_MPEG_DVB,
327 .tuner_type = TUNER_ABSENT,
328 .tuner_addr = 0x42, /* 0x84 >> 1 */
329 .force_bff = 1,
330 .input = {{
331 .type = CX23885_VMUX_TELEVISION,
332 .vmux = CX25840_VIN7_CH3 |
333 CX25840_VIN5_CH2 |
334 CX25840_VIN2_CH1 |
335 CX25840_DIF_ON,
336 .amux = CX25840_AUDIO8,
337 }, {
338 .type = CX23885_VMUX_COMPOSITE1,
339 .vmux = CX25840_VIN7_CH3 |
340 CX25840_VIN4_CH2 |
341 CX25840_VIN6_CH1,
342 .amux = CX25840_AUDIO7,
343 }, {
344 .type = CX23885_VMUX_SVIDEO,
345 .vmux = CX25840_VIN7_CH3 |
346 CX25840_VIN4_CH2 |
347 CX25840_VIN8_CH1 |
348 CX25840_SVIDEO_ON,
349 .amux = CX25840_AUDIO7,
350 } },
351 },
352 [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = {
353 .name = "Hauppauge WinTV-HVR1255",
354 .porta = CX23885_ANALOG_VIDEO,
355 .portc = CX23885_MPEG_DVB,
356 .tuner_type = TUNER_ABSENT,
357 .tuner_addr = 0x42, /* 0x84 >> 1 */
358 .force_bff = 1,
359 .input = {{
360 .type = CX23885_VMUX_TELEVISION,
361 .vmux = CX25840_VIN7_CH3 |
362 CX25840_VIN5_CH2 |
363 CX25840_VIN2_CH1 |
364 CX25840_DIF_ON,
365 .amux = CX25840_AUDIO8,
366 }, {
367 .type = CX23885_VMUX_SVIDEO,
368 .vmux = CX25840_VIN7_CH3 |
369 CX25840_VIN4_CH2 |
370 CX25840_VIN8_CH1 |
371 CX25840_SVIDEO_ON,
372 .amux = CX25840_AUDIO7,
373 } },
374 },
375 [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
376 .name = "Hauppauge WinTV-HVR1210",
377 .portc = CX23885_MPEG_DVB,
378 },
379 [CX23885_BOARD_MYGICA_X8506] = {
380 .name = "Mygica X8506 DMB-TH",
381 .tuner_type = TUNER_XC5000,
382 .tuner_addr = 0x61,
383 .tuner_bus = 1,
384 .porta = CX23885_ANALOG_VIDEO,
385 .portb = CX23885_MPEG_DVB,
386 .input = {
387 {
388 .type = CX23885_VMUX_TELEVISION,
389 .vmux = CX25840_COMPOSITE2,
390 },
391 {
392 .type = CX23885_VMUX_COMPOSITE1,
393 .vmux = CX25840_COMPOSITE8,
394 },
395 {
396 .type = CX23885_VMUX_SVIDEO,
397 .vmux = CX25840_SVIDEO_LUMA3 |
398 CX25840_SVIDEO_CHROMA4,
399 },
400 {
401 .type = CX23885_VMUX_COMPONENT,
402 .vmux = CX25840_COMPONENT_ON |
403 CX25840_VIN1_CH1 |
404 CX25840_VIN6_CH2 |
405 CX25840_VIN7_CH3,
406 },
407 },
408 },
409 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
410 .name = "Magic-Pro ProHDTV Extreme 2",
411 .tuner_type = TUNER_XC5000,
412 .tuner_addr = 0x61,
413 .tuner_bus = 1,
414 .porta = CX23885_ANALOG_VIDEO,
415 .portb = CX23885_MPEG_DVB,
416 .input = {
417 {
418 .type = CX23885_VMUX_TELEVISION,
419 .vmux = CX25840_COMPOSITE2,
420 },
421 {
422 .type = CX23885_VMUX_COMPOSITE1,
423 .vmux = CX25840_COMPOSITE8,
424 },
425 {
426 .type = CX23885_VMUX_SVIDEO,
427 .vmux = CX25840_SVIDEO_LUMA3 |
428 CX25840_SVIDEO_CHROMA4,
429 },
430 {
431 .type = CX23885_VMUX_COMPONENT,
432 .vmux = CX25840_COMPONENT_ON |
433 CX25840_VIN1_CH1 |
434 CX25840_VIN6_CH2 |
435 CX25840_VIN7_CH3,
436 },
437 },
438 },
439 [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
440 .name = "Hauppauge WinTV-HVR1850",
441 .porta = CX23885_ANALOG_VIDEO,
442 .portb = CX23885_MPEG_ENCODER,
443 .portc = CX23885_MPEG_DVB,
444 .tuner_type = TUNER_ABSENT,
445 .tuner_addr = 0x42, /* 0x84 >> 1 */
446 .force_bff = 1,
447 .input = {{
448 .type = CX23885_VMUX_TELEVISION,
449 .vmux = CX25840_VIN7_CH3 |
450 CX25840_VIN5_CH2 |
451 CX25840_VIN2_CH1 |
452 CX25840_DIF_ON,
453 .amux = CX25840_AUDIO8,
454 }, {
455 .type = CX23885_VMUX_COMPOSITE1,
456 .vmux = CX25840_VIN7_CH3 |
457 CX25840_VIN4_CH2 |
458 CX25840_VIN6_CH1,
459 .amux = CX25840_AUDIO7,
460 }, {
461 .type = CX23885_VMUX_SVIDEO,
462 .vmux = CX25840_VIN7_CH3 |
463 CX25840_VIN4_CH2 |
464 CX25840_VIN8_CH1 |
465 CX25840_SVIDEO_ON,
466 .amux = CX25840_AUDIO7,
467 } },
468 },
469 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
470 .name = "Compro VideoMate E800",
471 .portc = CX23885_MPEG_DVB,
472 },
473 [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
474 .name = "Hauppauge WinTV-HVR1290",
475 .portc = CX23885_MPEG_DVB,
476 },
477 [CX23885_BOARD_MYGICA_X8558PRO] = {
478 .name = "Mygica X8558 PRO DMB-TH",
479 .portb = CX23885_MPEG_DVB,
480 .portc = CX23885_MPEG_DVB,
481 },
482 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
483 .name = "LEADTEK WinFast PxTV1200",
484 .porta = CX23885_ANALOG_VIDEO,
485 .tuner_type = TUNER_XC2028,
486 .tuner_addr = 0x61,
487 .tuner_bus = 1,
488 .input = {{
489 .type = CX23885_VMUX_TELEVISION,
490 .vmux = CX25840_VIN2_CH1 |
491 CX25840_VIN5_CH2 |
492 CX25840_NONE0_CH3,
493 }, {
494 .type = CX23885_VMUX_COMPOSITE1,
495 .vmux = CX25840_COMPOSITE1,
496 }, {
497 .type = CX23885_VMUX_SVIDEO,
498 .vmux = CX25840_SVIDEO_LUMA3 |
499 CX25840_SVIDEO_CHROMA4,
500 }, {
501 .type = CX23885_VMUX_COMPONENT,
502 .vmux = CX25840_VIN7_CH1 |
503 CX25840_VIN6_CH2 |
504 CX25840_VIN8_CH3 |
505 CX25840_COMPONENT_ON,
506 } },
507 },
508 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
509 .name = "GoTView X5 3D Hybrid",
510 .tuner_type = TUNER_XC5000,
511 .tuner_addr = 0x64,
512 .tuner_bus = 1,
513 .porta = CX23885_ANALOG_VIDEO,
514 .portb = CX23885_MPEG_DVB,
515 .input = {{
516 .type = CX23885_VMUX_TELEVISION,
517 .vmux = CX25840_VIN2_CH1 |
518 CX25840_VIN5_CH2,
519 .gpio0 = 0x02,
520 }, {
521 .type = CX23885_VMUX_COMPOSITE1,
522 .vmux = CX23885_VMUX_COMPOSITE1,
523 }, {
524 .type = CX23885_VMUX_SVIDEO,
525 .vmux = CX25840_SVIDEO_LUMA3 |
526 CX25840_SVIDEO_CHROMA4,
527 } },
528 },
529 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
530 .ci_type = 2,
531 .name = "NetUP Dual DVB-T/C-CI RF",
532 .porta = CX23885_ANALOG_VIDEO,
533 .portb = CX23885_MPEG_DVB,
534 .portc = CX23885_MPEG_DVB,
535 .num_fds_portb = 2,
536 .num_fds_portc = 2,
537 .tuner_type = TUNER_XC5000,
538 .tuner_addr = 0x64,
539 .input = { {
540 .type = CX23885_VMUX_TELEVISION,
541 .vmux = CX25840_COMPOSITE1,
542 } },
543 },
544 [CX23885_BOARD_MPX885] = {
545 .name = "MPX-885",
546 .porta = CX23885_ANALOG_VIDEO,
547 .input = {{
548 .type = CX23885_VMUX_COMPOSITE1,
549 .vmux = CX25840_COMPOSITE1,
550 .amux = CX25840_AUDIO6,
551 .gpio0 = 0,
552 }, {
553 .type = CX23885_VMUX_COMPOSITE2,
554 .vmux = CX25840_COMPOSITE2,
555 .amux = CX25840_AUDIO6,
556 .gpio0 = 0,
557 }, {
558 .type = CX23885_VMUX_COMPOSITE3,
559 .vmux = CX25840_COMPOSITE3,
560 .amux = CX25840_AUDIO7,
561 .gpio0 = 0,
562 }, {
563 .type = CX23885_VMUX_COMPOSITE4,
564 .vmux = CX25840_COMPOSITE4,
565 .amux = CX25840_AUDIO7,
566 .gpio0 = 0,
567 } },
568 },
569 [CX23885_BOARD_MYGICA_X8507] = {
570 .name = "Mygica X8502/X8507 ISDB-T",
571 .tuner_type = TUNER_XC5000,
572 .tuner_addr = 0x61,
573 .tuner_bus = 1,
574 .porta = CX23885_ANALOG_VIDEO,
575 .portb = CX23885_MPEG_DVB,
576 .input = {
577 {
578 .type = CX23885_VMUX_TELEVISION,
579 .vmux = CX25840_COMPOSITE2,
580 .amux = CX25840_AUDIO8,
581 },
582 {
583 .type = CX23885_VMUX_COMPOSITE1,
584 .vmux = CX25840_COMPOSITE8,
585 .amux = CX25840_AUDIO7,
586 },
587 {
588 .type = CX23885_VMUX_SVIDEO,
589 .vmux = CX25840_SVIDEO_LUMA3 |
590 CX25840_SVIDEO_CHROMA4,
591 .amux = CX25840_AUDIO7,
592 },
593 {
594 .type = CX23885_VMUX_COMPONENT,
595 .vmux = CX25840_COMPONENT_ON |
596 CX25840_VIN1_CH1 |
597 CX25840_VIN6_CH2 |
598 CX25840_VIN7_CH3,
599 .amux = CX25840_AUDIO7,
600 },
601 },
602 },
603 [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = {
604 .name = "TerraTec Cinergy T PCIe Dual",
605 .portb = CX23885_MPEG_DVB,
606 .portc = CX23885_MPEG_DVB,
607 },
608 [CX23885_BOARD_TEVII_S471] = {
609 .name = "TeVii S471",
610 .portb = CX23885_MPEG_DVB,
611 },
612 [CX23885_BOARD_PROF_8000] = {
613 .name = "Prof Revolution DVB-S2 8000",
614 .portb = CX23885_MPEG_DVB,
615 },
616 [CX23885_BOARD_HAUPPAUGE_HVR4400] = {
617 .name = "Hauppauge WinTV-HVR4400/HVR5500",
618 .porta = CX23885_ANALOG_VIDEO,
619 .portb = CX23885_MPEG_DVB,
620 .portc = CX23885_MPEG_DVB,
621 .tuner_type = TUNER_NXP_TDA18271,
622 .tuner_addr = 0x60, /* 0xc0 >> 1 */
623 .tuner_bus = 1,
624 },
625 [CX23885_BOARD_HAUPPAUGE_STARBURST] = {
626 .name = "Hauppauge WinTV Starburst",
627 .portb = CX23885_MPEG_DVB,
628 },
629 [CX23885_BOARD_AVERMEDIA_HC81R] = {
630 .name = "AVerTV Hybrid Express Slim HC81R",
631 .tuner_type = TUNER_XC2028,
632 .tuner_addr = 0x61, /* 0xc2 >> 1 */
633 .tuner_bus = 1,
634 .porta = CX23885_ANALOG_VIDEO,
635 .input = {{
636 .type = CX23885_VMUX_TELEVISION,
637 .vmux = CX25840_VIN2_CH1 |
638 CX25840_VIN5_CH2 |
639 CX25840_NONE0_CH3 |
640 CX25840_NONE1_CH3,
641 .amux = CX25840_AUDIO8,
642 }, {
643 .type = CX23885_VMUX_SVIDEO,
644 .vmux = CX25840_VIN8_CH1 |
645 CX25840_NONE_CH2 |
646 CX25840_VIN7_CH3 |
647 CX25840_SVIDEO_ON,
648 .amux = CX25840_AUDIO6,
649 }, {
650 .type = CX23885_VMUX_COMPONENT,
651 .vmux = CX25840_VIN1_CH1 |
652 CX25840_NONE_CH2 |
653 CX25840_NONE0_CH3 |
654 CX25840_NONE1_CH3,
655 .amux = CX25840_AUDIO6,
656 } },
657 },
658 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2] = {
659 .name = "DViCO FusionHDTV DVB-T Dual Express2",
660 .portb = CX23885_MPEG_DVB,
661 .portc = CX23885_MPEG_DVB,
662 },
663 [CX23885_BOARD_HAUPPAUGE_IMPACTVCBE] = {
664 .name = "Hauppauge ImpactVCB-e",
665 .tuner_type = TUNER_ABSENT,
666 .porta = CX23885_ANALOG_VIDEO,
667 .input = {{
668 .type = CX23885_VMUX_COMPOSITE1,
669 .vmux = CX25840_VIN7_CH3 |
670 CX25840_VIN4_CH2 |
671 CX25840_VIN6_CH1,
672 .amux = CX25840_AUDIO7,
673 }, {
674 .type = CX23885_VMUX_SVIDEO,
675 .vmux = CX25840_VIN7_CH3 |
676 CX25840_VIN4_CH2 |
677 CX25840_VIN8_CH1 |
678 CX25840_SVIDEO_ON,
679 .amux = CX25840_AUDIO7,
680 } },
681 },
682 [CX23885_BOARD_DVBSKY_T9580] = {
683 .name = "DVBSky T9580",
684 .portb = CX23885_MPEG_DVB,
685 .portc = CX23885_MPEG_DVB,
686 },
687 [CX23885_BOARD_DVBSKY_T980C] = {
688 .name = "DVBSky T980C",
689 .portb = CX23885_MPEG_DVB,
690 },
691 [CX23885_BOARD_DVBSKY_S950C] = {
692 .name = "DVBSky S950C",
693 .portb = CX23885_MPEG_DVB,
694 },
695 [CX23885_BOARD_TT_CT2_4500_CI] = {
696 .name = "Technotrend TT-budget CT2-4500 CI",
697 .portb = CX23885_MPEG_DVB,
698 },
699 [CX23885_BOARD_DVBSKY_S950] = {
700 .name = "DVBSky S950",
701 .portb = CX23885_MPEG_DVB,
702 },
703 [CX23885_BOARD_DVBSKY_S952] = {
704 .name = "DVBSky S952",
705 .portb = CX23885_MPEG_DVB,
706 .portc = CX23885_MPEG_DVB,
707 },
708 [CX23885_BOARD_DVBSKY_T982] = {
709 .name = "DVBSky T982",
710 .portb = CX23885_MPEG_DVB,
711 .portc = CX23885_MPEG_DVB,
712 },
713 [CX23885_BOARD_HAUPPAUGE_HVR5525] = {
714 .name = "Hauppauge WinTV-HVR5525",
715 .portb = CX23885_MPEG_DVB,
716 .portc = CX23885_MPEG_DVB,
717 },
718 [CX23885_BOARD_VIEWCAST_260E] = {
719 .name = "ViewCast 260e",
720 .porta = CX23885_ANALOG_VIDEO,
721 .force_bff = 1,
722 .input = {{
723 .type = CX23885_VMUX_COMPOSITE1,
724 .vmux = CX25840_VIN6_CH1,
725 .amux = CX25840_AUDIO7,
726 }, {
727 .type = CX23885_VMUX_SVIDEO,
728 .vmux = CX25840_VIN7_CH3 |
729 CX25840_VIN5_CH1 |
730 CX25840_SVIDEO_ON,
731 .amux = CX25840_AUDIO7,
732 }, {
733 .type = CX23885_VMUX_COMPONENT,
734 .vmux = CX25840_VIN7_CH3 |
735 CX25840_VIN6_CH2 |
736 CX25840_VIN5_CH1 |
737 CX25840_COMPONENT_ON,
738 .amux = CX25840_AUDIO7,
739 } },
740 },
741 [CX23885_BOARD_VIEWCAST_460E] = {
742 .name = "ViewCast 460e",
743 .porta = CX23885_ANALOG_VIDEO,
744 .force_bff = 1,
745 .input = {{
746 .type = CX23885_VMUX_COMPOSITE1,
747 .vmux = CX25840_VIN4_CH1,
748 .amux = CX25840_AUDIO7,
749 }, {
750 .type = CX23885_VMUX_SVIDEO,
751 .vmux = CX25840_VIN7_CH3 |
752 CX25840_VIN6_CH1 |
753 CX25840_SVIDEO_ON,
754 .amux = CX25840_AUDIO7,
755 }, {
756 .type = CX23885_VMUX_COMPONENT,
757 .vmux = CX25840_VIN7_CH3 |
758 CX25840_VIN6_CH1 |
759 CX25840_VIN5_CH2 |
760 CX25840_COMPONENT_ON,
761 .amux = CX25840_AUDIO7,
762 }, {
763 .type = CX23885_VMUX_COMPOSITE2,
764 .vmux = CX25840_VIN6_CH1,
765 .amux = CX25840_AUDIO7,
766 } },
767 },
768 [CX23885_BOARD_HAUPPAUGE_QUADHD_DVB] = {
769 .name = "Hauppauge WinTV-QuadHD-DVB",
770 .portb = CX23885_MPEG_DVB,
771 .portc = CX23885_MPEG_DVB,
772 },
773 [CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC] = {
774 .name = "Hauppauge WinTV-QuadHD-ATSC",
775 .portb = CX23885_MPEG_DVB,
776 .portc = CX23885_MPEG_DVB,
777 },
778 };
779 const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
780
781 /* ------------------------------------------------------------------ */
782 /* PCI subsystem IDs */
783
784 struct cx23885_subid cx23885_subids[] = {
785 {
786 .subvendor = 0x0070,
787 .subdevice = 0x3400,
788 .card = CX23885_BOARD_UNKNOWN,
789 }, {
790 .subvendor = 0x0070,
791 .subdevice = 0x7600,
792 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
793 }, {
794 .subvendor = 0x0070,
795 .subdevice = 0x7800,
796 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
797 }, {
798 .subvendor = 0x0070,
799 .subdevice = 0x7801,
800 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
801 }, {
802 .subvendor = 0x0070,
803 .subdevice = 0x7809,
804 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
805 }, {
806 .subvendor = 0x0070,
807 .subdevice = 0x7911,
808 .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
809 }, {
810 .subvendor = 0x18ac,
811 .subdevice = 0xd500,
812 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
813 }, {
814 .subvendor = 0x0070,
815 .subdevice = 0x7790,
816 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
817 }, {
818 .subvendor = 0x0070,
819 .subdevice = 0x7797,
820 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
821 }, {
822 .subvendor = 0x0070,
823 .subdevice = 0x7710,
824 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
825 }, {
826 .subvendor = 0x0070,
827 .subdevice = 0x7717,
828 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
829 }, {
830 .subvendor = 0x0070,
831 .subdevice = 0x71d1,
832 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
833 }, {
834 .subvendor = 0x0070,
835 .subdevice = 0x71d3,
836 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
837 }, {
838 .subvendor = 0x0070,
839 .subdevice = 0x8101,
840 .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
841 }, {
842 .subvendor = 0x0070,
843 .subdevice = 0x8010,
844 .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
845 }, {
846 .subvendor = 0x18ac,
847 .subdevice = 0xd618,
848 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
849 }, {
850 .subvendor = 0x18ac,
851 .subdevice = 0xdb78,
852 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
853 }, {
854 .subvendor = 0x107d,
855 .subdevice = 0x6681,
856 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
857 }, {
858 .subvendor = 0x107d,
859 .subdevice = 0x6f21,
860 .card = CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200,
861 }, {
862 .subvendor = 0x107d,
863 .subdevice = 0x6f39,
864 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
865 }, {
866 .subvendor = 0x185b,
867 .subdevice = 0xe800,
868 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
869 }, {
870 .subvendor = 0x6920,
871 .subdevice = 0x8888,
872 .card = CX23885_BOARD_TBS_6920,
873 }, {
874 .subvendor = 0x6980,
875 .subdevice = 0x8888,
876 .card = CX23885_BOARD_TBS_6980,
877 }, {
878 .subvendor = 0x6981,
879 .subdevice = 0x8888,
880 .card = CX23885_BOARD_TBS_6981,
881 }, {
882 .subvendor = 0xd470,
883 .subdevice = 0x9022,
884 .card = CX23885_BOARD_TEVII_S470,
885 }, {
886 .subvendor = 0x0001,
887 .subdevice = 0x2005,
888 .card = CX23885_BOARD_DVBWORLD_2005,
889 }, {
890 .subvendor = 0x1b55,
891 .subdevice = 0x2a2c,
892 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
893 }, {
894 .subvendor = 0x0070,
895 .subdevice = 0x2211,
896 .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
897 }, {
898 .subvendor = 0x0070,
899 .subdevice = 0x2215,
900 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
901 }, {
902 .subvendor = 0x0070,
903 .subdevice = 0x221d,
904 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
905 }, {
906 .subvendor = 0x0070,
907 .subdevice = 0x2251,
908 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
909 }, {
910 .subvendor = 0x0070,
911 .subdevice = 0x2259,
912 .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111,
913 }, {
914 .subvendor = 0x0070,
915 .subdevice = 0x2291,
916 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
917 }, {
918 .subvendor = 0x0070,
919 .subdevice = 0x2295,
920 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
921 }, {
922 .subvendor = 0x0070,
923 .subdevice = 0x2299,
924 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
925 }, {
926 .subvendor = 0x0070,
927 .subdevice = 0x229d,
928 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
929 }, {
930 .subvendor = 0x0070,
931 .subdevice = 0x22f0,
932 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
933 }, {
934 .subvendor = 0x0070,
935 .subdevice = 0x22f1,
936 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
937 }, {
938 .subvendor = 0x0070,
939 .subdevice = 0x22f2,
940 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
941 }, {
942 .subvendor = 0x0070,
943 .subdevice = 0x22f3,
944 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
945 }, {
946 .subvendor = 0x0070,
947 .subdevice = 0x22f4,
948 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
949 }, {
950 .subvendor = 0x0070,
951 .subdevice = 0x22f5,
952 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
953 }, {
954 .subvendor = 0x14f1,
955 .subdevice = 0x8651,
956 .card = CX23885_BOARD_MYGICA_X8506,
957 }, {
958 .subvendor = 0x14f1,
959 .subdevice = 0x8657,
960 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
961 }, {
962 .subvendor = 0x0070,
963 .subdevice = 0x8541,
964 .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
965 }, {
966 .subvendor = 0x1858,
967 .subdevice = 0xe800,
968 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
969 }, {
970 .subvendor = 0x0070,
971 .subdevice = 0x8551,
972 .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
973 }, {
974 .subvendor = 0x14f1,
975 .subdevice = 0x8578,
976 .card = CX23885_BOARD_MYGICA_X8558PRO,
977 }, {
978 .subvendor = 0x107d,
979 .subdevice = 0x6f22,
980 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
981 }, {
982 .subvendor = 0x5654,
983 .subdevice = 0x2390,
984 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
985 }, {
986 .subvendor = 0x1b55,
987 .subdevice = 0xe2e4,
988 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
989 }, {
990 .subvendor = 0x14f1,
991 .subdevice = 0x8502,
992 .card = CX23885_BOARD_MYGICA_X8507,
993 }, {
994 .subvendor = 0x153b,
995 .subdevice = 0x117e,
996 .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL,
997 }, {
998 .subvendor = 0xd471,
999 .subdevice = 0x9022,
1000 .card = CX23885_BOARD_TEVII_S471,
1001 }, {
1002 .subvendor = 0x8000,
1003 .subdevice = 0x3034,
1004 .card = CX23885_BOARD_PROF_8000,
1005 }, {
1006 .subvendor = 0x0070,
1007 .subdevice = 0xc108,
1008 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-4400 (Model 121xxx, Hybrid DVB-T/S2, IR) */
1009 }, {
1010 .subvendor = 0x0070,
1011 .subdevice = 0xc138,
1012 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */
1013 }, {
1014 .subvendor = 0x0070,
1015 .subdevice = 0xc12a,
1016 .card = CX23885_BOARD_HAUPPAUGE_STARBURST, /* Hauppauge WinTV Starburst (Model 121x00, DVB-S2, IR) */
1017 }, {
1018 .subvendor = 0x0070,
1019 .subdevice = 0xc1f8,
1020 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */
1021 }, {
1022 .subvendor = 0x1461,
1023 .subdevice = 0xd939,
1024 .card = CX23885_BOARD_AVERMEDIA_HC81R,
1025 }, {
1026 .subvendor = 0x0070,
1027 .subdevice = 0x7133,
1028 .card = CX23885_BOARD_HAUPPAUGE_IMPACTVCBE,
1029 }, {
1030 .subvendor = 0x18ac,
1031 .subdevice = 0xdb98,
1032 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2,
1033 }, {
1034 .subvendor = 0x4254,
1035 .subdevice = 0x9580,
1036 .card = CX23885_BOARD_DVBSKY_T9580,
1037 }, {
1038 .subvendor = 0x4254,
1039 .subdevice = 0x980c,
1040 .card = CX23885_BOARD_DVBSKY_T980C,
1041 }, {
1042 .subvendor = 0x4254,
1043 .subdevice = 0x950c,
1044 .card = CX23885_BOARD_DVBSKY_S950C,
1045 }, {
1046 .subvendor = 0x13c2,
1047 .subdevice = 0x3013,
1048 .card = CX23885_BOARD_TT_CT2_4500_CI,
1049 }, {
1050 .subvendor = 0x4254,
1051 .subdevice = 0x0950,
1052 .card = CX23885_BOARD_DVBSKY_S950,
1053 }, {
1054 .subvendor = 0x4254,
1055 .subdevice = 0x0952,
1056 .card = CX23885_BOARD_DVBSKY_S952,
1057 }, {
1058 .subvendor = 0x4254,
1059 .subdevice = 0x0982,
1060 .card = CX23885_BOARD_DVBSKY_T982,
1061 }, {
1062 .subvendor = 0x0070,
1063 .subdevice = 0xf038,
1064 .card = CX23885_BOARD_HAUPPAUGE_HVR5525,
1065 }, {
1066 .subvendor = 0x1576,
1067 .subdevice = 0x0260,
1068 .card = CX23885_BOARD_VIEWCAST_260E,
1069 }, {
1070 .subvendor = 0x1576,
1071 .subdevice = 0x0460,
1072 .card = CX23885_BOARD_VIEWCAST_460E,
1073 }, {
1074 .subvendor = 0x0070,
1075 .subdevice = 0x6a28,
1076 .card = CX23885_BOARD_HAUPPAUGE_QUADHD_DVB, /* Tuner Pair 1 */
1077 }, {
1078 .subvendor = 0x0070,
1079 .subdevice = 0x6b28,
1080 .card = CX23885_BOARD_HAUPPAUGE_QUADHD_DVB, /* Tuner Pair 2 */
1081 }, {
1082 .subvendor = 0x0070,
1083 .subdevice = 0x6a18,
1084 .card = CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC, /* Tuner Pair 1 */
1085 }, {
1086 .subvendor = 0x0070,
1087 .subdevice = 0x6b18,
1088 .card = CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC, /* Tuner Pair 2 */
1089 },
1090 };
1091 const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
1092
1093 void cx23885_card_list(struct cx23885_dev *dev)
1094 {
1095 int i;
1096
1097 if (0 == dev->pci->subsystem_vendor &&
1098 0 == dev->pci->subsystem_device) {
1099 printk(KERN_INFO
1100 "%s: Board has no valid PCIe Subsystem ID and can't\n"
1101 "%s: be autodetected. Pass card=<n> insmod option\n"
1102 "%s: to workaround that. Redirect complaints to the\n"
1103 "%s: vendor of the TV card. Best regards,\n"
1104 "%s: -- tux\n",
1105 dev->name, dev->name, dev->name, dev->name, dev->name);
1106 } else {
1107 printk(KERN_INFO
1108 "%s: Your board isn't known (yet) to the driver.\n"
1109 "%s: Try to pick one of the existing card configs via\n"
1110 "%s: card=<n> insmod option. Updating to the latest\n"
1111 "%s: version might help as well.\n",
1112 dev->name, dev->name, dev->name, dev->name);
1113 }
1114 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
1115 dev->name);
1116 for (i = 0; i < cx23885_bcount; i++)
1117 printk(KERN_INFO "%s: card=%d -> %s\n",
1118 dev->name, i, cx23885_boards[i].name);
1119 }
1120
1121 static void viewcast_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
1122 {
1123 u32 sn;
1124
1125 /* The serial number record begins with tag 0x59 */
1126 if (*(eeprom_data + 0x00) != 0x59) {
1127 pr_info("%s() eeprom records are undefined, no serial number\n",
1128 __func__);
1129 return;
1130 }
1131
1132 sn = (*(eeprom_data + 0x06) << 24) |
1133 (*(eeprom_data + 0x05) << 16) |
1134 (*(eeprom_data + 0x04) << 8) |
1135 (*(eeprom_data + 0x03));
1136
1137 pr_info("%s: card '%s' sn# MM%d\n",
1138 dev->name,
1139 cx23885_boards[dev->board].name,
1140 sn);
1141 }
1142
1143 static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
1144 {
1145 struct tveeprom tv;
1146
1147 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
1148 eeprom_data);
1149
1150 /* Make sure we support the board model */
1151 switch (tv.model) {
1152 case 22001:
1153 /* WinTV-HVR1270 (PCIe, Retail, half height)
1154 * ATSC/QAM and basic analog, IR Blast */
1155 case 22009:
1156 /* WinTV-HVR1210 (PCIe, Retail, half height)
1157 * DVB-T and basic analog, IR Blast */
1158 case 22011:
1159 /* WinTV-HVR1270 (PCIe, Retail, half height)
1160 * ATSC/QAM and basic analog, IR Recv */
1161 case 22019:
1162 /* WinTV-HVR1210 (PCIe, Retail, half height)
1163 * DVB-T and basic analog, IR Recv */
1164 case 22021:
1165 /* WinTV-HVR1275 (PCIe, Retail, half height)
1166 * ATSC/QAM and basic analog, IR Recv */
1167 case 22029:
1168 /* WinTV-HVR1210 (PCIe, Retail, half height)
1169 * DVB-T and basic analog, IR Recv */
1170 case 22101:
1171 /* WinTV-HVR1270 (PCIe, Retail, full height)
1172 * ATSC/QAM and basic analog, IR Blast */
1173 case 22109:
1174 /* WinTV-HVR1210 (PCIe, Retail, full height)
1175 * DVB-T and basic analog, IR Blast */
1176 case 22111:
1177 /* WinTV-HVR1270 (PCIe, Retail, full height)
1178 * ATSC/QAM and basic analog, IR Recv */
1179 case 22119:
1180 /* WinTV-HVR1210 (PCIe, Retail, full height)
1181 * DVB-T and basic analog, IR Recv */
1182 case 22121:
1183 /* WinTV-HVR1275 (PCIe, Retail, full height)
1184 * ATSC/QAM and basic analog, IR Recv */
1185 case 22129:
1186 /* WinTV-HVR1210 (PCIe, Retail, full height)
1187 * DVB-T and basic analog, IR Recv */
1188 case 71009:
1189 /* WinTV-HVR1200 (PCIe, Retail, full height)
1190 * DVB-T and basic analog */
1191 case 71100:
1192 /* WinTV-ImpactVCB-e (PCIe, Retail, half height)
1193 * Basic analog */
1194 case 71359:
1195 /* WinTV-HVR1200 (PCIe, OEM, half height)
1196 * DVB-T and basic analog */
1197 case 71439:
1198 /* WinTV-HVR1200 (PCIe, OEM, half height)
1199 * DVB-T and basic analog */
1200 case 71449:
1201 /* WinTV-HVR1200 (PCIe, OEM, full height)
1202 * DVB-T and basic analog */
1203 case 71939:
1204 /* WinTV-HVR1200 (PCIe, OEM, half height)
1205 * DVB-T and basic analog */
1206 case 71949:
1207 /* WinTV-HVR1200 (PCIe, OEM, full height)
1208 * DVB-T and basic analog */
1209 case 71959:
1210 /* WinTV-HVR1200 (PCIe, OEM, full height)
1211 * DVB-T and basic analog */
1212 case 71979:
1213 /* WinTV-HVR1200 (PCIe, OEM, half height)
1214 * DVB-T and basic analog */
1215 case 71999:
1216 /* WinTV-HVR1200 (PCIe, OEM, full height)
1217 * DVB-T and basic analog */
1218 case 76601:
1219 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
1220 channel ATSC and MPEG2 HW Encoder */
1221 case 77001:
1222 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
1223 and Basic analog */
1224 case 77011:
1225 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
1226 and Basic analog */
1227 case 77041:
1228 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
1229 and Basic analog */
1230 case 77051:
1231 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
1232 and Basic analog */
1233 case 78011:
1234 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
1235 Dual channel ATSC and MPEG2 HW Encoder */
1236 case 78501:
1237 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
1238 Dual channel ATSC and MPEG2 HW Encoder */
1239 case 78521:
1240 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
1241 Dual channel ATSC and MPEG2 HW Encoder */
1242 case 78531:
1243 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
1244 Dual channel ATSC and MPEG2 HW Encoder */
1245 case 78631:
1246 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
1247 Dual channel ATSC and MPEG2 HW Encoder */
1248 case 79001:
1249 /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
1250 ATSC and Basic analog */
1251 case 79101:
1252 /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
1253 ATSC and Basic analog */
1254 case 79501:
1255 /* WinTV-HVR1250 (PCIe, No IR, half height,
1256 ATSC [at least] and Basic analog) */
1257 case 79561:
1258 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
1259 ATSC and Basic analog */
1260 case 79571:
1261 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
1262 ATSC and Basic analog */
1263 case 79671:
1264 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
1265 ATSC and Basic analog */
1266 case 80019:
1267 /* WinTV-HVR1400 (Express Card, Retail, IR,
1268 * DVB-T and Basic analog */
1269 case 81509:
1270 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
1271 * DVB-T and MPEG2 HW Encoder */
1272 case 81519:
1273 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
1274 * DVB-T and MPEG2 HW Encoder */
1275 break;
1276 case 85021:
1277 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
1278 Dual channel ATSC and MPEG2 HW Encoder */
1279 break;
1280 case 85721:
1281 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
1282 Dual channel ATSC and Basic analog */
1283 case 150329:
1284 /* WinTV-HVR5525 (PCIe, DVB-S/S2, DVB-T/T2/C) */
1285 break;
1286 case 166100:
1287 /* WinTV-QuadHD (DVB) Tuner Pair 1 (PCIe, IR, half height,
1288 DVB-T/T2/C, DVB-T/T2/C */
1289 break;
1290 case 166101:
1291 /* WinTV-QuadHD (DVB) Tuner Pair 2 (PCIe, IR, half height,
1292 DVB-T/T2/C, DVB-T/T2/C */
1293 break;
1294 case 165100:
1295 /*
1296 * WinTV-QuadHD (ATSC) Tuner Pair 1 (PCIe, IR, half height,
1297 * ATSC, ATSC
1298 */
1299 break;
1300 case 165101:
1301 /*
1302 * WinTV-QuadHD (DVB) Tuner Pair 2 (PCIe, IR, half height,
1303 * ATSC, ATSC
1304 */
1305 break;
1306 default:
1307 printk(KERN_WARNING "%s: warning: "
1308 "unknown hauppauge model #%d\n",
1309 dev->name, tv.model);
1310 break;
1311 }
1312
1313 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
1314 dev->name, tv.model);
1315 }
1316
1317 /* Some TBS cards require initing a chip using a bitbanged SPI attached
1318 to the cx23885 gpio's. If this chip doesn't get init'ed the demod
1319 doesn't respond to any command. */
1320 static void tbs_card_init(struct cx23885_dev *dev)
1321 {
1322 int i;
1323 const u8 buf[] = {
1324 0xe0, 0x06, 0x66, 0x33, 0x65,
1325 0x01, 0x17, 0x06, 0xde};
1326
1327 switch (dev->board) {
1328 case CX23885_BOARD_TBS_6980:
1329 case CX23885_BOARD_TBS_6981:
1330 cx_set(GP0_IO, 0x00070007);
1331 usleep_range(1000, 10000);
1332 cx_clear(GP0_IO, 2);
1333 usleep_range(1000, 10000);
1334 for (i = 0; i < 9 * 8; i++) {
1335 cx_clear(GP0_IO, 7);
1336 usleep_range(1000, 10000);
1337 cx_set(GP0_IO,
1338 ((buf[i >> 3] >> (7 - (i & 7))) & 1) | 4);
1339 usleep_range(1000, 10000);
1340 }
1341 cx_set(GP0_IO, 7);
1342 break;
1343 }
1344 }
1345
1346 int cx23885_tuner_callback(void *priv, int component, int command, int arg)
1347 {
1348 struct cx23885_tsport *port = priv;
1349 struct cx23885_dev *dev = port->dev;
1350 u32 bitmask = 0;
1351
1352 if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH))
1353 return 0;
1354
1355 if (command != 0) {
1356 printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
1357 __func__, command);
1358 return -EINVAL;
1359 }
1360
1361 switch (dev->board) {
1362 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1363 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1364 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1365 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1366 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
1367 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1368 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1369 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1370 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1371 /* Tuner Reset Command */
1372 bitmask = 0x04;
1373 break;
1374 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1375 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1376 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
1377 /* Two identical tuners on two different i2c buses,
1378 * we need to reset the correct gpio. */
1379 if (port->nr == 1)
1380 bitmask = 0x01;
1381 else if (port->nr == 2)
1382 bitmask = 0x04;
1383 break;
1384 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1385 /* Tuner Reset Command */
1386 bitmask = 0x02;
1387 break;
1388 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1389 altera_ci_tuner_reset(dev, port->nr);
1390 break;
1391 case CX23885_BOARD_AVERMEDIA_HC81R:
1392 /* XC3028L Reset Command */
1393 bitmask = 1 << 2;
1394 break;
1395 }
1396
1397 if (bitmask) {
1398 /* Drive the tuner into reset and back out */
1399 cx_clear(GP0_IO, bitmask);
1400 mdelay(200);
1401 cx_set(GP0_IO, bitmask);
1402 }
1403
1404 return 0;
1405 }
1406
1407 void cx23885_gpio_setup(struct cx23885_dev *dev)
1408 {
1409 switch (dev->board) {
1410 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1411 /* GPIO-0 cx24227 demodulator reset */
1412 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1413 break;
1414 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1415 /* GPIO-0 cx24227 demodulator */
1416 /* GPIO-2 xc3028 tuner */
1417
1418 /* Put the parts into reset */
1419 cx_set(GP0_IO, 0x00050000);
1420 cx_clear(GP0_IO, 0x00000005);
1421 msleep(5);
1422
1423 /* Bring the parts out of reset */
1424 cx_set(GP0_IO, 0x00050005);
1425 break;
1426 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1427 /* GPIO-0 cx24227 demodulator reset */
1428 /* GPIO-2 xc5000 tuner reset */
1429 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
1430 break;
1431 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1432 /* GPIO-0 656_CLK */
1433 /* GPIO-1 656_D0 */
1434 /* GPIO-2 8295A Reset */
1435 /* GPIO-3-10 cx23417 data0-7 */
1436 /* GPIO-11-14 cx23417 addr0-3 */
1437 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1438 /* GPIO-19 IR_RX */
1439
1440 /* CX23417 GPIO's */
1441 /* EIO15 Zilog Reset */
1442 /* EIO14 S5H1409/CX24227 Reset */
1443 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
1444
1445 /* Put the demod into reset and protect the eeprom */
1446 mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
1447 mdelay(100);
1448
1449 /* Bring the demod and blaster out of reset */
1450 mc417_gpio_set(dev, GPIO_15 | GPIO_14);
1451 mdelay(100);
1452
1453 /* Force the TDA8295A into reset and back */
1454 cx23885_gpio_enable(dev, GPIO_2, 1);
1455 cx23885_gpio_set(dev, GPIO_2);
1456 mdelay(20);
1457 cx23885_gpio_clear(dev, GPIO_2);
1458 mdelay(20);
1459 cx23885_gpio_set(dev, GPIO_2);
1460 mdelay(20);
1461 break;
1462 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1463 /* GPIO-0 tda10048 demodulator reset */
1464 /* GPIO-2 tda18271 tuner reset */
1465
1466 /* Put the parts into reset and back */
1467 cx_set(GP0_IO, 0x00050000);
1468 mdelay(20);
1469 cx_clear(GP0_IO, 0x00000005);
1470 mdelay(20);
1471 cx_set(GP0_IO, 0x00050005);
1472 break;
1473 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1474 /* GPIO-0 TDA10048 demodulator reset */
1475 /* GPIO-2 TDA8295A Reset */
1476 /* GPIO-3-10 cx23417 data0-7 */
1477 /* GPIO-11-14 cx23417 addr0-3 */
1478 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1479
1480 /* The following GPIO's are on the interna AVCore (cx25840) */
1481 /* GPIO-19 IR_RX */
1482 /* GPIO-20 IR_TX 416/DVBT Select */
1483 /* GPIO-21 IIS DAT */
1484 /* GPIO-22 IIS WCLK */
1485 /* GPIO-23 IIS BCLK */
1486
1487 /* Put the parts into reset and back */
1488 cx_set(GP0_IO, 0x00050000);
1489 mdelay(20);
1490 cx_clear(GP0_IO, 0x00000005);
1491 mdelay(20);
1492 cx_set(GP0_IO, 0x00050005);
1493 break;
1494 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1495 /* GPIO-0 Dibcom7000p demodulator reset */
1496 /* GPIO-2 xc3028L tuner reset */
1497 /* GPIO-13 LED */
1498
1499 /* Put the parts into reset and back */
1500 cx_set(GP0_IO, 0x00050000);
1501 mdelay(20);
1502 cx_clear(GP0_IO, 0x00000005);
1503 mdelay(20);
1504 cx_set(GP0_IO, 0x00050005);
1505 break;
1506 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1507 /* GPIO-0 xc5000 tuner reset i2c bus 0 */
1508 /* GPIO-1 s5h1409 demod reset i2c bus 0 */
1509 /* GPIO-2 xc5000 tuner reset i2c bus 1 */
1510 /* GPIO-3 s5h1409 demod reset i2c bus 0 */
1511
1512 /* Put the parts into reset and back */
1513 cx_set(GP0_IO, 0x000f0000);
1514 mdelay(20);
1515 cx_clear(GP0_IO, 0x0000000f);
1516 mdelay(20);
1517 cx_set(GP0_IO, 0x000f000f);
1518 break;
1519 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1520 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
1521 /* GPIO-0 portb xc3028 reset */
1522 /* GPIO-1 portb zl10353 reset */
1523 /* GPIO-2 portc xc3028 reset */
1524 /* GPIO-3 portc zl10353 reset */
1525
1526 /* Put the parts into reset and back */
1527 cx_set(GP0_IO, 0x000f0000);
1528 mdelay(20);
1529 cx_clear(GP0_IO, 0x0000000f);
1530 mdelay(20);
1531 cx_set(GP0_IO, 0x000f000f);
1532 break;
1533 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1534 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
1535 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1536 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1537 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1538 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1539 /* GPIO-2 xc3028 tuner reset */
1540
1541 /* The following GPIO's are on the internal AVCore (cx25840) */
1542 /* GPIO-? zl10353 demod reset */
1543
1544 /* Put the parts into reset and back */
1545 cx_set(GP0_IO, 0x00040000);
1546 mdelay(20);
1547 cx_clear(GP0_IO, 0x00000004);
1548 mdelay(20);
1549 cx_set(GP0_IO, 0x00040004);
1550 break;
1551 case CX23885_BOARD_TBS_6920:
1552 case CX23885_BOARD_TBS_6980:
1553 case CX23885_BOARD_TBS_6981:
1554 case CX23885_BOARD_PROF_8000:
1555 cx_write(MC417_CTL, 0x00000036);
1556 cx_write(MC417_OEN, 0x00001000);
1557 cx_set(MC417_RWD, 0x00000002);
1558 mdelay(200);
1559 cx_clear(MC417_RWD, 0x00000800);
1560 mdelay(200);
1561 cx_set(MC417_RWD, 0x00000800);
1562 mdelay(200);
1563 break;
1564 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1565 /* GPIO-0 INTA from CiMax1
1566 GPIO-1 INTB from CiMax2
1567 GPIO-2 reset chips
1568 GPIO-3 to GPIO-10 data/addr for CA
1569 GPIO-11 ~CS0 to CiMax1
1570 GPIO-12 ~CS1 to CiMax2
1571 GPIO-13 ADL0 load LSB addr
1572 GPIO-14 ADL1 load MSB addr
1573 GPIO-15 ~RDY from CiMax
1574 GPIO-17 ~RD to CiMax
1575 GPIO-18 ~WR to CiMax
1576 */
1577 cx_set(GP0_IO, 0x00040000); /* GPIO as out */
1578 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
1579 cx_clear(GP0_IO, 0x00030004);
1580 mdelay(100);/* reset delay */
1581 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
1582 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
1583 /* GPIO-15 IN as ~ACK, rest as OUT */
1584 cx_write(MC417_OEN, 0x00001000);
1585 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
1586 cx_write(MC417_RWD, 0x0000c300);
1587 /* enable irq */
1588 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1589 break;
1590 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1591 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1592 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1593 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1594 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1595 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
1596 /* GPIO-6 I2C Gate which can isolate the demod from the bus */
1597 /* GPIO-9 Demod reset */
1598
1599 /* Put the parts into reset and back */
1600 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
1601 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
1602 cx23885_gpio_clear(dev, GPIO_9);
1603 mdelay(20);
1604 cx23885_gpio_set(dev, GPIO_9);
1605 break;
1606 case CX23885_BOARD_MYGICA_X8506:
1607 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1608 case CX23885_BOARD_MYGICA_X8507:
1609 /* GPIO-0 (0)Analog / (1)Digital TV */
1610 /* GPIO-1 reset XC5000 */
1611 /* GPIO-2 demod reset */
1612 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
1613 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
1614 mdelay(100);
1615 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
1616 mdelay(100);
1617 break;
1618 case CX23885_BOARD_MYGICA_X8558PRO:
1619 /* GPIO-0 reset first ATBM8830 */
1620 /* GPIO-1 reset second ATBM8830 */
1621 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
1622 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
1623 mdelay(100);
1624 cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
1625 mdelay(100);
1626 break;
1627 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1628 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1629 /* GPIO-0 656_CLK */
1630 /* GPIO-1 656_D0 */
1631 /* GPIO-2 Wake# */
1632 /* GPIO-3-10 cx23417 data0-7 */
1633 /* GPIO-11-14 cx23417 addr0-3 */
1634 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1635 /* GPIO-19 IR_RX */
1636 /* GPIO-20 C_IR_TX */
1637 /* GPIO-21 I2S DAT */
1638 /* GPIO-22 I2S WCLK */
1639 /* GPIO-23 I2S BCLK */
1640 /* ALT GPIO: EXP GPIO LATCH */
1641
1642 /* CX23417 GPIO's */
1643 /* GPIO-14 S5H1411/CX24228 Reset */
1644 /* GPIO-13 EEPROM write protect */
1645 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
1646
1647 /* Put the demod into reset and protect the eeprom */
1648 mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
1649 mdelay(100);
1650
1651 /* Bring the demod out of reset */
1652 mc417_gpio_set(dev, GPIO_14);
1653 mdelay(100);
1654
1655 /* CX24228 GPIO */
1656 /* Connected to IF / Mux */
1657 break;
1658 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1659 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1660 break;
1661 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1662 /* GPIO-0 ~INT in
1663 GPIO-1 TMS out
1664 GPIO-2 ~reset chips out
1665 GPIO-3 to GPIO-10 data/addr for CA in/out
1666 GPIO-11 ~CS out
1667 GPIO-12 ADDR out
1668 GPIO-13 ~WR out
1669 GPIO-14 ~RD out
1670 GPIO-15 ~RDY in
1671 GPIO-16 TCK out
1672 GPIO-17 TDO in
1673 GPIO-18 TDI out
1674 */
1675 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
1676 /* GPIO-0 as INT, reset & TMS low */
1677 cx_clear(GP0_IO, 0x00010006);
1678 mdelay(100);/* reset delay */
1679 cx_set(GP0_IO, 0x00000004); /* reset high */
1680 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
1681 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
1682 cx_write(MC417_OEN, 0x00005000);
1683 /* ~RD, ~WR high; ADDR low; ~CS high */
1684 cx_write(MC417_RWD, 0x00000d00);
1685 /* enable irq */
1686 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1687 break;
1688 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1689 case CX23885_BOARD_HAUPPAUGE_STARBURST:
1690 /* GPIO-8 tda10071 demod reset */
1691 /* GPIO-9 si2165 demod reset (only HVR4400/HVR5500)*/
1692
1693 /* Put the parts into reset and back */
1694 cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1);
1695
1696 cx23885_gpio_clear(dev, GPIO_8 | GPIO_9);
1697 mdelay(100);
1698 cx23885_gpio_set(dev, GPIO_8 | GPIO_9);
1699 mdelay(100);
1700
1701 break;
1702 case CX23885_BOARD_AVERMEDIA_HC81R:
1703 cx_clear(MC417_CTL, 1);
1704 /* GPIO-0,1,2 setup direction as output */
1705 cx_set(GP0_IO, 0x00070000);
1706 mdelay(10);
1707 /* AF9013 demod reset */
1708 cx_set(GP0_IO, 0x00010001);
1709 mdelay(10);
1710 cx_clear(GP0_IO, 0x00010001);
1711 mdelay(10);
1712 cx_set(GP0_IO, 0x00010001);
1713 mdelay(10);
1714 /* demod tune? */
1715 cx_clear(GP0_IO, 0x00030003);
1716 mdelay(10);
1717 cx_set(GP0_IO, 0x00020002);
1718 mdelay(10);
1719 cx_set(GP0_IO, 0x00010001);
1720 mdelay(10);
1721 cx_clear(GP0_IO, 0x00020002);
1722 /* XC3028L tuner reset */
1723 cx_set(GP0_IO, 0x00040004);
1724 cx_clear(GP0_IO, 0x00040004);
1725 cx_set(GP0_IO, 0x00040004);
1726 mdelay(60);
1727 break;
1728 case CX23885_BOARD_DVBSKY_T9580:
1729 case CX23885_BOARD_DVBSKY_S952:
1730 case CX23885_BOARD_DVBSKY_T982:
1731 /* enable GPIO3-18 pins */
1732 cx_write(MC417_CTL, 0x00000037);
1733 cx23885_gpio_enable(dev, GPIO_2 | GPIO_11, 1);
1734 cx23885_gpio_clear(dev, GPIO_2 | GPIO_11);
1735 mdelay(100);
1736 cx23885_gpio_set(dev, GPIO_2 | GPIO_11);
1737 break;
1738 case CX23885_BOARD_DVBSKY_T980C:
1739 case CX23885_BOARD_DVBSKY_S950C:
1740 case CX23885_BOARD_TT_CT2_4500_CI:
1741 /*
1742 * GPIO-0 INTA from CiMax, input
1743 * GPIO-1 reset CiMax, output, high active
1744 * GPIO-2 reset demod, output, low active
1745 * GPIO-3 to GPIO-10 data/addr for CAM
1746 * GPIO-11 ~CS0 to CiMax1
1747 * GPIO-12 ~CS1 to CiMax2
1748 * GPIO-13 ADL0 load LSB addr
1749 * GPIO-14 ADL1 load MSB addr
1750 * GPIO-15 ~RDY from CiMax
1751 * GPIO-17 ~RD to CiMax
1752 * GPIO-18 ~WR to CiMax
1753 */
1754
1755 cx_set(GP0_IO, 0x00060002); /* GPIO 1/2 as output */
1756 cx_clear(GP0_IO, 0x00010004); /* GPIO 0 as input */
1757 mdelay(100); /* reset delay */
1758 cx_set(GP0_IO, 0x00060004); /* GPIO as out, reset high */
1759 cx_clear(GP0_IO, 0x00010002);
1760 cx_write(MC417_CTL, 0x00000037); /* enable GPIO3-18 pins */
1761
1762 /* GPIO-15 IN as ~ACK, rest as OUT */
1763 cx_write(MC417_OEN, 0x00001000);
1764
1765 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
1766 cx_write(MC417_RWD, 0x0000c300);
1767
1768 /* enable irq */
1769 cx_write(GPIO_ISM, 0x00000000); /* INTERRUPTS active low */
1770 break;
1771 case CX23885_BOARD_DVBSKY_S950:
1772 cx23885_gpio_enable(dev, GPIO_2, 1);
1773 cx23885_gpio_clear(dev, GPIO_2);
1774 msleep(100);
1775 cx23885_gpio_set(dev, GPIO_2);
1776 break;
1777 case CX23885_BOARD_HAUPPAUGE_HVR5525:
1778 case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
1779 case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
1780 /*
1781 * HVR5525 GPIO Details:
1782 * GPIO-00 IR_WIDE
1783 * GPIO-02 wake#
1784 * GPIO-03 VAUX Pres.
1785 * GPIO-07 PROG#
1786 * GPIO-08 SAT_RESN
1787 * GPIO-09 TER_RESN
1788 * GPIO-10 B2_SENSE
1789 * GPIO-11 B1_SENSE
1790 * GPIO-15 IR_LED_STATUS
1791 * GPIO-19 IR_NARROW
1792 * GPIO-20 Blauster1
1793 * ALTGPIO VAUX_SWITCH
1794 * AUX_PLL_CLK : Blaster2
1795 */
1796 /* Put the parts into reset and back */
1797 cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1);
1798 cx23885_gpio_clear(dev, GPIO_8 | GPIO_9);
1799 msleep(100);
1800 cx23885_gpio_set(dev, GPIO_8 | GPIO_9);
1801 msleep(100);
1802 break;
1803 case CX23885_BOARD_VIEWCAST_260E:
1804 case CX23885_BOARD_VIEWCAST_460E:
1805 /* For documentation purposes, it's worth noting that this
1806 * card does not have any GPIO's connected to subcomponents.
1807 */
1808 break;
1809 }
1810 }
1811
1812 int cx23885_ir_init(struct cx23885_dev *dev)
1813 {
1814 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
1815 {
1816 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1817 .pin = CX23885_PIN_IR_RX_GPIO19,
1818 .function = CX23885_PAD_IR_RX,
1819 .value = 0,
1820 .strength = CX25840_PIN_DRIVE_MEDIUM,
1821 }, {
1822 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
1823 .pin = CX23885_PIN_IR_TX_GPIO20,
1824 .function = CX23885_PAD_IR_TX,
1825 .value = 0,
1826 .strength = CX25840_PIN_DRIVE_MEDIUM,
1827 }
1828 };
1829 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
1830
1831 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
1832 {
1833 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1834 .pin = CX23885_PIN_IR_RX_GPIO19,
1835 .function = CX23885_PAD_IR_RX,
1836 .value = 0,
1837 .strength = CX25840_PIN_DRIVE_MEDIUM,
1838 }
1839 };
1840 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
1841
1842 struct v4l2_subdev_ir_parameters params;
1843 int ret = 0;
1844 switch (dev->board) {
1845 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1846 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1847 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1848 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1849 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1850 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1851 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1852 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1853 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1854 case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
1855 case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
1856 /* FIXME: Implement me */
1857 break;
1858 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1859 ret = cx23888_ir_probe(dev);
1860 if (ret)
1861 break;
1862 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1863 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1864 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1865 break;
1866 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1867 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1868 ret = cx23888_ir_probe(dev);
1869 if (ret)
1870 break;
1871 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1872 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1873 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1874 /*
1875 * For these boards we need to invert the Tx output via the
1876 * IR controller to have the LED off while idle
1877 */
1878 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
1879 params.enable = false;
1880 params.shutdown = false;
1881 params.invert_level = true;
1882 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1883 params.shutdown = true;
1884 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1885 break;
1886 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1887 case CX23885_BOARD_TEVII_S470:
1888 case CX23885_BOARD_MYGICA_X8507:
1889 case CX23885_BOARD_TBS_6980:
1890 case CX23885_BOARD_TBS_6981:
1891 case CX23885_BOARD_DVBSKY_T9580:
1892 case CX23885_BOARD_DVBSKY_T980C:
1893 case CX23885_BOARD_DVBSKY_S950C:
1894 case CX23885_BOARD_TT_CT2_4500_CI:
1895 case CX23885_BOARD_DVBSKY_S950:
1896 case CX23885_BOARD_DVBSKY_S952:
1897 case CX23885_BOARD_DVBSKY_T982:
1898 if (!enable_885_ir)
1899 break;
1900 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1901 if (dev->sd_ir == NULL) {
1902 ret = -ENODEV;
1903 break;
1904 }
1905 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1906 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1907 break;
1908 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1909 if (!enable_885_ir)
1910 break;
1911 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1912 if (dev->sd_ir == NULL) {
1913 ret = -ENODEV;
1914 break;
1915 }
1916 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1917 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1918 break;
1919 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1920 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
1921 request_module("ir-kbd-i2c");
1922 break;
1923 }
1924
1925 return ret;
1926 }
1927
1928 void cx23885_ir_fini(struct cx23885_dev *dev)
1929 {
1930 switch (dev->board) {
1931 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1932 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1933 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1934 cx23885_irq_remove(dev, PCI_MSK_IR);
1935 cx23888_ir_remove(dev);
1936 dev->sd_ir = NULL;
1937 break;
1938 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1939 case CX23885_BOARD_TEVII_S470:
1940 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1941 case CX23885_BOARD_MYGICA_X8507:
1942 case CX23885_BOARD_TBS_6980:
1943 case CX23885_BOARD_TBS_6981:
1944 case CX23885_BOARD_DVBSKY_T9580:
1945 case CX23885_BOARD_DVBSKY_T980C:
1946 case CX23885_BOARD_DVBSKY_S950C:
1947 case CX23885_BOARD_TT_CT2_4500_CI:
1948 case CX23885_BOARD_DVBSKY_S950:
1949 case CX23885_BOARD_DVBSKY_S952:
1950 case CX23885_BOARD_DVBSKY_T982:
1951 cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
1952 /* sd_ir is a duplicate pointer to the AV Core, just clear it */
1953 dev->sd_ir = NULL;
1954 break;
1955 }
1956 }
1957
1958 static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
1959 {
1960 int data;
1961 int tdo = 0;
1962 struct cx23885_dev *dev = (struct cx23885_dev *)device;
1963 /*TMS*/
1964 data = ((cx_read(GP0_IO)) & (~0x00000002));
1965 data |= (tms ? 0x00020002 : 0x00020000);
1966 cx_write(GP0_IO, data);
1967
1968 /*TDI*/
1969 data = ((cx_read(MC417_RWD)) & (~0x0000a000));
1970 data |= (tdi ? 0x00008000 : 0);
1971 cx_write(MC417_RWD, data);
1972 if (read_tdo)
1973 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
1974
1975 cx_write(MC417_RWD, data | 0x00002000);
1976 udelay(1);
1977 /*TCK*/
1978 cx_write(MC417_RWD, data);
1979
1980 return tdo;
1981 }
1982
1983 void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
1984 {
1985 switch (dev->board) {
1986 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1987 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1988 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1989 if (dev->sd_ir)
1990 cx23885_irq_add_enable(dev, PCI_MSK_IR);
1991 break;
1992 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1993 case CX23885_BOARD_TEVII_S470:
1994 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1995 case CX23885_BOARD_MYGICA_X8507:
1996 case CX23885_BOARD_TBS_6980:
1997 case CX23885_BOARD_TBS_6981:
1998 case CX23885_BOARD_DVBSKY_T9580:
1999 case CX23885_BOARD_DVBSKY_T980C:
2000 case CX23885_BOARD_DVBSKY_S950C:
2001 case CX23885_BOARD_TT_CT2_4500_CI:
2002 case CX23885_BOARD_DVBSKY_S950:
2003 case CX23885_BOARD_DVBSKY_S952:
2004 case CX23885_BOARD_DVBSKY_T982:
2005 if (dev->sd_ir)
2006 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
2007 break;
2008 }
2009 }
2010
2011 void cx23885_card_setup(struct cx23885_dev *dev)
2012 {
2013 struct cx23885_tsport *ts1 = &dev->ts1;
2014 struct cx23885_tsport *ts2 = &dev->ts2;
2015
2016 static u8 eeprom[256];
2017
2018 if (dev->i2c_bus[0].i2c_rc == 0) {
2019 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
2020 tveeprom_read(&dev->i2c_bus[0].i2c_client,
2021 eeprom, sizeof(eeprom));
2022 }
2023
2024 switch (dev->board) {
2025 case CX23885_BOARD_HAUPPAUGE_HVR1250:
2026 if (dev->i2c_bus[0].i2c_rc == 0) {
2027 if (eeprom[0x80] != 0x84)
2028 hauppauge_eeprom(dev, eeprom+0xc0);
2029 else
2030 hauppauge_eeprom(dev, eeprom+0x80);
2031 }
2032 break;
2033 case CX23885_BOARD_HAUPPAUGE_HVR1500:
2034 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
2035 case CX23885_BOARD_HAUPPAUGE_HVR1400:
2036 if (dev->i2c_bus[0].i2c_rc == 0)
2037 hauppauge_eeprom(dev, eeprom+0x80);
2038 break;
2039 case CX23885_BOARD_HAUPPAUGE_HVR1800:
2040 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
2041 case CX23885_BOARD_HAUPPAUGE_HVR1200:
2042 case CX23885_BOARD_HAUPPAUGE_HVR1700:
2043 case CX23885_BOARD_HAUPPAUGE_HVR1270:
2044 case CX23885_BOARD_HAUPPAUGE_HVR1275:
2045 case CX23885_BOARD_HAUPPAUGE_HVR1255:
2046 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
2047 case CX23885_BOARD_HAUPPAUGE_HVR1210:
2048 case CX23885_BOARD_HAUPPAUGE_HVR1850:
2049 case CX23885_BOARD_HAUPPAUGE_HVR1290:
2050 case CX23885_BOARD_HAUPPAUGE_HVR4400:
2051 case CX23885_BOARD_HAUPPAUGE_STARBURST:
2052 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
2053 case CX23885_BOARD_HAUPPAUGE_HVR5525:
2054 case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
2055 case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
2056 if (dev->i2c_bus[0].i2c_rc == 0)
2057 hauppauge_eeprom(dev, eeprom+0xc0);
2058 break;
2059 case CX23885_BOARD_VIEWCAST_260E:
2060 case CX23885_BOARD_VIEWCAST_460E:
2061 dev->i2c_bus[1].i2c_client.addr = 0xa0 >> 1;
2062 tveeprom_read(&dev->i2c_bus[1].i2c_client,
2063 eeprom, sizeof(eeprom));
2064 if (dev->i2c_bus[0].i2c_rc == 0)
2065 viewcast_eeprom(dev, eeprom);
2066 break;
2067 }
2068
2069 switch (dev->board) {
2070 case CX23885_BOARD_AVERMEDIA_HC81R:
2071 /* Defaults for VID B */
2072 ts1->gen_ctrl_val = 0x4; /* Parallel */
2073 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2074 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2075 /* Defaults for VID C */
2076 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
2077 ts2->gen_ctrl_val = 0x10e;
2078 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2079 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2080 break;
2081 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
2082 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
2083 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
2084 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2085 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2086 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2087 /* break omitted intentionally */
2088 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
2089 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2090 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2091 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2092 break;
2093 case CX23885_BOARD_HAUPPAUGE_HVR1850:
2094 case CX23885_BOARD_HAUPPAUGE_HVR1800:
2095 /* Defaults for VID B - Analog encoder */
2096 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
2097 ts1->gen_ctrl_val = 0x10e;
2098 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2099 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2100
2101 /* APB_TSVALERR_POL (active low)*/
2102 ts1->vld_misc_val = 0x2000;
2103 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
2104 cx_write(0x130184, 0xc);
2105
2106 /* Defaults for VID C */
2107 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2108 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2109 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2110 break;
2111 case CX23885_BOARD_TBS_6920:
2112 ts1->gen_ctrl_val = 0x4; /* Parallel */
2113 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2114 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2115 break;
2116 case CX23885_BOARD_TEVII_S470:
2117 case CX23885_BOARD_TEVII_S471:
2118 case CX23885_BOARD_DVBWORLD_2005:
2119 case CX23885_BOARD_PROF_8000:
2120 case CX23885_BOARD_DVBSKY_T980C:
2121 case CX23885_BOARD_DVBSKY_S950C:
2122 case CX23885_BOARD_TT_CT2_4500_CI:
2123 case CX23885_BOARD_DVBSKY_S950:
2124 ts1->gen_ctrl_val = 0x5; /* Parallel */
2125 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2126 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2127 break;
2128 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
2129 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
2130 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
2131 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2132 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2133 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2134 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2135 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2136 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2137 break;
2138 case CX23885_BOARD_TBS_6980:
2139 case CX23885_BOARD_TBS_6981:
2140 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2141 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2142 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2143 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2144 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2145 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2146 tbs_card_init(dev);
2147 break;
2148 case CX23885_BOARD_MYGICA_X8506:
2149 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
2150 case CX23885_BOARD_MYGICA_X8507:
2151 ts1->gen_ctrl_val = 0x5; /* Parallel */
2152 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2153 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2154 break;
2155 case CX23885_BOARD_MYGICA_X8558PRO:
2156 ts1->gen_ctrl_val = 0x5; /* Parallel */
2157 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2158 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2159 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2160 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2161 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2162 break;
2163 case CX23885_BOARD_HAUPPAUGE_HVR4400:
2164 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2165 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2166 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2167 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2168 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2169 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2170 break;
2171 case CX23885_BOARD_HAUPPAUGE_STARBURST:
2172 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2173 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2174 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2175 break;
2176 case CX23885_BOARD_DVBSKY_T9580:
2177 case CX23885_BOARD_DVBSKY_T982:
2178 ts1->gen_ctrl_val = 0x5; /* Parallel */
2179 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2180 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2181 ts2->gen_ctrl_val = 0x8; /* Serial bus */
2182 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2183 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2184 break;
2185 case CX23885_BOARD_DVBSKY_S952:
2186 ts1->gen_ctrl_val = 0x5; /* Parallel */
2187 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2188 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2189 ts2->gen_ctrl_val = 0xe; /* Serial bus */
2190 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2191 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2192 break;
2193 case CX23885_BOARD_HAUPPAUGE_HVR5525:
2194 ts1->gen_ctrl_val = 0x5; /* Parallel */
2195 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2196 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2197 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2198 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2199 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2200 break;
2201 case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
2202 case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
2203 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2204 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2205 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2206 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2207 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2208 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2209 break;
2210 case CX23885_BOARD_HAUPPAUGE_HVR1250:
2211 case CX23885_BOARD_HAUPPAUGE_HVR1500:
2212 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
2213 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
2214 case CX23885_BOARD_HAUPPAUGE_HVR1200:
2215 case CX23885_BOARD_HAUPPAUGE_HVR1700:
2216 case CX23885_BOARD_HAUPPAUGE_HVR1400:
2217 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
2218 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
2219 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
2220 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
2221 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
2222 case CX23885_BOARD_HAUPPAUGE_HVR1270:
2223 case CX23885_BOARD_HAUPPAUGE_HVR1275:
2224 case CX23885_BOARD_HAUPPAUGE_HVR1255:
2225 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
2226 case CX23885_BOARD_HAUPPAUGE_HVR1210:
2227 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
2228 case CX23885_BOARD_HAUPPAUGE_HVR1290:
2229 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
2230 default:
2231 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2232 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2233 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2234 }
2235
2236 /* Certain boards support analog, or require the avcore to be
2237 * loaded, ensure this happens.
2238 */
2239 switch (dev->board) {
2240 case CX23885_BOARD_TEVII_S470:
2241 /* Currently only enabled for the integrated IR controller */
2242 if (!enable_885_ir)
2243 break;
2244 case CX23885_BOARD_HAUPPAUGE_HVR1250:
2245 case CX23885_BOARD_HAUPPAUGE_HVR1800:
2246 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
2247 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
2248 case CX23885_BOARD_HAUPPAUGE_HVR1700:
2249 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
2250 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
2251 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
2252 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
2253 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
2254 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
2255 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
2256 case CX23885_BOARD_HAUPPAUGE_HVR1255:
2257 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
2258 case CX23885_BOARD_HAUPPAUGE_HVR1270:
2259 case CX23885_BOARD_HAUPPAUGE_HVR1850:
2260 case CX23885_BOARD_MYGICA_X8506:
2261 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
2262 case CX23885_BOARD_HAUPPAUGE_HVR1290:
2263 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
2264 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
2265 case CX23885_BOARD_HAUPPAUGE_HVR1500:
2266 case CX23885_BOARD_MPX885:
2267 case CX23885_BOARD_MYGICA_X8507:
2268 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
2269 case CX23885_BOARD_AVERMEDIA_HC81R:
2270 case CX23885_BOARD_TBS_6980:
2271 case CX23885_BOARD_TBS_6981:
2272 case CX23885_BOARD_DVBSKY_T9580:
2273 case CX23885_BOARD_DVBSKY_T980C:
2274 case CX23885_BOARD_DVBSKY_S950C:
2275 case CX23885_BOARD_TT_CT2_4500_CI:
2276 case CX23885_BOARD_DVBSKY_S950:
2277 case CX23885_BOARD_DVBSKY_S952:
2278 case CX23885_BOARD_DVBSKY_T982:
2279 case CX23885_BOARD_VIEWCAST_260E:
2280 case CX23885_BOARD_VIEWCAST_460E:
2281 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
2282 &dev->i2c_bus[2].i2c_adap,
2283 "cx25840", 0x88 >> 1, NULL);
2284 if (dev->sd_cx25840) {
2285 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
2286 v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
2287 }
2288 break;
2289 }
2290
2291 switch (dev->board) {
2292 case CX23885_BOARD_VIEWCAST_260E:
2293 v4l2_i2c_new_subdev(&dev->v4l2_dev,
2294 &dev->i2c_bus[0].i2c_adap,
2295 "cs3308", 0x82 >> 1, NULL);
2296 break;
2297 case CX23885_BOARD_VIEWCAST_460E:
2298 /* This cs3308 controls the audio from the breakout cable */
2299 v4l2_i2c_new_subdev(&dev->v4l2_dev,
2300 &dev->i2c_bus[0].i2c_adap,
2301 "cs3308", 0x80 >> 1, NULL);
2302 /* This cs3308 controls the audio from the onboard header */
2303 v4l2_i2c_new_subdev(&dev->v4l2_dev,
2304 &dev->i2c_bus[0].i2c_adap,
2305 "cs3308", 0x82 >> 1, NULL);
2306 break;
2307 }
2308
2309 /* AUX-PLL 27MHz CLK */
2310 switch (dev->board) {
2311 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
2312 netup_initialize(dev);
2313 break;
2314 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
2315 int ret;
2316 const struct firmware *fw;
2317 const char *filename = "dvb-netup-altera-01.fw";
2318 char *action = "configure";
2319 static struct netup_card_info cinfo;
2320 struct altera_config netup_config = {
2321 .dev = dev,
2322 .action = action,
2323 .jtag_io = netup_jtag_io,
2324 };
2325
2326 netup_initialize(dev);
2327
2328 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
2329 if (netup_card_rev)
2330 cinfo.rev = netup_card_rev;
2331
2332 switch (cinfo.rev) {
2333 case 0x4:
2334 filename = "dvb-netup-altera-04.fw";
2335 break;
2336 default:
2337 filename = "dvb-netup-altera-01.fw";
2338 break;
2339 }
2340 printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n",
2341 cinfo.rev, filename);
2342
2343 ret = request_firmware(&fw, filename, &dev->pci->dev);
2344 if (ret != 0)
2345 printk(KERN_ERR "did not find the firmware file. (%s) "
2346 "Please see linux/Documentation/dvb/ for more details "
2347 "on firmware-problems.", filename);
2348 else
2349 altera_init(&netup_config, fw);
2350
2351 release_firmware(fw);
2352 break;
2353 }
2354 }
2355 }
Linux with added FPC-III support