hwrng: core - Don't use a stack buffer in add_early_randomness()
[linux/fpc-iii.git] / drivers / misc / cxl / main.c
blobd9be23b24aa3b88dce63a8c3f1bf38f9c66ca5ef
1 /*
2 * Copyright 2014 IBM Corp.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
10 #include <linux/spinlock.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/device.h>
14 #include <linux/mutex.h>
15 #include <linux/init.h>
16 #include <linux/list.h>
17 #include <linux/mm.h>
18 #include <linux/of.h>
19 #include <linux/slab.h>
20 #include <linux/idr.h>
21 #include <linux/pci.h>
22 #include <asm/cputable.h>
23 #include <misc/cxl-base.h>
25 #include "cxl.h"
26 #include "trace.h"
28 static DEFINE_SPINLOCK(adapter_idr_lock);
29 static DEFINE_IDR(cxl_adapter_idr);
31 uint cxl_verbose;
32 module_param_named(verbose, cxl_verbose, uint, 0600);
33 MODULE_PARM_DESC(verbose, "Enable verbose dmesg output");
35 const struct cxl_backend_ops *cxl_ops;
37 int cxl_afu_slbia(struct cxl_afu *afu)
39 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
41 pr_devel("cxl_afu_slbia issuing SLBIA command\n");
42 cxl_p2n_write(afu, CXL_SLBIA_An, CXL_TLB_SLB_IQ_ALL);
43 while (cxl_p2n_read(afu, CXL_SLBIA_An) & CXL_TLB_SLB_P) {
44 if (time_after_eq(jiffies, timeout)) {
45 dev_warn(&afu->dev, "WARNING: CXL AFU SLBIA timed out!\n");
46 return -EBUSY;
48 /* If the adapter has gone down, we can assume that we
49 * will PERST it and that will invalidate everything.
51 if (!cxl_ops->link_ok(afu->adapter, afu))
52 return -EIO;
53 cpu_relax();
55 return 0;
58 static inline void _cxl_slbia(struct cxl_context *ctx, struct mm_struct *mm)
60 struct task_struct *task;
61 unsigned long flags;
62 if (!(task = get_pid_task(ctx->pid, PIDTYPE_PID))) {
63 pr_devel("%s unable to get task %i\n",
64 __func__, pid_nr(ctx->pid));
65 return;
68 if (task->mm != mm)
69 goto out_put;
71 pr_devel("%s matched mm - card: %i afu: %i pe: %i\n", __func__,
72 ctx->afu->adapter->adapter_num, ctx->afu->slice, ctx->pe);
74 spin_lock_irqsave(&ctx->sste_lock, flags);
75 trace_cxl_slbia(ctx);
76 memset(ctx->sstp, 0, ctx->sst_size);
77 spin_unlock_irqrestore(&ctx->sste_lock, flags);
78 mb();
79 cxl_afu_slbia(ctx->afu);
80 out_put:
81 put_task_struct(task);
84 static inline void cxl_slbia_core(struct mm_struct *mm)
86 struct cxl *adapter;
87 struct cxl_afu *afu;
88 struct cxl_context *ctx;
89 int card, slice, id;
91 pr_devel("%s called\n", __func__);
93 spin_lock(&adapter_idr_lock);
94 idr_for_each_entry(&cxl_adapter_idr, adapter, card) {
95 /* XXX: Make this lookup faster with link from mm to ctx */
96 spin_lock(&adapter->afu_list_lock);
97 for (slice = 0; slice < adapter->slices; slice++) {
98 afu = adapter->afu[slice];
99 if (!afu || !afu->enabled)
100 continue;
101 rcu_read_lock();
102 idr_for_each_entry(&afu->contexts_idr, ctx, id)
103 _cxl_slbia(ctx, mm);
104 rcu_read_unlock();
106 spin_unlock(&adapter->afu_list_lock);
108 spin_unlock(&adapter_idr_lock);
111 static struct cxl_calls cxl_calls = {
112 .cxl_slbia = cxl_slbia_core,
113 .cxl_pci_associate_default_context = _cxl_pci_associate_default_context,
114 .cxl_pci_disable_device = _cxl_pci_disable_device,
115 .cxl_next_msi_hwirq = _cxl_next_msi_hwirq,
116 .cxl_cx4_setup_msi_irqs = _cxl_cx4_setup_msi_irqs,
117 .cxl_cx4_teardown_msi_irqs = _cxl_cx4_teardown_msi_irqs,
118 .owner = THIS_MODULE,
121 int cxl_alloc_sst(struct cxl_context *ctx)
123 unsigned long vsid;
124 u64 ea_mask, size, sstp0, sstp1;
126 sstp0 = 0;
127 sstp1 = 0;
129 ctx->sst_size = PAGE_SIZE;
130 ctx->sst_lru = 0;
131 ctx->sstp = (struct cxl_sste *)get_zeroed_page(GFP_KERNEL);
132 if (!ctx->sstp) {
133 pr_err("cxl_alloc_sst: Unable to allocate segment table\n");
134 return -ENOMEM;
136 pr_devel("SSTP allocated at 0x%p\n", ctx->sstp);
138 vsid = get_kernel_vsid((u64)ctx->sstp, mmu_kernel_ssize) << 12;
140 sstp0 |= (u64)mmu_kernel_ssize << CXL_SSTP0_An_B_SHIFT;
141 sstp0 |= (SLB_VSID_KERNEL | mmu_psize_defs[mmu_linear_psize].sllp) << 50;
143 size = (((u64)ctx->sst_size >> 8) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT;
144 if (unlikely(size & ~CXL_SSTP0_An_SegTableSize_MASK)) {
145 WARN(1, "Impossible segment table size\n");
146 return -EINVAL;
148 sstp0 |= size;
150 if (mmu_kernel_ssize == MMU_SEGSIZE_256M)
151 ea_mask = 0xfffff00ULL;
152 else
153 ea_mask = 0xffffffff00ULL;
155 sstp0 |= vsid >> (50-14); /* Top 14 bits of VSID */
156 sstp1 |= (vsid << (64-(50-14))) & ~ea_mask;
157 sstp1 |= (u64)ctx->sstp & ea_mask;
158 sstp1 |= CXL_SSTP1_An_V;
160 pr_devel("Looked up %#llx: slbfee. %#llx (ssize: %x, vsid: %#lx), copied to SSTP0: %#llx, SSTP1: %#llx\n",
161 (u64)ctx->sstp, (u64)ctx->sstp & ESID_MASK, mmu_kernel_ssize, vsid, sstp0, sstp1);
163 /* Store calculated sstp hardware points for use later */
164 ctx->sstp0 = sstp0;
165 ctx->sstp1 = sstp1;
167 return 0;
170 /* print buffer content as integers when debugging */
171 void cxl_dump_debug_buffer(void *buf, size_t buf_len)
173 #ifdef DEBUG
174 int i, *ptr;
177 * We want to regroup up to 4 integers per line, which means they
178 * need to be in the same pr_devel() statement
180 ptr = (int *) buf;
181 for (i = 0; i * 4 < buf_len; i += 4) {
182 if ((i + 3) * 4 < buf_len)
183 pr_devel("%.8x %.8x %.8x %.8x\n", ptr[i], ptr[i + 1],
184 ptr[i + 2], ptr[i + 3]);
185 else if ((i + 2) * 4 < buf_len)
186 pr_devel("%.8x %.8x %.8x\n", ptr[i], ptr[i + 1],
187 ptr[i + 2]);
188 else if ((i + 1) * 4 < buf_len)
189 pr_devel("%.8x %.8x\n", ptr[i], ptr[i + 1]);
190 else
191 pr_devel("%.8x\n", ptr[i]);
193 #endif /* DEBUG */
196 /* Find a CXL adapter by it's number and increase it's refcount */
197 struct cxl *get_cxl_adapter(int num)
199 struct cxl *adapter;
201 spin_lock(&adapter_idr_lock);
202 if ((adapter = idr_find(&cxl_adapter_idr, num)))
203 get_device(&adapter->dev);
204 spin_unlock(&adapter_idr_lock);
206 return adapter;
209 static int cxl_alloc_adapter_nr(struct cxl *adapter)
211 int i;
213 idr_preload(GFP_KERNEL);
214 spin_lock(&adapter_idr_lock);
215 i = idr_alloc(&cxl_adapter_idr, adapter, 0, 0, GFP_NOWAIT);
216 spin_unlock(&adapter_idr_lock);
217 idr_preload_end();
218 if (i < 0)
219 return i;
221 adapter->adapter_num = i;
223 return 0;
226 void cxl_remove_adapter_nr(struct cxl *adapter)
228 idr_remove(&cxl_adapter_idr, adapter->adapter_num);
231 struct cxl *cxl_alloc_adapter(void)
233 struct cxl *adapter;
235 if (!(adapter = kzalloc(sizeof(struct cxl), GFP_KERNEL)))
236 return NULL;
238 spin_lock_init(&adapter->afu_list_lock);
240 if (cxl_alloc_adapter_nr(adapter))
241 goto err1;
243 if (dev_set_name(&adapter->dev, "card%i", adapter->adapter_num))
244 goto err2;
246 return adapter;
248 err2:
249 cxl_remove_adapter_nr(adapter);
250 err1:
251 kfree(adapter);
252 return NULL;
255 struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice)
257 struct cxl_afu *afu;
259 if (!(afu = kzalloc(sizeof(struct cxl_afu), GFP_KERNEL)))
260 return NULL;
262 afu->adapter = adapter;
263 afu->dev.parent = &adapter->dev;
264 afu->dev.release = cxl_ops->release_afu;
265 afu->slice = slice;
266 idr_init(&afu->contexts_idr);
267 mutex_init(&afu->contexts_lock);
268 spin_lock_init(&afu->afu_cntl_lock);
270 afu->prefault_mode = CXL_PREFAULT_NONE;
271 afu->irqs_max = afu->adapter->user_irqs;
273 return afu;
276 int cxl_afu_select_best_mode(struct cxl_afu *afu)
278 if (afu->modes_supported & CXL_MODE_DIRECTED)
279 return cxl_ops->afu_activate_mode(afu, CXL_MODE_DIRECTED);
281 if (afu->modes_supported & CXL_MODE_DEDICATED)
282 return cxl_ops->afu_activate_mode(afu, CXL_MODE_DEDICATED);
284 dev_warn(&afu->dev, "No supported programming modes available\n");
285 /* We don't fail this so the user can inspect sysfs */
286 return 0;
289 static int __init init_cxl(void)
291 int rc = 0;
293 if ((rc = cxl_file_init()))
294 return rc;
296 cxl_debugfs_init();
298 if ((rc = register_cxl_calls(&cxl_calls)))
299 goto err;
301 if (cpu_has_feature(CPU_FTR_HVMODE)) {
302 cxl_ops = &cxl_native_ops;
303 rc = pci_register_driver(&cxl_pci_driver);
305 #ifdef CONFIG_PPC_PSERIES
306 else {
307 cxl_ops = &cxl_guest_ops;
308 rc = platform_driver_register(&cxl_of_driver);
310 #endif
311 if (rc)
312 goto err1;
314 return 0;
315 err1:
316 unregister_cxl_calls(&cxl_calls);
317 err:
318 cxl_debugfs_exit();
319 cxl_file_exit();
321 return rc;
324 static void exit_cxl(void)
326 if (cpu_has_feature(CPU_FTR_HVMODE))
327 pci_unregister_driver(&cxl_pci_driver);
328 #ifdef CONFIG_PPC_PSERIES
329 else
330 platform_driver_unregister(&cxl_of_driver);
331 #endif
333 cxl_debugfs_exit();
334 cxl_file_exit();
335 unregister_cxl_calls(&cxl_calls);
336 idr_destroy(&cxl_adapter_idr);
339 module_init(init_cxl);
340 module_exit(exit_cxl);
342 MODULE_DESCRIPTION("IBM Coherent Accelerator");
343 MODULE_AUTHOR("Ian Munsie <imunsie@au1.ibm.com>");
344 MODULE_LICENSE("GPL");