drivers/misc/mei/hw-txe.c

   1 /*
   2  *
   3  * Intel Management Engine Interface (Intel MEI) Linux driver
   4  * Copyright (c) 2013-2014, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13  * more details.
  14  *
  15  */
  16
  17 #include <linux/pci.h>
  18 #include <linux/jiffies.h>
  19 #include <linux/ktime.h>
  20 #include <linux/delay.h>
  21 #include <linux/kthread.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/pm_runtime.h>
  24
  25 #include <linux/mei.h>
  26
  27 #include "mei_dev.h"
  28 #include "hw-txe.h"
  29 #include "client.h"
  30 #include "hbm.h"
  31
  32 #include "mei-trace.h"
  33
  34
  35 /**
  36  * mei_txe_reg_read - Reads 32bit data from the txe device
  37  *
  38  * @base_addr: registers base address
  39  * @offset: register offset
  40  *
  41  * Return: register value
  42  */
  43 static inline u32 mei_txe_reg_read(void __iomem *base_addr,
  44                                         unsigned long offset)
  45 {
  46         return ioread32(base_addr + offset);
  47 }
  48
  49 /**
  50  * mei_txe_reg_write - Writes 32bit data to the txe device
  51  *
  52  * @base_addr: registers base address
  53  * @offset: register offset
  54  * @value: the value to write
  55  */
  56 static inline void mei_txe_reg_write(void __iomem *base_addr,
  57                                 unsigned long offset, u32 value)
  58 {
  59         iowrite32(value, base_addr + offset);
  60 }
  61
  62 /**
  63  * mei_txe_sec_reg_read_silent - Reads 32bit data from the SeC BAR
  64  *
  65  * @hw: the txe hardware structure
  66  * @offset: register offset
  67  *
  68  * Doesn't check for aliveness while Reads 32bit data from the SeC BAR
  69  *
  70  * Return: register value
  71  */
  72 static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw,
  73                                 unsigned long offset)
  74 {
  75         return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset);
  76 }
  77
  78 /**
  79  * mei_txe_sec_reg_read - Reads 32bit data from the SeC BAR
  80  *
  81  * @hw: the txe hardware structure
  82  * @offset: register offset
  83  *
  84  * Reads 32bit data from the SeC BAR and shout loud if aliveness is not set
  85  *
  86  * Return: register value
  87  */
  88 static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw,
  89                                 unsigned long offset)
  90 {
  91         WARN(!hw->aliveness, "sec read: aliveness not asserted\n");
  92         return mei_txe_sec_reg_read_silent(hw, offset);
  93 }
  94 /**
  95  * mei_txe_sec_reg_write_silent - Writes 32bit data to the SeC BAR
  96  *   doesn't check for aliveness
  97  *
  98  * @hw: the txe hardware structure
  99  * @offset: register offset
 100  * @value: value to write
 101  *
 102  * Doesn't check for aliveness while writes 32bit data from to the SeC BAR
 103  */
 104 static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw,
 105                                 unsigned long offset, u32 value)
 106 {
 107         mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value);
 108 }
 109
 110 /**
 111  * mei_txe_sec_reg_write - Writes 32bit data to the SeC BAR
 112  *
 113  * @hw: the txe hardware structure
 114  * @offset: register offset
 115  * @value: value to write
 116  *
 117  * Writes 32bit data from the SeC BAR and shout loud if aliveness is not set
 118  */
 119 static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw,
 120                                 unsigned long offset, u32 value)
 121 {
 122         WARN(!hw->aliveness, "sec write: aliveness not asserted\n");
 123         mei_txe_sec_reg_write_silent(hw, offset, value);
 124 }
 125 /**
 126  * mei_txe_br_reg_read - Reads 32bit data from the Bridge BAR
 127  *
 128  * @hw: the txe hardware structure
 129  * @offset: offset from which to read the data
 130  *
 131  * Return: the byte read.
 132  */
 133 static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw,
 134                                 unsigned long offset)
 135 {
 136         return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset);
 137 }
 138
 139 /**
 140  * mei_txe_br_reg_write - Writes 32bit data to the Bridge BAR
 141  *
 142  * @hw: the txe hardware structure
 143  * @offset: offset from which to write the data
 144  * @value: the byte to write
 145  */
 146 static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw,
 147                                 unsigned long offset, u32 value)
 148 {
 149         mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value);
 150 }
 151
 152 /**
 153  * mei_txe_aliveness_set - request for aliveness change
 154  *
 155  * @dev: the device structure
 156  * @req: requested aliveness value
 157  *
 158  * Request for aliveness change and returns true if the change is
 159  *   really needed and false if aliveness is already
 160  *   in the requested state
 161  *
 162  * Locking: called under "dev->device_lock" lock
 163  *
 164  * Return: true if request was send
 165  */
 166 static bool mei_txe_aliveness_set(struct mei_device *dev, u32 req)
 167 {
 168
 169         struct mei_txe_hw *hw = to_txe_hw(dev);
 170         bool do_req = hw->aliveness != req;
 171
 172         dev_dbg(dev->dev, "Aliveness current=%d request=%d\n",
 173                                 hw->aliveness, req);
 174         if (do_req) {
 175                 dev->pg_event = MEI_PG_EVENT_WAIT;
 176                 mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req);
 177         }
 178         return do_req;
 179 }
 180
 181
 182 /**
 183  * mei_txe_aliveness_req_get - get aliveness requested register value
 184  *
 185  * @dev: the device structure
 186  *
 187  * Extract HICR_HOST_ALIVENESS_RESP_ACK bit from
 188  * from HICR_HOST_ALIVENESS_REQ register value
 189  *
 190  * Return: SICR_HOST_ALIVENESS_REQ_REQUESTED bit value
 191  */
 192 static u32 mei_txe_aliveness_req_get(struct mei_device *dev)
 193 {
 194         struct mei_txe_hw *hw = to_txe_hw(dev);
 195         u32 reg;
 196
 197         reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG);
 198         return reg & SICR_HOST_ALIVENESS_REQ_REQUESTED;
 199 }
 200
 201 /**
 202  * mei_txe_aliveness_get - get aliveness response register value
 203  *
 204  * @dev: the device structure
 205  *
 206  * Return: HICR_HOST_ALIVENESS_RESP_ACK bit from HICR_HOST_ALIVENESS_RESP
 207  *         register
 208  */
 209 static u32 mei_txe_aliveness_get(struct mei_device *dev)
 210 {
 211         struct mei_txe_hw *hw = to_txe_hw(dev);
 212         u32 reg;
 213
 214         reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG);
 215         return reg & HICR_HOST_ALIVENESS_RESP_ACK;
 216 }
 217
 218 /**
 219  * mei_txe_aliveness_poll - waits for aliveness to settle
 220  *
 221  * @dev: the device structure
 222  * @expected: expected aliveness value
 223  *
 224  * Polls for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set
 225  *
 226  * Return: 0 if the expected value was received, -ETIME otherwise
 227  */
 228 static int mei_txe_aliveness_poll(struct mei_device *dev, u32 expected)
 229 {
 230         struct mei_txe_hw *hw = to_txe_hw(dev);
 231         ktime_t stop, start;
 232
 233         start = ktime_get();
 234         stop = ktime_add(start, ms_to_ktime(SEC_ALIVENESS_WAIT_TIMEOUT));
 235         do {
 236                 hw->aliveness = mei_txe_aliveness_get(dev);
 237                 if (hw->aliveness == expected) {
 238                         dev->pg_event = MEI_PG_EVENT_IDLE;
 239                         dev_dbg(dev->dev, "aliveness settled after %lld usecs\n",
 240                                 ktime_to_us(ktime_sub(ktime_get(), start)));
 241                         return 0;
 242                 }
 243                 usleep_range(20, 50);
 244         } while (ktime_before(ktime_get(), stop));
 245
 246         dev->pg_event = MEI_PG_EVENT_IDLE;
 247         dev_err(dev->dev, "aliveness timed out\n");
 248         return -ETIME;
 249 }
 250
 251 /**
 252  * mei_txe_aliveness_wait - waits for aliveness to settle
 253  *
 254  * @dev: the device structure
 255  * @expected: expected aliveness value
 256  *
 257  * Waits for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set
 258  *
 259  * Return: 0 on success and < 0 otherwise
 260  */
 261 static int mei_txe_aliveness_wait(struct mei_device *dev, u32 expected)
 262 {
 263         struct mei_txe_hw *hw = to_txe_hw(dev);
 264         const unsigned long timeout =
 265                         msecs_to_jiffies(SEC_ALIVENESS_WAIT_TIMEOUT);
 266         long err;
 267         int ret;
 268
 269         hw->aliveness = mei_txe_aliveness_get(dev);
 270         if (hw->aliveness == expected)
 271                 return 0;
 272
 273         mutex_unlock(&dev->device_lock);
 274         err = wait_event_timeout(hw->wait_aliveness_resp,
 275                         dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
 276         mutex_lock(&dev->device_lock);
 277
 278         hw->aliveness = mei_txe_aliveness_get(dev);
 279         ret = hw->aliveness == expected ? 0 : -ETIME;
 280
 281         if (ret)
 282                 dev_warn(dev->dev, "aliveness timed out = %ld aliveness = %d event = %d\n",
 283                         err, hw->aliveness, dev->pg_event);
 284         else
 285                 dev_dbg(dev->dev, "aliveness settled after = %d msec aliveness = %d event = %d\n",
 286                         jiffies_to_msecs(timeout - err),
 287                         hw->aliveness, dev->pg_event);
 288
 289         dev->pg_event = MEI_PG_EVENT_IDLE;
 290         return ret;
 291 }
 292
 293 /**
 294  * mei_txe_aliveness_set_sync - sets an wait for aliveness to complete
 295  *
 296  * @dev: the device structure
 297  * @req: requested aliveness value
 298  *
 299  * Return: 0 on success and < 0 otherwise
 300  */
 301 int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req)
 302 {
 303         if (mei_txe_aliveness_set(dev, req))
 304                 return mei_txe_aliveness_wait(dev, req);
 305         return 0;
 306 }
 307
 308 /**
 309  * mei_txe_pg_in_transition - is device now in pg transition
 310  *
 311  * @dev: the device structure
 312  *
 313  * Return: true if in pg transition, false otherwise
 314  */
 315 static bool mei_txe_pg_in_transition(struct mei_device *dev)
 316 {
 317         return dev->pg_event == MEI_PG_EVENT_WAIT;
 318 }
 319
 320 /**
 321  * mei_txe_pg_is_enabled - detect if PG is supported by HW
 322  *
 323  * @dev: the device structure
 324  *
 325  * Return: true is pg supported, false otherwise
 326  */
 327 static bool mei_txe_pg_is_enabled(struct mei_device *dev)
 328 {
 329         return true;
 330 }
 331
 332 /**
 333  * mei_txe_pg_state  - translate aliveness register value
 334  *   to the mei power gating state
 335  *
 336  * @dev: the device structure
 337  *
 338  * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
 339  */
 340 static inline enum mei_pg_state mei_txe_pg_state(struct mei_device *dev)
 341 {
 342         struct mei_txe_hw *hw = to_txe_hw(dev);
 343
 344         return hw->aliveness ? MEI_PG_OFF : MEI_PG_ON;
 345 }
 346
 347 /**
 348  * mei_txe_input_ready_interrupt_enable - sets the Input Ready Interrupt
 349  *
 350  * @dev: the device structure
 351  */
 352 static void mei_txe_input_ready_interrupt_enable(struct mei_device *dev)
 353 {
 354         struct mei_txe_hw *hw = to_txe_hw(dev);
 355         u32 hintmsk;
 356         /* Enable the SEC_IPC_HOST_INT_MASK_IN_RDY interrupt */
 357         hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG);
 358         hintmsk |= SEC_IPC_HOST_INT_MASK_IN_RDY;
 359         mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk);
 360 }
 361
 362 /**
 363  * mei_txe_input_doorbell_set - sets bit 0 in
 364  *    SEC_IPC_INPUT_DOORBELL.IPC_INPUT_DOORBELL.
 365  *
 366  * @hw: the txe hardware structure
 367  */
 368 static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw)
 369 {
 370         /* Clear the interrupt cause */
 371         clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause);
 372         mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1);
 373 }
 374
 375 /**
 376  * mei_txe_output_ready_set - Sets the SICR_SEC_IPC_OUTPUT_STATUS bit to 1
 377  *
 378  * @hw: the txe hardware structure
 379  */
 380 static void mei_txe_output_ready_set(struct mei_txe_hw *hw)
 381 {
 382         mei_txe_br_reg_write(hw,
 383                         SICR_SEC_IPC_OUTPUT_STATUS_REG,
 384                         SEC_IPC_OUTPUT_STATUS_RDY);
 385 }
 386
 387 /**
 388  * mei_txe_is_input_ready - check if TXE is ready for receiving data
 389  *
 390  * @dev: the device structure
 391  *
 392  * Return: true if INPUT STATUS READY bit is set
 393  */
 394 static bool mei_txe_is_input_ready(struct mei_device *dev)
 395 {
 396         struct mei_txe_hw *hw = to_txe_hw(dev);
 397         u32 status;
 398
 399         status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG);
 400         return !!(SEC_IPC_INPUT_STATUS_RDY & status);
 401 }
 402
 403 /**
 404  * mei_txe_intr_clear - clear all interrupts
 405  *
 406  * @dev: the device structure
 407  */
 408 static inline void mei_txe_intr_clear(struct mei_device *dev)
 409 {
 410         struct mei_txe_hw *hw = to_txe_hw(dev);
 411
 412         mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG,
 413                 SEC_IPC_HOST_INT_STATUS_PENDING);
 414         mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK);
 415         mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK);
 416 }
 417
 418 /**
 419  * mei_txe_intr_disable - disable all interrupts
 420  *
 421  * @dev: the device structure
 422  */
 423 static void mei_txe_intr_disable(struct mei_device *dev)
 424 {
 425         struct mei_txe_hw *hw = to_txe_hw(dev);
 426
 427         mei_txe_br_reg_write(hw, HHIER_REG, 0);
 428         mei_txe_br_reg_write(hw, HIER_REG, 0);
 429 }
 430 /**
 431  * mei_txe_intr_enable - enable all interrupts
 432  *
 433  * @dev: the device structure
 434  */
 435 static void mei_txe_intr_enable(struct mei_device *dev)
 436 {
 437         struct mei_txe_hw *hw = to_txe_hw(dev);
 438
 439         mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK);
 440         mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK);
 441 }
 442
 443 /**
 444  * mei_txe_pending_interrupts - check if there are pending interrupts
 445  *      only Aliveness, Input ready, and output doorbell are of relevance
 446  *
 447  * @dev: the device structure
 448  *
 449  * Checks if there are pending interrupts
 450  * only Aliveness, Readiness, Input ready, and Output doorbell are relevant
 451  *
 452  * Return: true if there are pending interrupts
 453  */
 454 static bool mei_txe_pending_interrupts(struct mei_device *dev)
 455 {
 456
 457         struct mei_txe_hw *hw = to_txe_hw(dev);
 458         bool ret = (hw->intr_cause & (TXE_INTR_READINESS |
 459                                       TXE_INTR_ALIVENESS |
 460                                       TXE_INTR_IN_READY  |
 461                                       TXE_INTR_OUT_DB));
 462
 463         if (ret) {
 464                 dev_dbg(dev->dev,
 465                         "Pending Interrupts InReady=%01d Readiness=%01d, Aliveness=%01d, OutDoor=%01d\n",
 466                         !!(hw->intr_cause & TXE_INTR_IN_READY),
 467                         !!(hw->intr_cause & TXE_INTR_READINESS),
 468                         !!(hw->intr_cause & TXE_INTR_ALIVENESS),
 469                         !!(hw->intr_cause & TXE_INTR_OUT_DB));
 470         }
 471         return ret;
 472 }
 473
 474 /**
 475  * mei_txe_input_payload_write - write a dword to the host buffer
 476  *      at offset idx
 477  *
 478  * @dev: the device structure
 479  * @idx: index in the host buffer
 480  * @value: value
 481  */
 482 static void mei_txe_input_payload_write(struct mei_device *dev,
 483                         unsigned long idx, u32 value)
 484 {
 485         struct mei_txe_hw *hw = to_txe_hw(dev);
 486
 487         mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG +
 488                         (idx * sizeof(u32)), value);
 489 }
 490
 491 /**
 492  * mei_txe_out_data_read - read dword from the device buffer
 493  *      at offset idx
 494  *
 495  * @dev: the device structure
 496  * @idx: index in the device buffer
 497  *
 498  * Return: register value at index
 499  */
 500 static u32 mei_txe_out_data_read(const struct mei_device *dev,
 501                                         unsigned long idx)
 502 {
 503         struct mei_txe_hw *hw = to_txe_hw(dev);
 504
 505         return mei_txe_br_reg_read(hw,
 506                 BRIDGE_IPC_OUTPUT_PAYLOAD_REG + (idx * sizeof(u32)));
 507 }
 508
 509 /* Readiness */
 510
 511 /**
 512  * mei_txe_readiness_set_host_rdy - set host readiness bit
 513  *
 514  * @dev: the device structure
 515  */
 516 static void mei_txe_readiness_set_host_rdy(struct mei_device *dev)
 517 {
 518         struct mei_txe_hw *hw = to_txe_hw(dev);
 519
 520         mei_txe_br_reg_write(hw,
 521                 SICR_HOST_IPC_READINESS_REQ_REG,
 522                 SICR_HOST_IPC_READINESS_HOST_RDY);
 523 }
 524
 525 /**
 526  * mei_txe_readiness_clear - clear host readiness bit
 527  *
 528  * @dev: the device structure
 529  */
 530 static void mei_txe_readiness_clear(struct mei_device *dev)
 531 {
 532         struct mei_txe_hw *hw = to_txe_hw(dev);
 533
 534         mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG,
 535                                 SICR_HOST_IPC_READINESS_RDY_CLR);
 536 }
 537 /**
 538  * mei_txe_readiness_get - Reads and returns
 539  *      the HICR_SEC_IPC_READINESS register value
 540  *
 541  * @dev: the device structure
 542  *
 543  * Return: the HICR_SEC_IPC_READINESS register value
 544  */
 545 static u32 mei_txe_readiness_get(struct mei_device *dev)
 546 {
 547         struct mei_txe_hw *hw = to_txe_hw(dev);
 548
 549         return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
 550 }
 551
 552
 553 /**
 554  * mei_txe_readiness_is_sec_rdy - check readiness
 555  *  for HICR_SEC_IPC_READINESS_SEC_RDY
 556  *
 557  * @readiness: cached readiness state
 558  *
 559  * Return: true if readiness bit is set
 560  */
 561 static inline bool mei_txe_readiness_is_sec_rdy(u32 readiness)
 562 {
 563         return !!(readiness & HICR_SEC_IPC_READINESS_SEC_RDY);
 564 }
 565
 566 /**
 567  * mei_txe_hw_is_ready - check if the hw is ready
 568  *
 569  * @dev: the device structure
 570  *
 571  * Return: true if sec is ready
 572  */
 573 static bool mei_txe_hw_is_ready(struct mei_device *dev)
 574 {
 575         u32 readiness =  mei_txe_readiness_get(dev);
 576
 577         return mei_txe_readiness_is_sec_rdy(readiness);
 578 }
 579
 580 /**
 581  * mei_txe_host_is_ready - check if the host is ready
 582  *
 583  * @dev: the device structure
 584  *
 585  * Return: true if host is ready
 586  */
 587 static inline bool mei_txe_host_is_ready(struct mei_device *dev)
 588 {
 589         struct mei_txe_hw *hw = to_txe_hw(dev);
 590         u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
 591
 592         return !!(reg & HICR_SEC_IPC_READINESS_HOST_RDY);
 593 }
 594
 595 /**
 596  * mei_txe_readiness_wait - wait till readiness settles
 597  *
 598  * @dev: the device structure
 599  *
 600  * Return: 0 on success and -ETIME on timeout
 601  */
 602 static int mei_txe_readiness_wait(struct mei_device *dev)
 603 {
 604         if (mei_txe_hw_is_ready(dev))
 605                 return 0;
 606
 607         mutex_unlock(&dev->device_lock);
 608         wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready,
 609                         msecs_to_jiffies(SEC_RESET_WAIT_TIMEOUT));
 610         mutex_lock(&dev->device_lock);
 611         if (!dev->recvd_hw_ready) {
 612                 dev_err(dev->dev, "wait for readiness failed\n");
 613                 return -ETIME;
 614         }
 615
 616         dev->recvd_hw_ready = false;
 617         return 0;
 618 }
 619
 620 static const struct mei_fw_status mei_txe_fw_sts = {
 621         .count = 2,
 622         .status[0] = PCI_CFG_TXE_FW_STS0,
 623         .status[1] = PCI_CFG_TXE_FW_STS1
 624 };
 625
 626 /**
 627  * mei_txe_fw_status - read fw status register from pci config space
 628  *
 629  * @dev: mei device
 630  * @fw_status: fw status register values
 631  *
 632  * Return: 0 on success, error otherwise
 633  */
 634 static int mei_txe_fw_status(struct mei_device *dev,
 635                              struct mei_fw_status *fw_status)
 636 {
 637         const struct mei_fw_status *fw_src = &mei_txe_fw_sts;
 638         struct pci_dev *pdev = to_pci_dev(dev->dev);
 639         int ret;
 640         int i;
 641
 642         if (!fw_status)
 643                 return -EINVAL;
 644
 645         fw_status->count = fw_src->count;
 646         for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
 647                 ret = pci_read_config_dword(pdev, fw_src->status[i],
 648                                             &fw_status->status[i]);
 649                 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X",
 650                                        fw_src->status[i],
 651                                        fw_status->status[i]);
 652                 if (ret)
 653                         return ret;
 654         }
 655
 656         return 0;
 657 }
 658
 659 /**
 660  *  mei_txe_hw_config - configure hardware at the start of the devices
 661  *
 662  * @dev: the device structure
 663  *
 664  * Configure hardware at the start of the device should be done only
 665  *   once at the device probe time
 666  */
 667 static void mei_txe_hw_config(struct mei_device *dev)
 668 {
 669
 670         struct mei_txe_hw *hw = to_txe_hw(dev);
 671
 672         /* Doesn't change in runtime */
 673         dev->hbuf_depth = PAYLOAD_SIZE / 4;
 674
 675         hw->aliveness = mei_txe_aliveness_get(dev);
 676         hw->readiness = mei_txe_readiness_get(dev);
 677
 678         dev_dbg(dev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n",
 679                 hw->aliveness, hw->readiness);
 680 }
 681
 682
 683 /**
 684  * mei_txe_write - writes a message to device.
 685  *
 686  * @dev: the device structure
 687  * @header: header of message
 688  * @buf: message buffer will be written
 689  *
 690  * Return: 0 if success, <0 - otherwise.
 691  */
 692
 693 static int mei_txe_write(struct mei_device *dev,
 694                 struct mei_msg_hdr *header, unsigned char *buf)
 695 {
 696         struct mei_txe_hw *hw = to_txe_hw(dev);
 697         unsigned long rem;
 698         unsigned long length;
 699         int slots = dev->hbuf_depth;
 700         u32 *reg_buf = (u32 *)buf;
 701         u32 dw_cnt;
 702         int i;
 703
 704         if (WARN_ON(!header || !buf))
 705                 return -EINVAL;
 706
 707         length = header->length;
 708
 709         dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
 710
 711         dw_cnt = mei_data2slots(length);
 712         if (dw_cnt > slots)
 713                 return -EMSGSIZE;
 714
 715         if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n"))
 716                 return -EAGAIN;
 717
 718         /* Enable Input Ready Interrupt. */
 719         mei_txe_input_ready_interrupt_enable(dev);
 720
 721         if (!mei_txe_is_input_ready(dev)) {
 722                 char fw_sts_str[MEI_FW_STATUS_STR_SZ];
 723
 724                 mei_fw_status_str(dev, fw_sts_str, MEI_FW_STATUS_STR_SZ);
 725                 dev_err(dev->dev, "Input is not ready %s\n", fw_sts_str);
 726                 return -EAGAIN;
 727         }
 728
 729         mei_txe_input_payload_write(dev, 0, *((u32 *)header));
 730
 731         for (i = 0; i < length / 4; i++)
 732                 mei_txe_input_payload_write(dev, i + 1, reg_buf[i]);
 733
 734         rem = length & 0x3;
 735         if (rem > 0) {
 736                 u32 reg = 0;
 737
 738                 memcpy(&reg, &buf[length - rem], rem);
 739                 mei_txe_input_payload_write(dev, i + 1, reg);
 740         }
 741
 742         /* after each write the whole buffer is consumed */
 743         hw->slots = 0;
 744
 745         /* Set Input-Doorbell */
 746         mei_txe_input_doorbell_set(hw);
 747
 748         return 0;
 749 }
 750
 751 /**
 752  * mei_txe_hbuf_max_len - mimics the me hbuf circular buffer
 753  *
 754  * @dev: the device structure
 755  *
 756  * Return: the PAYLOAD_SIZE - 4
 757  */
 758 static size_t mei_txe_hbuf_max_len(const struct mei_device *dev)
 759 {
 760         return PAYLOAD_SIZE - sizeof(struct mei_msg_hdr);
 761 }
 762
 763 /**
 764  * mei_txe_hbuf_empty_slots - mimics the me hbuf circular buffer
 765  *
 766  * @dev: the device structure
 767  *
 768  * Return: always hbuf_depth
 769  */
 770 static int mei_txe_hbuf_empty_slots(struct mei_device *dev)
 771 {
 772         struct mei_txe_hw *hw = to_txe_hw(dev);
 773
 774         return hw->slots;
 775 }
 776
 777 /**
 778  * mei_txe_count_full_read_slots - mimics the me device circular buffer
 779  *
 780  * @dev: the device structure
 781  *
 782  * Return: always buffer size in dwords count
 783  */
 784 static int mei_txe_count_full_read_slots(struct mei_device *dev)
 785 {
 786         /* read buffers has static size */
 787         return  PAYLOAD_SIZE / 4;
 788 }
 789
 790 /**
 791  * mei_txe_read_hdr - read message header which is always in 4 first bytes
 792  *
 793  * @dev: the device structure
 794  *
 795  * Return: mei message header
 796  */
 797
 798 static u32 mei_txe_read_hdr(const struct mei_device *dev)
 799 {
 800         return mei_txe_out_data_read(dev, 0);
 801 }
 802 /**
 803  * mei_txe_read - reads a message from the txe device.
 804  *
 805  * @dev: the device structure
 806  * @buf: message buffer will be written
 807  * @len: message size will be read
 808  *
 809  * Return: -EINVAL on error wrong argument and 0 on success
 810  */
 811 static int mei_txe_read(struct mei_device *dev,
 812                 unsigned char *buf, unsigned long len)
 813 {
 814
 815         struct mei_txe_hw *hw = to_txe_hw(dev);
 816         u32 *reg_buf, reg;
 817         u32 rem;
 818         u32 i;
 819
 820         if (WARN_ON(!buf || !len))
 821                 return -EINVAL;
 822
 823         reg_buf = (u32 *)buf;
 824         rem = len & 0x3;
 825
 826         dev_dbg(dev->dev, "buffer-length = %lu buf[0]0x%08X\n",
 827                 len, mei_txe_out_data_read(dev, 0));
 828
 829         for (i = 0; i < len / 4; i++) {
 830                 /* skip header: index starts from 1 */
 831                 reg = mei_txe_out_data_read(dev, i + 1);
 832                 dev_dbg(dev->dev, "buf[%d] = 0x%08X\n", i, reg);
 833                 *reg_buf++ = reg;
 834         }
 835
 836         if (rem) {
 837                 reg = mei_txe_out_data_read(dev, i + 1);
 838                 memcpy(reg_buf, &reg, rem);
 839         }
 840
 841         mei_txe_output_ready_set(hw);
 842         return 0;
 843 }
 844
 845 /**
 846  * mei_txe_hw_reset - resets host and fw.
 847  *
 848  * @dev: the device structure
 849  * @intr_enable: if interrupt should be enabled after reset.
 850  *
 851  * Return: 0 on success and < 0 in case of error
 852  */
 853 static int mei_txe_hw_reset(struct mei_device *dev, bool intr_enable)
 854 {
 855         struct mei_txe_hw *hw = to_txe_hw(dev);
 856
 857         u32 aliveness_req;
 858         /*
 859          * read input doorbell to ensure consistency between  Bridge and SeC
 860          * return value might be garbage return
 861          */
 862         (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG);
 863
 864         aliveness_req = mei_txe_aliveness_req_get(dev);
 865         hw->aliveness = mei_txe_aliveness_get(dev);
 866
 867         /* Disable interrupts in this stage we will poll */
 868         mei_txe_intr_disable(dev);
 869
 870         /*
 871          * If Aliveness Request and Aliveness Response are not equal then
 872          * wait for them to be equal
 873          * Since we might have interrupts disabled - poll for it
 874          */
 875         if (aliveness_req != hw->aliveness)
 876                 if (mei_txe_aliveness_poll(dev, aliveness_req) < 0) {
 877                         dev_err(dev->dev, "wait for aliveness settle failed ... bailing out\n");
 878                         return -EIO;
 879                 }
 880
 881         /*
 882          * If Aliveness Request and Aliveness Response are set then clear them
 883          */
 884         if (aliveness_req) {
 885                 mei_txe_aliveness_set(dev, 0);
 886                 if (mei_txe_aliveness_poll(dev, 0) < 0) {
 887                         dev_err(dev->dev, "wait for aliveness failed ... bailing out\n");
 888                         return -EIO;
 889                 }
 890         }
 891
 892         /*
 893          * Set readiness RDY_CLR bit
 894          */
 895         mei_txe_readiness_clear(dev);
 896
 897         return 0;
 898 }
 899
 900 /**
 901  * mei_txe_hw_start - start the hardware after reset
 902  *
 903  * @dev: the device structure
 904  *
 905  * Return: 0 on success an error code otherwise
 906  */
 907 static int mei_txe_hw_start(struct mei_device *dev)
 908 {
 909         struct mei_txe_hw *hw = to_txe_hw(dev);
 910         int ret;
 911
 912         u32 hisr;
 913
 914         /* bring back interrupts */
 915         mei_txe_intr_enable(dev);
 916
 917         ret = mei_txe_readiness_wait(dev);
 918         if (ret < 0) {
 919                 dev_err(dev->dev, "waiting for readiness failed\n");
 920                 return ret;
 921         }
 922
 923         /*
 924          * If HISR.INT2_STS interrupt status bit is set then clear it.
 925          */
 926         hisr = mei_txe_br_reg_read(hw, HISR_REG);
 927         if (hisr & HISR_INT_2_STS)
 928                 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS);
 929
 930         /* Clear the interrupt cause of OutputDoorbell */
 931         clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause);
 932
 933         ret = mei_txe_aliveness_set_sync(dev, 1);
 934         if (ret < 0) {
 935                 dev_err(dev->dev, "wait for aliveness failed ... bailing out\n");
 936                 return ret;
 937         }
 938
 939         pm_runtime_set_active(dev->dev);
 940
 941         /* enable input ready interrupts:
 942          * SEC_IPC_HOST_INT_MASK.IPC_INPUT_READY_INT_MASK
 943          */
 944         mei_txe_input_ready_interrupt_enable(dev);
 945
 946
 947         /*  Set the SICR_SEC_IPC_OUTPUT_STATUS.IPC_OUTPUT_READY bit */
 948         mei_txe_output_ready_set(hw);
 949
 950         /* Set bit SICR_HOST_IPC_READINESS.HOST_RDY
 951          */
 952         mei_txe_readiness_set_host_rdy(dev);
 953
 954         return 0;
 955 }
 956
 957 /**
 958  * mei_txe_check_and_ack_intrs - translate multi BAR interrupt into
 959  *  single bit mask and acknowledge the interrupts
 960  *
 961  * @dev: the device structure
 962  * @do_ack: acknowledge interrupts
 963  *
 964  * Return: true if found interrupts to process.
 965  */
 966 static bool mei_txe_check_and_ack_intrs(struct mei_device *dev, bool do_ack)
 967 {
 968         struct mei_txe_hw *hw = to_txe_hw(dev);
 969         u32 hisr;
 970         u32 hhisr;
 971         u32 ipc_isr;
 972         u32 aliveness;
 973         bool generated;
 974
 975         /* read interrupt registers */
 976         hhisr = mei_txe_br_reg_read(hw, HHISR_REG);
 977         generated = (hhisr & IPC_HHIER_MSK);
 978         if (!generated)
 979                 goto out;
 980
 981         hisr = mei_txe_br_reg_read(hw, HISR_REG);
 982
 983         aliveness = mei_txe_aliveness_get(dev);
 984         if (hhisr & IPC_HHIER_SEC && aliveness)
 985                 ipc_isr = mei_txe_sec_reg_read_silent(hw,
 986                                 SEC_IPC_HOST_INT_STATUS_REG);
 987         else
 988                 ipc_isr = 0;
 989
 990         generated = generated ||
 991                 (hisr & HISR_INT_STS_MSK) ||
 992                 (ipc_isr & SEC_IPC_HOST_INT_STATUS_PENDING);
 993
 994         if (generated && do_ack) {
 995                 /* Save the interrupt causes */
 996                 hw->intr_cause |= hisr & HISR_INT_STS_MSK;
 997                 if (ipc_isr & SEC_IPC_HOST_INT_STATUS_IN_RDY)
 998                         hw->intr_cause |= TXE_INTR_IN_READY;
 999
1000
1001                 mei_txe_intr_disable(dev);
1002                 /* Clear the interrupts in hierarchy:
1003                  * IPC and Bridge, than the High Level */
1004                 mei_txe_sec_reg_write_silent(hw,
1005                         SEC_IPC_HOST_INT_STATUS_REG, ipc_isr);
1006                 mei_txe_br_reg_write(hw, HISR_REG, hisr);
1007                 mei_txe_br_reg_write(hw, HHISR_REG, hhisr);
1008         }
1009
1010 out:
1011         return generated;
1012 }
1013
1014 /**
1015  * mei_txe_irq_quick_handler - The ISR of the MEI device
1016  *
1017  * @irq: The irq number
1018  * @dev_id: pointer to the device structure
1019  *
1020  * Return: IRQ_WAKE_THREAD if interrupt is designed for the device
1021  *         IRQ_NONE otherwise
1022  */
1023 irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id)
1024 {
1025         struct mei_device *dev = dev_id;
1026
1027         if (mei_txe_check_and_ack_intrs(dev, true))
1028                 return IRQ_WAKE_THREAD;
1029         return IRQ_NONE;
1030 }
1031
1032
1033 /**
1034  * mei_txe_irq_thread_handler - txe interrupt thread
1035  *
1036  * @irq: The irq number
1037  * @dev_id: pointer to the device structure
1038  *
1039  * Return: IRQ_HANDLED
1040  */
1041 irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id)
1042 {
1043         struct mei_device *dev = (struct mei_device *) dev_id;
1044         struct mei_txe_hw *hw = to_txe_hw(dev);
1045         struct mei_cl_cb complete_list;
1046         s32 slots;
1047         int rets = 0;
1048
1049         dev_dbg(dev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n",
1050                 mei_txe_br_reg_read(hw, HHISR_REG),
1051                 mei_txe_br_reg_read(hw, HISR_REG),
1052                 mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG));
1053
1054
1055         /* initialize our complete list */
1056         mutex_lock(&dev->device_lock);
1057         mei_io_list_init(&complete_list);
1058
1059         if (pci_dev_msi_enabled(to_pci_dev(dev->dev)))
1060                 mei_txe_check_and_ack_intrs(dev, true);
1061
1062         /* show irq events */
1063         mei_txe_pending_interrupts(dev);
1064
1065         hw->aliveness = mei_txe_aliveness_get(dev);
1066         hw->readiness = mei_txe_readiness_get(dev);
1067
1068         /* Readiness:
1069          * Detection of TXE driver going through reset
1070          * or TXE driver resetting the HECI interface.
1071          */
1072         if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) {
1073                 dev_dbg(dev->dev, "Readiness Interrupt was received...\n");
1074
1075                 /* Check if SeC is going through reset */
1076                 if (mei_txe_readiness_is_sec_rdy(hw->readiness)) {
1077                         dev_dbg(dev->dev, "we need to start the dev.\n");
1078                         dev->recvd_hw_ready = true;
1079                 } else {
1080                         dev->recvd_hw_ready = false;
1081                         if (dev->dev_state != MEI_DEV_RESETTING) {
1082
1083                                 dev_warn(dev->dev, "FW not ready: resetting.\n");
1084                                 schedule_work(&dev->reset_work);
1085                                 goto end;
1086
1087                         }
1088                 }
1089                 wake_up(&dev->wait_hw_ready);
1090         }
1091
1092         /************************************************************/
1093         /* Check interrupt cause:
1094          * Aliveness: Detection of SeC acknowledge of host request that
1095          * it remain alive or host cancellation of that request.
1096          */
1097
1098         if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) {
1099                 /* Clear the interrupt cause */
1100                 dev_dbg(dev->dev,
1101                         "Aliveness Interrupt: Status: %d\n", hw->aliveness);
1102                 dev->pg_event = MEI_PG_EVENT_RECEIVED;
1103                 if (waitqueue_active(&hw->wait_aliveness_resp))
1104                         wake_up(&hw->wait_aliveness_resp);
1105         }
1106
1107
1108         /* Output Doorbell:
1109          * Detection of SeC having sent output to host
1110          */
1111         slots = mei_count_full_read_slots(dev);
1112         if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) {
1113                 /* Read from TXE */
1114                 rets = mei_irq_read_handler(dev, &complete_list, &slots);
1115                 if (rets && dev->dev_state != MEI_DEV_RESETTING) {
1116                         dev_err(dev->dev,
1117                                 "mei_irq_read_handler ret = %d.\n", rets);
1118
1119                         schedule_work(&dev->reset_work);
1120                         goto end;
1121                 }
1122         }
1123         /* Input Ready: Detection if host can write to SeC */
1124         if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) {
1125                 dev->hbuf_is_ready = true;
1126                 hw->slots = dev->hbuf_depth;
1127         }
1128
1129         if (hw->aliveness && dev->hbuf_is_ready) {
1130                 /* get the real register value */
1131                 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1132                 rets = mei_irq_write_handler(dev, &complete_list);
1133                 if (rets && rets != -EMSGSIZE)
1134                         dev_err(dev->dev, "mei_irq_write_handler ret = %d.\n",
1135                                 rets);
1136                 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1137         }
1138
1139         mei_irq_compl_handler(dev, &complete_list);
1140
1141 end:
1142         dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
1143
1144         mutex_unlock(&dev->device_lock);
1145
1146         mei_enable_interrupts(dev);
1147         return IRQ_HANDLED;
1148 }
1149
1150 static const struct mei_hw_ops mei_txe_hw_ops = {
1151
1152         .host_is_ready = mei_txe_host_is_ready,
1153
1154         .fw_status = mei_txe_fw_status,
1155         .pg_state = mei_txe_pg_state,
1156
1157         .hw_is_ready = mei_txe_hw_is_ready,
1158         .hw_reset = mei_txe_hw_reset,
1159         .hw_config = mei_txe_hw_config,
1160         .hw_start = mei_txe_hw_start,
1161
1162         .pg_in_transition = mei_txe_pg_in_transition,
1163         .pg_is_enabled = mei_txe_pg_is_enabled,
1164
1165         .intr_clear = mei_txe_intr_clear,
1166         .intr_enable = mei_txe_intr_enable,
1167         .intr_disable = mei_txe_intr_disable,
1168
1169         .hbuf_free_slots = mei_txe_hbuf_empty_slots,
1170         .hbuf_is_ready = mei_txe_is_input_ready,
1171         .hbuf_max_len = mei_txe_hbuf_max_len,
1172
1173         .write = mei_txe_write,
1174
1175         .rdbuf_full_slots = mei_txe_count_full_read_slots,
1176         .read_hdr = mei_txe_read_hdr,
1177
1178         .read = mei_txe_read,
1179
1180 };
1181
1182 /**
1183  * mei_txe_dev_init - allocates and initializes txe hardware specific structure
1184  *
1185  * @pdev: pci device
1186  *
1187  * Return: struct mei_device * on success or NULL
1188  */
1189 struct mei_device *mei_txe_dev_init(struct pci_dev *pdev)
1190 {
1191         struct mei_device *dev;
1192         struct mei_txe_hw *hw;
1193
1194         dev = kzalloc(sizeof(struct mei_device) +
1195                          sizeof(struct mei_txe_hw), GFP_KERNEL);
1196         if (!dev)
1197                 return NULL;
1198
1199         mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops);
1200
1201         hw = to_txe_hw(dev);
1202
1203         init_waitqueue_head(&hw->wait_aliveness_resp);
1204
1205         return dev;
1206 }
1207
1208 /**
1209  * mei_txe_setup_satt2 - SATT2 configuration for DMA support.
1210  *
1211  * @dev:   the device structure
1212  * @addr:  physical address start of the range
1213  * @range: physical range size
1214  *
1215  * Return: 0 on success an error code otherwise
1216  */
1217 int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range)
1218 {
1219         struct mei_txe_hw *hw = to_txe_hw(dev);
1220
1221         u32 lo32 = lower_32_bits(addr);
1222         u32 hi32 = upper_32_bits(addr);
1223         u32 ctrl;
1224
1225         /* SATT is limited to 36 Bits */
1226         if (hi32 & ~0xF)
1227                 return -EINVAL;
1228
1229         /* SATT has to be 16Byte aligned */
1230         if (lo32 & 0xF)
1231                 return -EINVAL;
1232
1233         /* SATT range has to be 4Bytes aligned */
1234         if (range & 0x4)
1235                 return -EINVAL;
1236
1237         /* SATT is limited to 32 MB range*/
1238         if (range > SATT_RANGE_MAX)
1239                 return -EINVAL;
1240
1241         ctrl = SATT2_CTRL_VALID_MSK;
1242         ctrl |= hi32  << SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT;
1243
1244         mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range);
1245         mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32);
1246         mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl);
1247         dev_dbg(dev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n",
1248                 range, lo32, ctrl);
1249
1250         return 0;
1251 }