drivers/staging/rtl8192u/r8192U.h

   1 /*
   2  * This is part of rtl8187 OpenSource driver.
   3  * Copyright (C) Andrea Merello 2004-2005  <andrea.merello@gmail.com>
   4  * Released under the terms of GPL (General Public Licence)
   5  *
   6  * Parts of this driver are based on the GPL part of the
   7  * official realtek driver
   8  *
   9  * Parts of this driver are based on the rtl8192 driver skeleton
  10  * from Patric Schenke & Andres Salomon
  11  *
  12  * Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
  13  *
  14  * We want to thank the Authors of those projects and the Ndiswrapper
  15  * project Authors.
  16  */
  17
  18 #ifndef R819xU_H
  19 #define R819xU_H
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 #include <linux/ioport.h>
  24 #include <linux/sched.h>
  25 #include <linux/types.h>
  26 #include <linux/slab.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/usb.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/delay.h>
  31 #include <linux/rtnetlink.h>
  32 #include <linux/wireless.h>
  33 #include <linux/timer.h>
  34 #include <linux/proc_fs.h>
  35 #include <linux/if_arp.h>
  36 #include <linux/random.h>
  37 #include <asm/io.h>
  38 #include "ieee80211/ieee80211.h"
  39
  40 #define RTL8192U
  41 #define RTL819xU_MODULE_NAME "rtl819xU"
  42 /* HW security */
  43 #define MAX_KEY_LEN     61
  44 #define KEY_BUF_SIZE    5
  45
  46 #define Rx_Smooth_Factor                20
  47 #define DMESG(x, a...)
  48 #define DMESGW(x, a...)
  49 #define DMESGE(x, a...)
  50 extern u32 rt_global_debug_component;
  51 #define RT_TRACE(component, x, args...) \
  52         do {                                                    \
  53                 if (rt_global_debug_component & component)      \
  54                         pr_debug("RTL8192U: " x "\n", ##args);  \
  55         } while (0)
  56
  57 #define COMP_TRACE              BIT(0)  /* Function call tracing. */
  58 #define COMP_DBG                BIT(1)
  59 #define COMP_INIT               BIT(2)  /* Driver initialization/halt/reset. */
  60
  61
  62 #define COMP_RECV               BIT(3)  /* Receive data path. */
  63 #define COMP_SEND               BIT(4)  /* Send data path. */
  64 #define COMP_IO                 BIT(5)
  65 /* 802.11 Power Save mode or System/Device Power state. */
  66 #define COMP_POWER              BIT(6)
  67 /* 802.11 link related: join/start BSS, leave BSS. */
  68 #define COMP_EPROM              BIT(7)
  69 #define COMP_SWBW               BIT(8)  /* Bandwidth switch. */
  70 #define COMP_POWER_TRACKING     BIT(9)  /* 8190 TX Power Tracking */
  71 #define COMP_TURBO              BIT(10) /* Turbo Mode */
  72 #define COMP_QOS                BIT(11)
  73 #define COMP_RATE               BIT(12) /* Rate Adaptive mechanism */
  74 #define COMP_RM                 BIT(13) /* Radio Measurement */
  75 #define COMP_DIG                BIT(14)
  76 #define COMP_PHY                BIT(15)
  77 #define COMP_CH                 BIT(16) /* Channel setting debug */
  78 #define COMP_TXAGC              BIT(17) /* Tx power */
  79 #define COMP_HIPWR              BIT(18) /* High Power Mechanism */
  80 #define COMP_HALDM              BIT(19) /* HW Dynamic Mechanism */
  81 #define COMP_SEC                BIT(20) /* Event handling */
  82 #define COMP_LED                BIT(21)
  83 #define COMP_RF                 BIT(22)
  84 #define COMP_RXDESC             BIT(23) /* Rx desc information for SD3 debug */
  85
  86 /* 11n or 8190 specific code */
  87
  88 #define COMP_FIRMWARE           BIT(24) /* Firmware downloading */
  89 #define COMP_HT                 BIT(25) /* 802.11n HT related information */
  90 #define COMP_AMSDU              BIT(26) /* A-MSDU Debugging */
  91 #define COMP_SCAN               BIT(27)
  92 #define COMP_DOWN               BIT(29) /* rm driver module */
  93 #define COMP_RESET              BIT(30) /* Silent reset */
  94 #define COMP_ERR                BIT(31) /* Error out, always on */
  95
  96 #define RTL819x_DEBUG
  97 #ifdef RTL819x_DEBUG
  98 #define RTL8192U_ASSERT(expr) \
  99         do {                                                            \
 100                 if (!(expr)) {                                          \
 101                         pr_debug("Assertion failed! %s, %s, %s, line = %d\n", \
 102                                  #expr, __FILE__, __func__, __LINE__);  \
 103                 }                                                       \
 104         } while (0)
 105 /*
 106  * Debug out data buf.
 107  * If you want to print DATA buffer related BA,
 108  * please set ieee80211_debug_level to DATA|BA
 109  */
 110 #define RT_DEBUG_DATA(level, data, datalen) \
 111         do {                                                            \
 112                 if ((rt_global_debug_component & (level)) == (level)) { \
 113                         int i;                                          \
 114                         u8 *pdata = (u8 *) data;                        \
 115                         pr_debug("RTL8192U: %s()\n", __func__);         \
 116                         for (i = 0; i < (int)(datalen); i++) {          \
 117                                 printk("%2x ", pdata[i]);               \
 118                                 if ((i+1)%16 == 0)                      \
 119                                         printk("\n");                   \
 120                         }                                               \
 121                         printk("\n");                                   \
 122                 }                                                       \
 123         } while (0)
 124 #else
 125 #define RTL8192U_ASSERT(expr) do {} while (0)
 126 #define RT_DEBUG_DATA(level, data, datalen) do {} while (0)
 127 #endif /* RTL8169_DEBUG */
 128
 129
 130 /* Queue Select Value in TxDesc */
 131 #define QSLT_BK                                 0x1
 132 #define QSLT_BE                                 0x0
 133 #define QSLT_VI                                 0x4
 134 #define QSLT_VO                                 0x6
 135 #define QSLT_BEACON                             0x10
 136 #define QSLT_HIGH                               0x11
 137 #define QSLT_MGNT                               0x12
 138 #define QSLT_CMD                                0x13
 139
 140 #define DESC90_RATE1M                           0x00
 141 #define DESC90_RATE2M                           0x01
 142 #define DESC90_RATE5_5M                         0x02
 143 #define DESC90_RATE11M                          0x03
 144 #define DESC90_RATE6M                           0x04
 145 #define DESC90_RATE9M                           0x05
 146 #define DESC90_RATE12M                          0x06
 147 #define DESC90_RATE18M                          0x07
 148 #define DESC90_RATE24M                          0x08
 149 #define DESC90_RATE36M                          0x09
 150 #define DESC90_RATE48M                          0x0a
 151 #define DESC90_RATE54M                          0x0b
 152 #define DESC90_RATEMCS0                         0x00
 153 #define DESC90_RATEMCS1                         0x01
 154 #define DESC90_RATEMCS2                         0x02
 155 #define DESC90_RATEMCS3                         0x03
 156 #define DESC90_RATEMCS4                         0x04
 157 #define DESC90_RATEMCS5                         0x05
 158 #define DESC90_RATEMCS6                         0x06
 159 #define DESC90_RATEMCS7                         0x07
 160 #define DESC90_RATEMCS8                         0x08
 161 #define DESC90_RATEMCS9                         0x09
 162 #define DESC90_RATEMCS10                        0x0a
 163 #define DESC90_RATEMCS11                        0x0b
 164 #define DESC90_RATEMCS12                        0x0c
 165 #define DESC90_RATEMCS13                        0x0d
 166 #define DESC90_RATEMCS14                        0x0e
 167 #define DESC90_RATEMCS15                        0x0f
 168 #define DESC90_RATEMCS32                        0x20
 169
 170 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
 171
 172 #define IEEE80211_WATCH_DOG_TIME    2000
 173 #define         PHY_Beacon_RSSI_SLID_WIN_MAX            10
 174 /* For Tx Power Tracking */
 175 #define         OFDM_Table_Length       19
 176 #define CCK_Table_length        12
 177
 178 /* For rtl819x */
 179 typedef struct _tx_desc_819x_usb {
 180         /* DWORD 0 */
 181         u16     PktSize;
 182         u8      Offset;
 183         u8      Reserved0:3;
 184         u8      CmdInit:1;
 185         u8      LastSeg:1;
 186         u8      FirstSeg:1;
 187         u8      LINIP:1;
 188         u8      OWN:1;
 189
 190         /* DWORD 1 */
 191         u8      TxFWInfoSize;
 192         u8      RATid:3;
 193         u8      DISFB:1;
 194         u8      USERATE:1;
 195         u8      MOREFRAG:1;
 196         u8      NoEnc:1;
 197         u8      PIFS:1;
 198         u8      QueueSelect:5;
 199         u8      NoACM:1;
 200         u8      Reserved1:2;
 201         u8      SecCAMID:5;
 202         u8      SecDescAssign:1;
 203         u8      SecType:2;
 204
 205         /* DWORD 2 */
 206         u16     TxBufferSize;
 207         u8      ResvForPaddingLen:7;
 208         u8      Reserved3:1;
 209         u8      Reserved4;
 210
 211         /* DWORD 3, 4, 5 */
 212         u32     Reserved5;
 213         u32     Reserved6;
 214         u32     Reserved7;
 215 } tx_desc_819x_usb, *ptx_desc_819x_usb;
 216
 217 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 218 typedef struct _tx_desc_819x_usb_aggr_subframe {
 219         /* DWORD 0 */
 220         u16     PktSize;
 221         u8      Offset;
 222         u8      TxFWInfoSize;
 223
 224         /* DWORD 1 */
 225         u8      RATid:3;
 226         u8      DISFB:1;
 227         u8      USERATE:1;
 228         u8      MOREFRAG:1;
 229         u8      NoEnc:1;
 230         u8      PIFS:1;
 231         u8      QueueSelect:5;
 232         u8      NoACM:1;
 233         u8      Reserved1:2;
 234         u8      SecCAMID:5;
 235         u8      SecDescAssign:1;
 236         u8      SecType:2;
 237         u8      PacketID:7;
 238         u8      OWN:1;
 239 } tx_desc_819x_usb_aggr_subframe, *ptx_desc_819x_usb_aggr_subframe;
 240 #endif
 241
 242
 243
 244 typedef struct _tx_desc_cmd_819x_usb {
 245         /* DWORD 0 */
 246         u16     Reserved0;
 247         u8      Reserved1;
 248         u8      Reserved2:3;
 249         u8      CmdInit:1;
 250         u8      LastSeg:1;
 251         u8      FirstSeg:1;
 252         u8      LINIP:1;
 253         u8      OWN:1;
 254
 255         /* DOWRD 1 */
 256         u8      TxFWInfoSize;
 257         u8      Reserved3;
 258         u8      QueueSelect;
 259         u8      Reserved4;
 260
 261         /* DOWRD 2 */
 262         u16     TxBufferSize;
 263         u16     Reserved5;
 264
 265         /* DWORD 3, 4, 5 */
 266         u32     Reserved6;
 267         u32     Reserved7;
 268         u32     Reserved8;
 269 } tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
 270
 271
 272 typedef struct _tx_fwinfo_819x_usb {
 273         /* DOWRD 0 */
 274         u8      TxRate:7;
 275         u8      CtsEnable:1;
 276         u8      RtsRate:7;
 277         u8      RtsEnable:1;
 278         u8      TxHT:1;
 279         u8      Short:1;        /* Error out, always on */
 280         u8      TxBandwidth:1;  /* Used for HT MCS rate only */
 281         u8      TxSubCarrier:2; /* Used for legacy OFDM rate only */
 282         u8      STBC:2;
 283         u8      AllowAggregation:1;
 284         /* Interpret RtsRate field as high throughput data rate */
 285         u8      RtsHT:1;
 286         u8      RtsShort:1;     /* Short PLCP for CCK or short GI for 11n MCS */
 287         u8      RtsBandwidth:1; /* Used for HT MCS rate only */
 288         u8      RtsSubcarrier:2;/* Used for legacy OFDM rate only */
 289         u8      RtsSTBC:2;
 290         /* Enable firmware to recalculate and assign packet duration */
 291         u8      EnableCPUDur:1;
 292
 293         /* DWORD 1 */
 294         u32     RxMF:2;
 295         u32     RxAMD:3;
 296         /* 1 indicate Tx info gathered by firmware and returned by Rx Cmd */
 297         u32     TxPerPktInfoFeedback:1;
 298         u32     Reserved1:2;
 299         u32     TxAGCOffSet:4;
 300         u32     TxAGCSign:1;
 301         u32     Tx_INFO_RSVD:6;
 302         u32     PacketID:13;
 303 } tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
 304
 305 struct rtl8192_rx_info {
 306         struct urb *urb;
 307         struct net_device *dev;
 308         u8 out_pipe;
 309 };
 310
 311 typedef struct rx_desc_819x_usb {
 312         /* DOWRD 0 */
 313         u16                 Length:14;
 314         u16                 CRC32:1;
 315         u16                 ICV:1;
 316         u8                  RxDrvInfoSize;
 317         u8                  Shift:2;
 318         u8                  PHYStatus:1;
 319         u8                  SWDec:1;
 320         u8                  Reserved1:4;
 321
 322         /* DWORD 1 */
 323         u32                 Reserved2;
 324 } rx_desc_819x_usb, *prx_desc_819x_usb;
 325
 326 #ifdef USB_RX_AGGREGATION_SUPPORT
 327 typedef struct _rx_desc_819x_usb_aggr_subframe {
 328         /* DOWRD 0 */
 329         u16                     Length:14;
 330         u16                     CRC32:1;
 331         u16                     ICV:1;
 332         u8                      Offset;
 333         u8                      RxDrvInfoSize;
 334         /* DOWRD 1 */
 335         u8                      Shift:2;
 336         u8                      PHYStatus:1;
 337         u8                      SWDec:1;
 338         u8                      Reserved1:4;
 339         u8                      Reserved2;
 340         u16                     Reserved3;
 341 } rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe;
 342 #endif
 343
 344 typedef struct rx_drvinfo_819x_usb {
 345         /* DWORD 0 */
 346         u16                 Reserved1:12;
 347         u16                 PartAggr:1;
 348         u16                 FirstAGGR:1;
 349         u16                 Reserved2:2;
 350
 351         u8                  RxRate:7;
 352         u8                  RxHT:1;
 353
 354         u8                  BW:1;
 355         u8                  SPLCP:1;
 356         u8                  Reserved3:2;
 357         u8                  PAM:1;
 358         u8                  Mcast:1;
 359         u8                  Bcast:1;
 360         u8                  Reserved4:1;
 361
 362         /* DWORD 1 */
 363         u32                  TSFL;
 364
 365 } rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
 366
 367 /* Support till 64 bit bus width OS */
 368 #define MAX_DEV_ADDR_SIZE               8
 369 /* For RTL8190 */
 370 #define MAX_FIRMWARE_INFORMATION_SIZE   32
 371 #define MAX_802_11_HEADER_LENGTH        (40 + MAX_FIRMWARE_INFORMATION_SIZE)
 372 #define ENCRYPTION_MAX_OVERHEAD         128
 373 #define USB_HWDESC_HEADER_LEN           sizeof(tx_desc_819x_usb)
 374 #define TX_PACKET_SHIFT_BYTES           (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
 375 #define MAX_FRAGMENT_COUNT              8
 376 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 377 #define MAX_TRANSMIT_BUFFER_SIZE                        32000
 378 #else
 379 #define MAX_TRANSMIT_BUFFER_SIZE                        8000
 380 #endif
 381 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 382 #define TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES (sizeof(tx_desc_819x_usb_aggr_subframe) + sizeof(tx_fwinfo_819x_usb))
 383 #endif
 384 /* Octets for crc32 (FCS, ICV) */
 385 #define scrclng                                 4
 386
 387 typedef enum rf_optype {
 388         RF_OP_By_SW_3wire = 0,
 389         RF_OP_By_FW,
 390         RF_OP_MAX
 391 } rf_op_type;
 392 /* 8190 Loopback Mode definition */
 393 typedef enum _rtl819xUsb_loopback {
 394         RTL819xU_NO_LOOPBACK = 0,
 395         RTL819xU_MAC_LOOPBACK = 1,
 396         RTL819xU_DMA_LOOPBACK = 2,
 397         RTL819xU_CCK_LOOPBACK = 3,
 398 } rtl819xUsb_loopback_e;
 399
 400 /* due to rtl8192 firmware */
 401 typedef enum _desc_packet_type_e {
 402         DESC_PACKET_TYPE_INIT = 0,
 403         DESC_PACKET_TYPE_NORMAL = 1,
 404 } desc_packet_type_e;
 405
 406 typedef enum _firmware_status {
 407         FW_STATUS_0_INIT = 0,
 408         FW_STATUS_1_MOVE_BOOT_CODE = 1,
 409         FW_STATUS_2_MOVE_MAIN_CODE = 2,
 410         FW_STATUS_3_TURNON_CPU = 3,
 411         FW_STATUS_4_MOVE_DATA_CODE = 4,
 412         FW_STATUS_5_READY = 5,
 413 } firmware_status_e;
 414
 415 typedef struct _rt_firmare_seg_container {
 416         u16     seg_size;
 417         u8      *seg_ptr;
 418 } fw_seg_container, *pfw_seg_container;
 419 typedef struct _rt_firmware {
 420         firmware_status_e firmware_status;
 421         u16               cmdpacket_frag_thresold;
 422 #define RTL8190_MAX_FIRMWARE_CODE_SIZE  64000
 423         u8                firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];
 424         u16               firmware_buf_size;
 425 } rt_firmware, *prt_firmware;
 426
 427 /* Add this to 9100 bytes to receive A-MSDU from RT-AP */
 428 #define MAX_RECEIVE_BUFFER_SIZE 9100
 429
 430 typedef struct _rt_firmware_info_819xUsb {
 431         u8              sz_info[16];
 432 } rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
 433
 434 /* Firmware Queue Layout */
 435 #define NUM_OF_FIRMWARE_QUEUE           10
 436 #define NUM_OF_PAGES_IN_FW              0x100
 437
 438 #ifdef USE_ONE_PIPE
 439 #define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x000
 440 #define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x000
 441 #define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x0ff
 442 #define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x000
 443 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 444 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x0
 445 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x00
 446 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 447 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x0
 448 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x00
 449 #else
 450
 451 #define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x020
 452 #define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x020
 453 #define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x040
 454 #define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x040
 455 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 456 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x4
 457 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x20
 458 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 459 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x4
 460 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x18
 461
 462 #endif
 463
 464 #define APPLIED_RESERVED_QUEUE_IN_FW    0x80000000
 465 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT     0x00
 466 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT     0x08
 467 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT     0x10
 468 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT     0x18
 469 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT   0x10
 470 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT    0x08
 471 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT    0x00
 472 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT    0x08
 473
 474 /*
 475  * =================================================================
 476  * =================================================================
 477  */
 478
 479 #define EPROM_93c46 0
 480 #define EPROM_93c56 1
 481
 482 #define DEFAULT_FRAG_THRESHOLD 2342U
 483 #define MIN_FRAG_THRESHOLD     256U
 484 #define DEFAULT_BEACONINTERVAL 0x64U
 485 #define DEFAULT_BEACON_ESSID "Rtl819xU"
 486
 487 #define DEFAULT_SSID ""
 488 #define DEFAULT_RETRY_RTS 7
 489 #define DEFAULT_RETRY_DATA 7
 490 #define PRISM_HDR_SIZE 64
 491
 492 #define         PHY_RSSI_SLID_WIN_MAX                           100
 493
 494
 495 typedef enum _WIRELESS_MODE {
 496         WIRELESS_MODE_UNKNOWN = 0x00,
 497         WIRELESS_MODE_A = 0x01,
 498         WIRELESS_MODE_B = 0x02,
 499         WIRELESS_MODE_G = 0x04,
 500         WIRELESS_MODE_AUTO = 0x08,
 501         WIRELESS_MODE_N_24G = 0x10,
 502         WIRELESS_MODE_N_5G = 0x20
 503 } WIRELESS_MODE;
 504
 505
 506 #define RTL_IOCTL_WPA_SUPPLICANT                (SIOCIWFIRSTPRIV + 30)
 507
 508 typedef struct buffer {
 509         struct buffer *next;
 510         u32 *buf;
 511
 512 } buffer;
 513
 514 typedef struct rtl_reg_debug {
 515         unsigned int  cmd;
 516         struct {
 517                 unsigned char type;
 518                 unsigned char addr;
 519                 unsigned char page;
 520                 unsigned char length;
 521         } head;
 522         unsigned char buf[0xff];
 523 } rtl_reg_debug;
 524
 525
 526
 527
 528
 529
 530 typedef struct _rt_9x_tx_rate_history {
 531         u32             cck[4];
 532         u32             ofdm[8];
 533         u32             ht_mcs[4][16];
 534 } rt_tx_rahis_t, *prt_tx_rahis_t;
 535 typedef struct _RT_SMOOTH_DATA_4RF {
 536         s8    elements[4][100]; /* array to store values */
 537         u32     index;            /* index to current array to store */
 538         u32     TotalNum;         /* num of valid elements */
 539         u32     TotalVal[4];      /* sum of valid elements */
 540 } RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
 541
 542 /* This maybe changed for D-cut larger aggregation size */
 543 #define MAX_8192U_RX_SIZE                       8192
 544 /* Stats seems messed up, clean it ASAP */
 545 typedef struct Stats {
 546         unsigned long txrdu;
 547         unsigned long rxok;
 548         unsigned long rxframgment;
 549         unsigned long rxurberr;
 550         unsigned long rxstaterr;
 551         /* 0: Total, 1: OK, 2: CRC, 3: ICV */
 552         unsigned long received_rate_histogram[4][32];
 553         /* 0: Long preamble/GI, 1: Short preamble/GI */
 554         unsigned long received_preamble_GI[2][32];
 555         /* level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K) */
 556         unsigned long rx_AMPDUsize_histogram[5];
 557         /* level: (<5), (5~10), (10~20), (20~40), (>40) */
 558         unsigned long rx_AMPDUnum_histogram[5];
 559         unsigned long numpacket_matchbssid;
 560         unsigned long numpacket_toself;
 561         unsigned long num_process_phyinfo;
 562         unsigned long numqry_phystatus;
 563         unsigned long numqry_phystatusCCK;
 564         unsigned long numqry_phystatusHT;
 565         /* 0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate */
 566         unsigned long received_bwtype[5];
 567         unsigned long txnperr;
 568         unsigned long txnpdrop;
 569         unsigned long txresumed;
 570         unsigned long txnpokint;
 571         unsigned long txoverflow;
 572         unsigned long txlpokint;
 573         unsigned long txlpdrop;
 574         unsigned long txlperr;
 575         unsigned long txbeokint;
 576         unsigned long txbedrop;
 577         unsigned long txbeerr;
 578         unsigned long txbkokint;
 579         unsigned long txbkdrop;
 580         unsigned long txbkerr;
 581         unsigned long txviokint;
 582         unsigned long txvidrop;
 583         unsigned long txvierr;
 584         unsigned long txvookint;
 585         unsigned long txvodrop;
 586         unsigned long txvoerr;
 587         unsigned long txbeaconokint;
 588         unsigned long txbeacondrop;
 589         unsigned long txbeaconerr;
 590         unsigned long txmanageokint;
 591         unsigned long txmanagedrop;
 592         unsigned long txmanageerr;
 593         unsigned long txdatapkt;
 594         unsigned long txfeedback;
 595         unsigned long txfeedbackok;
 596
 597         unsigned long txoktotal;
 598         unsigned long txokbytestotal;
 599         unsigned long txokinperiod;
 600         unsigned long txmulticast;
 601         unsigned long txbytesmulticast;
 602         unsigned long txbroadcast;
 603         unsigned long txbytesbroadcast;
 604         unsigned long txunicast;
 605         unsigned long txbytesunicast;
 606
 607         unsigned long rxoktotal;
 608         unsigned long rxbytesunicast;
 609         unsigned long txfeedbackfail;
 610         unsigned long txerrtotal;
 611         unsigned long txerrbytestotal;
 612         unsigned long txerrmulticast;
 613         unsigned long txerrbroadcast;
 614         unsigned long txerrunicast;
 615         unsigned long txretrycount;
 616         unsigned long txfeedbackretry;
 617         u8            last_packet_rate;
 618         unsigned long slide_signal_strength[100];
 619         unsigned long slide_evm[100];
 620         /* For recording sliding window's RSSI value */
 621         unsigned long slide_rssi_total;
 622         /* For recording sliding window's EVM value */
 623         unsigned long slide_evm_total;
 624         /* Transformed in dbm. Beautified signal strength for UI, not correct */
 625         long signal_strength;
 626         long signal_quality;
 627         long last_signal_strength_inpercent;
 628         /* Correct smoothed ss in dbm, only used in driver
 629          * to report real power now */
 630         long recv_signal_power;
 631         u8 rx_rssi_percentage[4];
 632         u8 rx_evm_percentage[2];
 633         long rxSNRdB[4];
 634         rt_tx_rahis_t txrate;
 635         /* For beacon RSSI */
 636         u32 Slide_Beacon_pwdb[100];
 637         u32 Slide_Beacon_Total;
 638         RT_SMOOTH_DATA_4RF              cck_adc_pwdb;
 639
 640         u32     CurrentShowTxate;
 641 } Stats;
 642
 643
 644 /* Bandwidth Offset */
 645 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
 646 #define HAL_PRIME_CHNL_OFFSET_LOWER                     1
 647 #define HAL_PRIME_CHNL_OFFSET_UPPER                     2
 648
 649
 650 typedef struct  ChnlAccessSetting {
 651         u16 SIFS_Timer;
 652         u16 DIFS_Timer;
 653         u16 SlotTimeTimer;
 654         u16 EIFS_Timer;
 655         u16 CWminIndex;
 656         u16 CWmaxIndex;
 657 } *PCHANNEL_ACCESS_SETTING, CHANNEL_ACCESS_SETTING;
 658
 659 typedef struct _BB_REGISTER_DEFINITION {
 660         /* set software control:        0x870~0x877 [8 bytes]  */
 661         u32 rfintfs;
 662         /* readback data:               0x8e0~0x8e7 [8 bytes]  */
 663         u32 rfintfi;
 664         /* output data:                 0x860~0x86f [16 bytes] */
 665         u32 rfintfo;
 666         /* output enable:               0x860~0x86f [16 bytes] */
 667         u32 rfintfe;
 668         /* LSSI data:                   0x840~0x84f [16 bytes] */
 669         u32 rf3wireOffset;
 670         /* BB Band Select:              0x878~0x87f [8 bytes]  */
 671         u32 rfLSSI_Select;
 672         /* Tx gain stage:               0x80c~0x80f [4 bytes]  */
 673         u32 rfTxGainStage;
 674         /* wire parameter control1:     0x820~0x823, 0x828~0x82b,
 675          *                              0x830~0x833, 0x838~0x83b [16 bytes] */
 676         u32 rfHSSIPara1;
 677         /* wire parameter control2:     0x824~0x827, 0x82c~0x82f,
 678          *                              0x834~0x837, 0x83c~0x83f [16 bytes] */
 679         u32 rfHSSIPara2;
 680         /* Tx Rx antenna control:       0x858~0x85f [16 bytes] */
 681         u32 rfSwitchControl;
 682         /* AGC parameter control1:      0xc50~0xc53, 0xc58~0xc5b,
 683          *                              0xc60~0xc63, 0xc68~0xc6b [16 bytes] */
 684         u32 rfAGCControl1;
 685         /* AGC parameter control2:      0xc54~0xc57, 0xc5c~0xc5f,
 686          *                              0xc64~0xc67, 0xc6c~0xc6f [16 bytes] */
 687         u32 rfAGCControl2;
 688         /* OFDM Rx IQ imbalance matrix: 0xc14~0xc17, 0xc1c~0xc1f,
 689          *                              0xc24~0xc27, 0xc2c~0xc2f [16 bytes] */
 690         u32 rfRxIQImbalance;
 691         /* Rx IQ DC offset and Rx digital filter, Rx DC notch filter:
 692          *                              0xc10~0xc13, 0xc18~0xc1b,
 693          *                              0xc20~0xc23, 0xc28~0xc2b [16 bytes] */
 694         u32 rfRxAFE;
 695         /* OFDM Tx IQ imbalance matrix: 0xc80~0xc83, 0xc88~0xc8b,
 696          *                              0xc90~0xc93, 0xc98~0xc9b [16 bytes] */
 697         u32 rfTxIQImbalance;
 698         /* Tx IQ DC Offset and Tx DFIR type:
 699          *                              0xc84~0xc87, 0xc8c~0xc8f,
 700          *                              0xc94~0xc97, 0xc9c~0xc9f [16 bytes] */
 701         u32 rfTxAFE;
 702         /* LSSI RF readback data:       0x8a0~0x8af [16 bytes] */
 703         u32 rfLSSIReadBack;
 704 } BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
 705
 706 typedef enum _RT_RF_TYPE_819xU {
 707         RF_TYPE_MIN = 0,
 708         RF_8225,
 709         RF_8256,
 710         RF_8258,
 711         RF_PSEUDO_11N = 4,
 712 } RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
 713
 714 typedef struct _rate_adaptive {
 715         u8                              rate_adaptive_disabled;
 716         u8                              ratr_state;
 717         u16                             reserve;
 718
 719         u32                             high_rssi_thresh_for_ra;
 720         u32                             high2low_rssi_thresh_for_ra;
 721         u8                              low2high_rssi_thresh_for_ra40M;
 722         u32                             low_rssi_thresh_for_ra40M;
 723         u8                              low2high_rssi_thresh_for_ra20M;
 724         u32                             low_rssi_thresh_for_ra20M;
 725         u32                             upper_rssi_threshold_ratr;
 726         u32                             middle_rssi_threshold_ratr;
 727         u32                             low_rssi_threshold_ratr;
 728         u32                             low_rssi_threshold_ratr_40M;
 729         u32                             low_rssi_threshold_ratr_20M;
 730         u8                              ping_rssi_enable;
 731         u32                             ping_rssi_ratr;
 732         u32                             ping_rssi_thresh_for_ra;
 733         u32                             last_ratr;
 734
 735 } rate_adaptive, *prate_adaptive;
 736
 737 #define TxBBGainTableLength 37
 738 #define CCKTxBBGainTableLength 23
 739
 740 typedef struct _txbbgain_struct {
 741         long    txbb_iq_amplifygain;
 742         u32     txbbgain_value;
 743 } txbbgain_struct, *ptxbbgain_struct;
 744
 745 typedef struct _ccktxbbgain_struct {
 746         /* The value is from a22 to a29, one byte one time is much safer */
 747         u8      ccktxbb_valuearray[8];
 748 } ccktxbbgain_struct, *pccktxbbgain_struct;
 749
 750
 751 typedef struct _init_gain {
 752         u8                              xaagccore1;
 753         u8                              xbagccore1;
 754         u8                              xcagccore1;
 755         u8                              xdagccore1;
 756         u8                              cca;
 757
 758 } init_gain, *pinit_gain;
 759
 760 typedef struct _phy_ofdm_rx_status_report_819xusb {
 761         u8      trsw_gain_X[4];
 762         u8      pwdb_all;
 763         u8      cfosho_X[4];
 764         u8      cfotail_X[4];
 765         u8      rxevm_X[2];
 766         u8      rxsnr_X[4];
 767         u8      pdsnr_X[2];
 768         u8      csi_current_X[2];
 769         u8      csi_target_X[2];
 770         u8      sigevm;
 771         u8      max_ex_pwr;
 772         u8      sgi_en;
 773         u8  rxsc_sgien_exflg;
 774 } phy_sts_ofdm_819xusb_t;
 775
 776 typedef struct _phy_cck_rx_status_report_819xusb {
 777         /* For CCK rate descriptor. This is an unsigned 8:1 variable.
 778          * LSB bit presend 0.5. And MSB 7 bts presend a signed value.
 779          * Range from -64~+63.5. */
 780         u8      adc_pwdb_X[4];
 781         u8      sq_rpt;
 782         u8      cck_agc_rpt;
 783 } phy_sts_cck_819xusb_t;
 784
 785
 786 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag {
 787         u8                      reserved:4;
 788         u8                      rxsc:2;
 789         u8                      sgi_en:1;
 790         u8                      ex_intf_flag:1;
 791 } phy_ofdm_rx_status_rxsc_sgien_exintfflag;
 792
 793 typedef enum _RT_CUSTOMER_ID {
 794         RT_CID_DEFAULT = 0,
 795         RT_CID_8187_ALPHA0 = 1,
 796         RT_CID_8187_SERCOMM_PS = 2,
 797         RT_CID_8187_HW_LED = 3,
 798         RT_CID_8187_NETGEAR = 4,
 799         RT_CID_WHQL = 5,
 800         RT_CID_819x_CAMEO  = 6,
 801         RT_CID_819x_RUNTOP = 7,
 802         RT_CID_819x_Senao = 8,
 803         RT_CID_TOSHIBA = 9,
 804         RT_CID_819x_Netcore = 10,
 805         RT_CID_Nettronix = 11,
 806         RT_CID_DLINK = 12,
 807         RT_CID_PRONET = 13,
 808 } RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
 809
 810 /*
 811  * ==========================================================================
 812  * LED customization.
 813  * ==========================================================================
 814  */
 815
 816 typedef enum _LED_STRATEGY_8190 {
 817         SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
 818         SW_LED_MODE1, /* SW control for PCI Express */
 819         SW_LED_MODE2, /* SW control for Cameo. */
 820         SW_LED_MODE3, /* SW control for RunTop. */
 821         SW_LED_MODE4, /* SW control for Netcore. */
 822         /* HW control 2 LEDs, LED0 and LED1 (4 different control modes) */
 823         HW_LED,
 824 } LED_STRATEGY_8190, *PLED_STRATEGY_8190;
 825
 826 typedef enum _RESET_TYPE {
 827         RESET_TYPE_NORESET = 0x00,
 828         RESET_TYPE_NORMAL = 0x01,
 829         RESET_TYPE_SILENT = 0x02
 830 } RESET_TYPE;
 831
 832 /* The simple tx command OP code. */
 833 typedef enum _tag_TxCmd_Config_Index {
 834         TXCMD_TXRA_HISTORY_CTRL                         = 0xFF900000,
 835         TXCMD_RESET_TX_PKT_BUFF                         = 0xFF900001,
 836         TXCMD_RESET_RX_PKT_BUFF                         = 0xFF900002,
 837         TXCMD_SET_TX_DURATION                           = 0xFF900003,
 838         TXCMD_SET_RX_RSSI                                               = 0xFF900004,
 839         TXCMD_SET_TX_PWR_TRACKING                       = 0xFF900005,
 840         TXCMD_XXXX_CTRL,
 841 } DCMD_TXCMD_OP;
 842
 843 typedef struct r8192_priv {
 844         struct usb_device *udev;
 845         /* For maintain info from eeprom */
 846         short epromtype;
 847         u16 eeprom_vid;
 848         u16 eeprom_pid;
 849         u8  eeprom_CustomerID;
 850         u8  eeprom_ChannelPlan;
 851         RT_CUSTOMER_ID CustomerID;
 852         LED_STRATEGY_8190       LedStrategy;
 853         u8  txqueue_to_outpipemap[9];
 854         int irq;
 855         struct ieee80211_device *ieee80211;
 856
 857         /* O: rtl8192, 1: rtl8185 V B/C, 2: rtl8185 V D */
 858         short card_8192;
 859         /* If TCR reports card V B/C, this discriminates */
 860         u8 card_8192_version;
 861         short enable_gpio0;
 862         enum card_type {
 863                 PCI, MINIPCI, CARDBUS, USB
 864         } card_type;
 865         short hw_plcp_len;
 866         short plcp_preamble_mode;
 867
 868         spinlock_t irq_lock;
 869         spinlock_t tx_lock;
 870         struct mutex mutex;
 871
 872         u16 irq_mask;
 873         short chan;
 874         short sens;
 875         short max_sens;
 876
 877
 878         short up;
 879         /* If 1, allow bad crc frame, reception in monitor mode */
 880         short crcmon;
 881
 882         struct mutex wx_mutex;
 883
 884         u8 rf_type;                     /* 0: 1T2R, 1: 2T4R */
 885         RT_RF_TYPE_819xU rf_chip;
 886
 887         short (*rf_set_sens)(struct net_device *dev, short sens);
 888         u8 (*rf_set_chan)(struct net_device *dev, u8 ch);
 889         void (*rf_close)(struct net_device *dev);
 890         void (*rf_init)(struct net_device *dev);
 891         short promisc;
 892         /* Stats */
 893         struct Stats stats;
 894         struct iw_statistics wstats;
 895
 896         /* RX stuff */
 897         struct urb **rx_urb;
 898         struct urb **rx_cmd_urb;
 899 #ifdef THOMAS_BEACON
 900         u32 *oldaddr;
 901 #endif
 902 #ifdef THOMAS_TASKLET
 903         atomic_t irt_counter; /* count for irq_rx_tasklet */
 904 #endif
 905 #ifdef JACKSON_NEW_RX
 906         struct sk_buff **pp_rxskb;
 907         int     rx_inx;
 908 #endif
 909
 910        struct sk_buff_head rx_queue;
 911        struct sk_buff_head skb_queue;
 912        struct work_struct qos_activate;
 913         short  tx_urb_index;
 914         atomic_t tx_pending[0x10]; /* UART_PRIORITY + 1 */
 915
 916
 917         struct tasklet_struct irq_rx_tasklet;
 918         struct urb *rxurb_task;
 919
 920         /* Tx Related variables */
 921         u16     ShortRetryLimit;
 922         u16     LongRetryLimit;
 923         u32     TransmitConfig;
 924         u8      RegCWinMin;     /* For turbo mode CW adaptive */
 925
 926         u32     LastRxDescTSFHigh;
 927         u32     LastRxDescTSFLow;
 928
 929
 930         /* Rx Related variables */
 931         u16     EarlyRxThreshold;
 932         u32     ReceiveConfig;
 933         u8      AcmControl;
 934
 935         u8      RFProgType;
 936
 937         u8 retry_data;
 938         u8 retry_rts;
 939         u16 rts;
 940
 941         struct  ChnlAccessSetting  ChannelAccessSetting;
 942         struct work_struct reset_wq;
 943
 944 /**********************************************************/
 945         /* For rtl819xUsb */
 946         u16     basic_rate;
 947         u8      short_preamble;
 948         u8      slot_time;
 949         bool    bDcut;
 950         bool bCurrentRxAggrEnable;
 951         u8 Rf_Mode;     /* For Firmware RF -R/W switch */
 952         prt_firmware            pFirmware;
 953         rtl819xUsb_loopback_e   LoopbackMode;
 954         u16 EEPROMTxPowerDiff;
 955         u8 EEPROMThermalMeter;
 956         u8 EEPROMPwDiff;
 957         u8 EEPROMCrystalCap;
 958         u8 EEPROM_Def_Ver;
 959         u8 EEPROMTxPowerLevelCCK;               /* CCK channel 1~14 */
 960         u8 EEPROMTxPowerLevelCCK_V1[3];
 961         u8 EEPROMTxPowerLevelOFDM24G[3];        /* OFDM 2.4G channel 1~14 */
 962         u8 EEPROMTxPowerLevelOFDM5G[24];        /* OFDM 5G */
 963
 964         /* PHY related */
 965         BB_REGISTER_DEFINITION_T PHYRegDef[4];  /* Radio A/B/C/D */
 966         /* Read/write are allow for following hardware information variables */
 967         u32     MCSTxPowerLevelOriginalOffset[6];
 968         u32     CCKTxPowerLevelOriginalOffset;
 969         u8      TxPowerLevelCCK[14];            /* CCK channel 1~14 */
 970         u8      TxPowerLevelOFDM24G[14];        /* OFDM 2.4G channel 1~14 */
 971         u8      TxPowerLevelOFDM5G[14];         /* OFDM 5G */
 972         u32     Pwr_Track;
 973         u8      TxPowerDiff;
 974         u8      AntennaTxPwDiff[2]; /* Antenna gain offset, 0: B, 1: C, 2: D */
 975         u8      CrystalCap;
 976         u8      ThermalMeter[2];    /* index 0: RFIC0, index 1: RFIC1 */
 977
 978         u8      CckPwEnl;
 979         /* Use to calculate PWBD */
 980         u8      bCckHighPower;
 981         long    undecorated_smoothed_pwdb;
 982
 983         /* For set channel */
 984         u8      SwChnlInProgress;
 985         u8      SwChnlStage;
 986         u8      SwChnlStep;
 987         u8      SetBWModeInProgress;
 988         HT_CHANNEL_WIDTH                CurrentChannelBW;
 989         u8      ChannelPlan;
 990         /* 8190 40MHz mode */
 991         /* Control channel sub-carrier */
 992         u8      nCur40MhzPrimeSC;
 993         /* Test for shorten RF configuration time.
 994          * We save RF reg0 in this variable to reduce RF reading. */
 995         u32                                     RfReg0Value[4];
 996         u8                                      NumTotalRFPath;
 997         bool                            brfpath_rxenable[4];
 998         /* RF set related */
 999         bool                            SetRFPowerStateInProgress;
1000         struct timer_list watch_dog_timer;
1001
1002         /* For dynamic mechanism */
1003         /* Tx Power Control for Near/Far Range */
1004         bool    bdynamic_txpower;
1005         bool    bDynamicTxHighPower;
1006         bool    bDynamicTxLowPower;
1007         bool    bLastDTPFlag_High;
1008         bool    bLastDTPFlag_Low;
1009
1010         bool    bstore_last_dtpflag;
1011         /* Define to discriminate on High power State or
1012          * on sitesurvey to change Tx gain index */
1013         bool    bstart_txctrl_bydtp;
1014         rate_adaptive rate_adaptive;
1015         /* TX power tracking
1016          * OPEN/CLOSE TX POWER TRACKING */
1017         txbbgain_struct txbbgain_table[TxBBGainTableLength];
1018         u8              txpower_count; /* For 6 sec do tracking again */
1019         bool            btxpower_trackingInit;
1020         u8              OFDM_index;
1021         u8              CCK_index;
1022         /* CCK TX Power Tracking */
1023         ccktxbbgain_struct      cck_txbbgain_table[CCKTxBBGainTableLength];
1024         ccktxbbgain_struct      cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
1025         u8 rfa_txpowertrackingindex;
1026         u8 rfa_txpowertrackingindex_real;
1027         u8 rfa_txpowertracking_default;
1028         u8 rfc_txpowertrackingindex;
1029         u8 rfc_txpowertrackingindex_real;
1030
1031         s8 cck_present_attentuation;
1032         u8 cck_present_attentuation_20Mdefault;
1033         u8 cck_present_attentuation_40Mdefault;
1034         s8 cck_present_attentuation_difference;
1035         bool btxpower_tracking;
1036         bool bcck_in_ch14;
1037         bool btxpowerdata_readfromEEPORM;
1038         u16     TSSI_13dBm;
1039         init_gain initgain_backup;
1040         u8 DefaultInitialGain[4];
1041         /* For EDCA Turbo mode */
1042         bool            bis_any_nonbepkts;
1043         bool            bcurrent_turbo_EDCA;
1044         bool            bis_cur_rdlstate;
1045         struct timer_list fsync_timer;
1046         bool bfsync_processing; /* 500ms Fsync timer is active or not */
1047         u32     rate_record;
1048         u32     rateCountDiffRecord;
1049         u32     ContinueDiffCount;
1050         bool bswitch_fsync;
1051
1052         u8      framesync;
1053         u32     framesyncC34;
1054         u8      framesyncMonitor;
1055         u16     nrxAMPDU_size;
1056         u8      nrxAMPDU_aggr_num;
1057
1058         /* For gpio */
1059          bool bHwRadioOff;
1060
1061         u32 reset_count;
1062         bool bpbc_pressed;
1063         u32 txpower_checkcnt;
1064         u32 txpower_tracking_callback_cnt;
1065         u8 thermal_read_val[40];
1066         u8 thermal_readback_index;
1067         u32 ccktxpower_adjustcnt_not_ch14;
1068         u32 ccktxpower_adjustcnt_ch14;
1069         u8 tx_fwinfo_force_subcarriermode;
1070         u8 tx_fwinfo_force_subcarrierval;
1071         /* For silent reset */
1072         RESET_TYPE      ResetProgress;
1073         bool            bForcedSilentReset;
1074         bool            bDisableNormalResetCheck;
1075         u16             TxCounter;
1076         u16             RxCounter;
1077         int             IrpPendingCount;
1078         bool            bResetInProgress;
1079         bool            force_reset;
1080         u8              InitialGainOperateType;
1081
1082         u16             SifsTime;
1083
1084         /* Define work item */
1085
1086         struct delayed_work update_beacon_wq;
1087         struct delayed_work watch_dog_wq;
1088         struct delayed_work txpower_tracking_wq;
1089         struct delayed_work rfpath_check_wq;
1090         struct delayed_work gpio_change_rf_wq;
1091         struct delayed_work initialgain_operate_wq;
1092         struct workqueue_struct *priv_wq;
1093 } r8192_priv;
1094
1095 /* For rtl8187B */
1096 typedef enum{
1097         BULK_PRIORITY = 0x01,
1098         LOW_PRIORITY,
1099         NORM_PRIORITY,
1100         VO_PRIORITY,
1101         VI_PRIORITY,
1102         BE_PRIORITY,
1103         BK_PRIORITY,
1104         RSVD2,
1105         RSVD3,
1106         BEACON_PRIORITY,
1107         HIGH_PRIORITY,
1108         MANAGE_PRIORITY,
1109         RSVD4,
1110         RSVD5,
1111         UART_PRIORITY
1112 } priority_t;
1113
1114 typedef enum {
1115         NIC_8192U = 1,
1116         NIC_8190P = 2,
1117         NIC_8192E = 3,
1118 } nic_t;
1119
1120 bool init_firmware(struct net_device *dev);
1121 short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1122 short rtl8192_tx(struct net_device *dev, struct sk_buff *skb);
1123
1124 u32 read_cam(struct net_device *dev, u8 addr);
1125 void write_cam(struct net_device *dev, u8 addr, u32 data);
1126
1127 int read_nic_byte(struct net_device *dev, int x, u8 *data);
1128 int read_nic_byte_E(struct net_device *dev, int x, u8 *data);
1129 int read_nic_dword(struct net_device *dev, int x, u32 *data);
1130 int read_nic_word(struct net_device *dev, int x, u16 *data);
1131 int write_nic_byte(struct net_device *dev, int x, u8 y);
1132 int write_nic_byte_E(struct net_device *dev, int x, u8 y);
1133 int write_nic_word(struct net_device *dev, int x, u16 y);
1134 int write_nic_dword(struct net_device *dev, int x, u32 y);
1135 void force_pci_posting(struct net_device *dev);
1136
1137 void rtl8192_rtx_disable(struct net_device *);
1138 void rtl8192_rx_enable(struct net_device *);
1139 void rtl8192_tx_enable(struct net_device *);
1140
1141 void rtl8192_disassociate(struct net_device *dev);
1142 void rtl8185_set_rf_pins_enable(struct net_device *dev, u32 a);
1143
1144 void rtl8192_set_anaparam(struct net_device *dev, u32 a);
1145 void rtl8185_set_anaparam2(struct net_device *dev, u32 a);
1146 void rtl8192_update_msr(struct net_device *dev);
1147 int rtl8192_down(struct net_device *dev);
1148 int rtl8192_up(struct net_device *dev);
1149 void rtl8192_commit(struct net_device *dev);
1150 void rtl8192_set_chan(struct net_device *dev, short ch);
1151 void write_phy(struct net_device *dev, u8 adr, u8 data);
1152 void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
1153 void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
1154 void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
1155 void rtl8192_set_rxconf(struct net_device *dev);
1156 void rtl819xusb_beacon_tx(struct net_device *dev, u16 tx_rate);
1157
1158 void EnableHWSecurityConfig8192(struct net_device *dev);
1159 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent);
1160
1161
1162 #endif