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Staging: comedi: Give the addi_apci_* drivers different driver names
[linux/fpc-iii.git] / drivers / serial / crisv10.c
blob31f172397af35f82061adada0faed4fff7a529fc
1 /*
2 * Serial port driver for the ETRAX 100LX chip
3 *
4 * Copyright (C) 1998-2007 Axis Communications AB
5 *
6 * Many, many authors. Based once upon a time on serial.c for 16x50.
7 *
8 */
9
10 static char *serial_version = "$Revision: 1.25 $";
11
12 #include <linux/types.h>
13 #include <linux/errno.h>
14 #include <linux/signal.h>
15 #include <linux/sched.h>
16 #include <linux/timer.h>
17 #include <linux/interrupt.h>
18 #include <linux/tty.h>
19 #include <linux/tty_flip.h>
20 #include <linux/major.h>
21 #include <linux/smp_lock.h>
22 #include <linux/string.h>
23 #include <linux/fcntl.h>
24 #include <linux/mm.h>
25 #include <linux/slab.h>
26 #include <linux/init.h>
27 #include <linux/kernel.h>
28 #include <linux/mutex.h>
29 #include <linux/bitops.h>
30 #include <linux/seq_file.h>
31 #include <linux/delay.h>
32 #include <linux/module.h>
33 #include <linux/uaccess.h>
34 #include <linux/io.h>
35
36 #include <asm/irq.h>
37 #include <asm/dma.h>
38 #include <asm/system.h>
39
40 #include <arch/svinto.h>
41
42 /* non-arch dependent serial structures are in linux/serial.h */
43 #include <linux/serial.h>
44 /* while we keep our own stuff (struct e100_serial) in a local .h file */
45 #include "crisv10.h"
46 #include <asm/fasttimer.h>
47 #include <arch/io_interface_mux.h>
48
49 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
50 #ifndef CONFIG_ETRAX_FAST_TIMER
51 #error "Enable FAST_TIMER to use SERIAL_FAST_TIMER"
52 #endif
53 #endif
54
55 #if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \
56 (CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0)
57 #error "RX_TIMEOUT_TICKS == 0 not allowed, use 1"
58 #endif
59
60 #if defined(CONFIG_ETRAX_RS485_ON_PA) && defined(CONFIG_ETRAX_RS485_ON_PORT_G)
61 #error "Disable either CONFIG_ETRAX_RS485_ON_PA or CONFIG_ETRAX_RS485_ON_PORT_G"
62 #endif
63
64 /*
65 * All of the compatibilty code so we can compile serial.c against
66 * older kernels is hidden in serial_compat.h
67 */
68 #if defined(LOCAL_HEADERS)
69 #include "serial_compat.h"
70 #endif
71
72 struct tty_driver *serial_driver;
73
74 /* number of characters left in xmit buffer before we ask for more */
75 #define WAKEUP_CHARS 256
76
77 //#define SERIAL_DEBUG_INTR
78 //#define SERIAL_DEBUG_OPEN
79 //#define SERIAL_DEBUG_FLOW
80 //#define SERIAL_DEBUG_DATA
81 //#define SERIAL_DEBUG_THROTTLE
82 //#define SERIAL_DEBUG_IO /* Debug for Extra control and status pins */
83 //#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */
84
85 /* Enable this to use serial interrupts to handle when you
86 expect the first received event on the serial port to
87 be an error, break or similar. Used to be able to flash IRMA
88 from eLinux */
89 #define SERIAL_HANDLE_EARLY_ERRORS
90
91 /* Currently 16 descriptors x 128 bytes = 2048 bytes */
92 #define SERIAL_DESCR_BUF_SIZE 256
93
94 #define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */
95 #define DEF_BAUD_BASE SERIAL_PRESCALE_BASE
96
97 /* We don't want to load the system with massive fast timer interrupt
98 * on high baudrates so limit it to 250 us (4kHz) */
99 #define MIN_FLUSH_TIME_USEC 250
100
101 /* Add an x here to log a lot of timer stuff */
102 #define TIMERD(x)
103 /* Debug details of interrupt handling */
104 #define DINTR1(x) /* irq on/off, errors */
105 #define DINTR2(x) /* tx and rx */
106 /* Debug flip buffer stuff */
107 #define DFLIP(x)
108 /* Debug flow control and overview of data flow */
109 #define DFLOW(x)
110 #define DBAUD(x)
111 #define DLOG_INT_TRIG(x)
112
113 //#define DEBUG_LOG_INCLUDED
114 #ifndef DEBUG_LOG_INCLUDED
115 #define DEBUG_LOG(line, string, value)
116 #else
117 struct debug_log_info
118 {
119 unsigned long time;
120 unsigned long timer_data;
121 // int line;
122 const char *string;
123 int value;
124 };
125 #define DEBUG_LOG_SIZE 4096
126
127 struct debug_log_info debug_log[DEBUG_LOG_SIZE];
128 int debug_log_pos = 0;
129
130 #define DEBUG_LOG(_line, _string, _value) do { \
131 if ((_line) == SERIAL_DEBUG_LINE) {\
132 debug_log_func(_line, _string, _value); \
133 }\
134 }while(0)
135
136 void debug_log_func(int line, const char *string, int value)
137 {
138 if (debug_log_pos < DEBUG_LOG_SIZE) {
139 debug_log[debug_log_pos].time = jiffies;
140 debug_log[debug_log_pos].timer_data = *R_TIMER_DATA;
141 // debug_log[debug_log_pos].line = line;
142 debug_log[debug_log_pos].string = string;
143 debug_log[debug_log_pos].value = value;
144 debug_log_pos++;
145 }
146 /*printk(string, value);*/
147 }
148 #endif
149
150 #ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS
151 /* Default number of timer ticks before flushing rx fifo
152 * When using "little data, low latency applications: use 0
153 * When using "much data applications (PPP)" use ~5
154 */
155 #define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5
156 #endif
157
158 unsigned long timer_data_to_ns(unsigned long timer_data);
159
160 static void change_speed(struct e100_serial *info);
161 static void rs_throttle(struct tty_struct * tty);
162 static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
163 static int rs_write(struct tty_struct *tty,
164 const unsigned char *buf, int count);
165 #ifdef CONFIG_ETRAX_RS485
166 static int e100_write_rs485(struct tty_struct *tty,
167 const unsigned char *buf, int count);
168 #endif
169 static int get_lsr_info(struct e100_serial *info, unsigned int *value);
170
171
172 #define DEF_BAUD 115200 /* 115.2 kbit/s */
173 #define STD_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
174 #define DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */
175 /* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */
176 #define DEF_TX 0x80 /* or SERIAL_CTRL_B */
177
178 /* offsets from R_SERIALx_CTRL */
179
180 #define REG_DATA 0
181 #define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */
182 #define REG_TR_DATA 0
183 #define REG_STATUS 1
184 #define REG_TR_CTRL 1
185 #define REG_REC_CTRL 2
186 #define REG_BAUD 3
187 #define REG_XOFF 4 /* this is a 32 bit register */
188
189 /* The bitfields are the same for all serial ports */
190 #define SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd)
191 #define SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail)
192 #define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
193 #define SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err)
194 #define SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun)
195
196 #define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK)
197
198 /* Values for info->errorcode */
199 #define ERRCODE_SET_BREAK (TTY_BREAK)
200 #define ERRCODE_INSERT 0x100
201 #define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK)
202
203 #define FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop;
204
205 /*
206 * General note regarding the use of IO_* macros in this file:
207 *
208 * We will use the bits defined for DMA channel 6 when using various
209 * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are
210 * the same for all channels (which of course they are).
211 *
212 * We will also use the bits defined for serial port 0 when writing commands
213 * to the different ports, as these bits too are the same for all ports.
214 */
215
216
217 /* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */
218 static const unsigned long e100_ser_int_mask = 0
219 #ifdef CONFIG_ETRAX_SERIAL_PORT0
220 | IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
221 #endif
222 #ifdef CONFIG_ETRAX_SERIAL_PORT1
223 | IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
224 #endif
225 #ifdef CONFIG_ETRAX_SERIAL_PORT2
226 | IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
227 #endif
228 #ifdef CONFIG_ETRAX_SERIAL_PORT3
229 | IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
230 #endif
231 ;
232 unsigned long r_alt_ser_baudrate_shadow = 0;
233
234 /* this is the data for the four serial ports in the etrax100 */
235 /* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */
236 /* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */
237
238 static struct e100_serial rs_table[] = {
239 { .baud = DEF_BAUD,
240 .ioport = (unsigned char *)R_SERIAL0_CTRL,
241 .irq = 1U << 12, /* uses DMA 6 and 7 */
242 .oclrintradr = R_DMA_CH6_CLR_INTR,
243 .ofirstadr = R_DMA_CH6_FIRST,
244 .ocmdadr = R_DMA_CH6_CMD,
245 .ostatusadr = R_DMA_CH6_STATUS,
246 .iclrintradr = R_DMA_CH7_CLR_INTR,
247 .ifirstadr = R_DMA_CH7_FIRST,
248 .icmdadr = R_DMA_CH7_CMD,
249 .idescradr = R_DMA_CH7_DESCR,
250 .flags = STD_FLAGS,
251 .rx_ctrl = DEF_RX,
252 .tx_ctrl = DEF_TX,
253 .iseteop = 2,
254 .dma_owner = dma_ser0,
255 .io_if = if_serial_0,
256 #ifdef CONFIG_ETRAX_SERIAL_PORT0
257 .enabled = 1,
258 #ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
259 .dma_out_enabled = 1,
260 .dma_out_nbr = SER0_TX_DMA_NBR,
261 .dma_out_irq_nbr = SER0_DMA_TX_IRQ_NBR,
262 .dma_out_irq_flags = IRQF_DISABLED,
263 .dma_out_irq_description = "serial 0 dma tr",
264 #else
265 .dma_out_enabled = 0,
266 .dma_out_nbr = UINT_MAX,
267 .dma_out_irq_nbr = 0,
268 .dma_out_irq_flags = 0,
269 .dma_out_irq_description = NULL,
270 #endif
271 #ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
272 .dma_in_enabled = 1,
273 .dma_in_nbr = SER0_RX_DMA_NBR,
274 .dma_in_irq_nbr = SER0_DMA_RX_IRQ_NBR,
275 .dma_in_irq_flags = IRQF_DISABLED,
276 .dma_in_irq_description = "serial 0 dma rec",
277 #else
278 .dma_in_enabled = 0,
279 .dma_in_nbr = UINT_MAX,
280 .dma_in_irq_nbr = 0,
281 .dma_in_irq_flags = 0,
282 .dma_in_irq_description = NULL,
283 #endif
284 #else
285 .enabled = 0,
286 .io_if_description = NULL,
287 .dma_out_enabled = 0,
288 .dma_in_enabled = 0
289 #endif
290
291 }, /* ttyS0 */
292 #ifndef CONFIG_SVINTO_SIM
293 { .baud = DEF_BAUD,
294 .ioport = (unsigned char *)R_SERIAL1_CTRL,
295 .irq = 1U << 16, /* uses DMA 8 and 9 */
296 .oclrintradr = R_DMA_CH8_CLR_INTR,
297 .ofirstadr = R_DMA_CH8_FIRST,
298 .ocmdadr = R_DMA_CH8_CMD,
299 .ostatusadr = R_DMA_CH8_STATUS,
300 .iclrintradr = R_DMA_CH9_CLR_INTR,
301 .ifirstadr = R_DMA_CH9_FIRST,
302 .icmdadr = R_DMA_CH9_CMD,
303 .idescradr = R_DMA_CH9_DESCR,
304 .flags = STD_FLAGS,
305 .rx_ctrl = DEF_RX,
306 .tx_ctrl = DEF_TX,
307 .iseteop = 3,
308 .dma_owner = dma_ser1,
309 .io_if = if_serial_1,
310 #ifdef CONFIG_ETRAX_SERIAL_PORT1
311 .enabled = 1,
312 .io_if_description = "ser1",
313 #ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
314 .dma_out_enabled = 1,
315 .dma_out_nbr = SER1_TX_DMA_NBR,
316 .dma_out_irq_nbr = SER1_DMA_TX_IRQ_NBR,
317 .dma_out_irq_flags = IRQF_DISABLED,
318 .dma_out_irq_description = "serial 1 dma tr",
319 #else
320 .dma_out_enabled = 0,
321 .dma_out_nbr = UINT_MAX,
322 .dma_out_irq_nbr = 0,
323 .dma_out_irq_flags = 0,
324 .dma_out_irq_description = NULL,
325 #endif
326 #ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
327 .dma_in_enabled = 1,
328 .dma_in_nbr = SER1_RX_DMA_NBR,
329 .dma_in_irq_nbr = SER1_DMA_RX_IRQ_NBR,
330 .dma_in_irq_flags = IRQF_DISABLED,
331 .dma_in_irq_description = "serial 1 dma rec",
332 #else
333 .dma_in_enabled = 0,
334 .dma_in_enabled = 0,
335 .dma_in_nbr = UINT_MAX,
336 .dma_in_irq_nbr = 0,
337 .dma_in_irq_flags = 0,
338 .dma_in_irq_description = NULL,
339 #endif
340 #else
341 .enabled = 0,
342 .io_if_description = NULL,
343 .dma_in_irq_nbr = 0,
344 .dma_out_enabled = 0,
345 .dma_in_enabled = 0
346 #endif
347 }, /* ttyS1 */
348
349 { .baud = DEF_BAUD,
350 .ioport = (unsigned char *)R_SERIAL2_CTRL,
351 .irq = 1U << 4, /* uses DMA 2 and 3 */
352 .oclrintradr = R_DMA_CH2_CLR_INTR,
353 .ofirstadr = R_DMA_CH2_FIRST,
354 .ocmdadr = R_DMA_CH2_CMD,
355 .ostatusadr = R_DMA_CH2_STATUS,
356 .iclrintradr = R_DMA_CH3_CLR_INTR,
357 .ifirstadr = R_DMA_CH3_FIRST,
358 .icmdadr = R_DMA_CH3_CMD,
359 .idescradr = R_DMA_CH3_DESCR,
360 .flags = STD_FLAGS,
361 .rx_ctrl = DEF_RX,
362 .tx_ctrl = DEF_TX,
363 .iseteop = 0,
364 .dma_owner = dma_ser2,
365 .io_if = if_serial_2,
366 #ifdef CONFIG_ETRAX_SERIAL_PORT2
367 .enabled = 1,
368 .io_if_description = "ser2",
369 #ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
370 .dma_out_enabled = 1,
371 .dma_out_nbr = SER2_TX_DMA_NBR,
372 .dma_out_irq_nbr = SER2_DMA_TX_IRQ_NBR,
373 .dma_out_irq_flags = IRQF_DISABLED,
374 .dma_out_irq_description = "serial 2 dma tr",
375 #else
376 .dma_out_enabled = 0,
377 .dma_out_nbr = UINT_MAX,
378 .dma_out_irq_nbr = 0,
379 .dma_out_irq_flags = 0,
380 .dma_out_irq_description = NULL,
381 #endif
382 #ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
383 .dma_in_enabled = 1,
384 .dma_in_nbr = SER2_RX_DMA_NBR,
385 .dma_in_irq_nbr = SER2_DMA_RX_IRQ_NBR,
386 .dma_in_irq_flags = IRQF_DISABLED,
387 .dma_in_irq_description = "serial 2 dma rec",
388 #else
389 .dma_in_enabled = 0,
390 .dma_in_nbr = UINT_MAX,
391 .dma_in_irq_nbr = 0,
392 .dma_in_irq_flags = 0,
393 .dma_in_irq_description = NULL,
394 #endif
395 #else
396 .enabled = 0,
397 .io_if_description = NULL,
398 .dma_out_enabled = 0,
399 .dma_in_enabled = 0
400 #endif
401 }, /* ttyS2 */
402
403 { .baud = DEF_BAUD,
404 .ioport = (unsigned char *)R_SERIAL3_CTRL,
405 .irq = 1U << 8, /* uses DMA 4 and 5 */
406 .oclrintradr = R_DMA_CH4_CLR_INTR,
407 .ofirstadr = R_DMA_CH4_FIRST,
408 .ocmdadr = R_DMA_CH4_CMD,
409 .ostatusadr = R_DMA_CH4_STATUS,
410 .iclrintradr = R_DMA_CH5_CLR_INTR,
411 .ifirstadr = R_DMA_CH5_FIRST,
412 .icmdadr = R_DMA_CH5_CMD,
413 .idescradr = R_DMA_CH5_DESCR,
414 .flags = STD_FLAGS,
415 .rx_ctrl = DEF_RX,
416 .tx_ctrl = DEF_TX,
417 .iseteop = 1,
418 .dma_owner = dma_ser3,
419 .io_if = if_serial_3,
420 #ifdef CONFIG_ETRAX_SERIAL_PORT3
421 .enabled = 1,
422 .io_if_description = "ser3",
423 #ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
424 .dma_out_enabled = 1,
425 .dma_out_nbr = SER3_TX_DMA_NBR,
426 .dma_out_irq_nbr = SER3_DMA_TX_IRQ_NBR,
427 .dma_out_irq_flags = IRQF_DISABLED,
428 .dma_out_irq_description = "serial 3 dma tr",
429 #else
430 .dma_out_enabled = 0,
431 .dma_out_nbr = UINT_MAX,
432 .dma_out_irq_nbr = 0,
433 .dma_out_irq_flags = 0,
434 .dma_out_irq_description = NULL,
435 #endif
436 #ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
437 .dma_in_enabled = 1,
438 .dma_in_nbr = SER3_RX_DMA_NBR,
439 .dma_in_irq_nbr = SER3_DMA_RX_IRQ_NBR,
440 .dma_in_irq_flags = IRQF_DISABLED,
441 .dma_in_irq_description = "serial 3 dma rec",
442 #else
443 .dma_in_enabled = 0,
444 .dma_in_nbr = UINT_MAX,
445 .dma_in_irq_nbr = 0,
446 .dma_in_irq_flags = 0,
447 .dma_in_irq_description = NULL
448 #endif
449 #else
450 .enabled = 0,
451 .io_if_description = NULL,
452 .dma_out_enabled = 0,
453 .dma_in_enabled = 0
454 #endif
455 } /* ttyS3 */
456 #endif
457 };
458
459
460 #define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial))
461
462 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
463 static struct fast_timer fast_timers[NR_PORTS];
464 #endif
465
466 #ifdef CONFIG_ETRAX_SERIAL_PROC_ENTRY
467 #define PROCSTAT(x) x
468 struct ser_statistics_type {
469 int overrun_cnt;
470 int early_errors_cnt;
471 int ser_ints_ok_cnt;
472 int errors_cnt;
473 unsigned long int processing_flip;
474 unsigned long processing_flip_still_room;
475 unsigned long int timeout_flush_cnt;
476 int rx_dma_ints;
477 int tx_dma_ints;
478 int rx_tot;
479 int tx_tot;
480 };
481
482 static struct ser_statistics_type ser_stat[NR_PORTS];
483
484 #else
485
486 #define PROCSTAT(x)
487
488 #endif /* CONFIG_ETRAX_SERIAL_PROC_ENTRY */
489
490 /* RS-485 */
491 #if defined(CONFIG_ETRAX_RS485)
492 #ifdef CONFIG_ETRAX_FAST_TIMER
493 static struct fast_timer fast_timers_rs485[NR_PORTS];
494 #endif
495 #if defined(CONFIG_ETRAX_RS485_ON_PA)
496 static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT;
497 #endif
498 #if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
499 static int rs485_port_g_bit = CONFIG_ETRAX_RS485_ON_PORT_G_BIT;
500 #endif
501 #endif
502
503 /* Info and macros needed for each ports extra control/status signals. */
504 #define E100_STRUCT_PORT(line, pinname) \
505 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
506 (R_PORT_PA_DATA): ( \
507 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
508 (R_PORT_PB_DATA):&dummy_ser[line]))
509
510 #define E100_STRUCT_SHADOW(line, pinname) \
511 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
512 (&port_pa_data_shadow): ( \
513 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
514 (&port_pb_data_shadow):&dummy_ser[line]))
515 #define E100_STRUCT_MASK(line, pinname) \
516 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
517 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT): ( \
518 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
519 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT):DUMMY_##pinname##_MASK))
520
521 #define DUMMY_DTR_MASK 1
522 #define DUMMY_RI_MASK 2
523 #define DUMMY_DSR_MASK 4
524 #define DUMMY_CD_MASK 8
525 static unsigned char dummy_ser[NR_PORTS] = {0xFF, 0xFF, 0xFF,0xFF};
526
527 /* If not all status pins are used or disabled, use mixed mode */
528 #ifdef CONFIG_ETRAX_SERIAL_PORT0
529
530 #define SER0_PA_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PA_BIT+CONFIG_ETRAX_SER0_RI_ON_PA_BIT+CONFIG_ETRAX_SER0_DSR_ON_PA_BIT+CONFIG_ETRAX_SER0_CD_ON_PA_BIT)
531
532 #if SER0_PA_BITSUM != -4
533 # if CONFIG_ETRAX_SER0_DTR_ON_PA_BIT == -1
534 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
535 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
536 # endif
537 # endif
538 # if CONFIG_ETRAX_SER0_RI_ON_PA_BIT == -1
539 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
540 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
541 # endif
542 # endif
543 # if CONFIG_ETRAX_SER0_DSR_ON_PA_BIT == -1
544 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
545 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
546 # endif
547 # endif
548 # if CONFIG_ETRAX_SER0_CD_ON_PA_BIT == -1
549 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
550 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
551 # endif
552 # endif
553 #endif
554
555 #define SER0_PB_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PB_BIT+CONFIG_ETRAX_SER0_RI_ON_PB_BIT+CONFIG_ETRAX_SER0_DSR_ON_PB_BIT+CONFIG_ETRAX_SER0_CD_ON_PB_BIT)
556
557 #if SER0_PB_BITSUM != -4
558 # if CONFIG_ETRAX_SER0_DTR_ON_PB_BIT == -1
559 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
560 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
561 # endif
562 # endif
563 # if CONFIG_ETRAX_SER0_RI_ON_PB_BIT == -1
564 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
565 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
566 # endif
567 # endif
568 # if CONFIG_ETRAX_SER0_DSR_ON_PB_BIT == -1
569 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
570 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
571 # endif
572 # endif
573 # if CONFIG_ETRAX_SER0_CD_ON_PB_BIT == -1
574 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
575 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
576 # endif
577 # endif
578 #endif
579
580 #endif /* PORT0 */
581
582
583 #ifdef CONFIG_ETRAX_SERIAL_PORT1
584
585 #define SER1_PA_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PA_BIT+CONFIG_ETRAX_SER1_RI_ON_PA_BIT+CONFIG_ETRAX_SER1_DSR_ON_PA_BIT+CONFIG_ETRAX_SER1_CD_ON_PA_BIT)
586
587 #if SER1_PA_BITSUM != -4
588 # if CONFIG_ETRAX_SER1_DTR_ON_PA_BIT == -1
589 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
590 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
591 # endif
592 # endif
593 # if CONFIG_ETRAX_SER1_RI_ON_PA_BIT == -1
594 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
595 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
596 # endif
597 # endif
598 # if CONFIG_ETRAX_SER1_DSR_ON_PA_BIT == -1
599 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
600 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
601 # endif
602 # endif
603 # if CONFIG_ETRAX_SER1_CD_ON_PA_BIT == -1
604 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
605 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
606 # endif
607 # endif
608 #endif
609
610 #define SER1_PB_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PB_BIT+CONFIG_ETRAX_SER1_RI_ON_PB_BIT+CONFIG_ETRAX_SER1_DSR_ON_PB_BIT+CONFIG_ETRAX_SER1_CD_ON_PB_BIT)
611
612 #if SER1_PB_BITSUM != -4
613 # if CONFIG_ETRAX_SER1_DTR_ON_PB_BIT == -1
614 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
615 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
616 # endif
617 # endif
618 # if CONFIG_ETRAX_SER1_RI_ON_PB_BIT == -1
619 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
620 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
621 # endif
622 # endif
623 # if CONFIG_ETRAX_SER1_DSR_ON_PB_BIT == -1
624 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
625 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
626 # endif
627 # endif
628 # if CONFIG_ETRAX_SER1_CD_ON_PB_BIT == -1
629 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
630 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
631 # endif
632 # endif
633 #endif
634
635 #endif /* PORT1 */
636
637 #ifdef CONFIG_ETRAX_SERIAL_PORT2
638
639 #define SER2_PA_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PA_BIT+CONFIG_ETRAX_SER2_RI_ON_PA_BIT+CONFIG_ETRAX_SER2_DSR_ON_PA_BIT+CONFIG_ETRAX_SER2_CD_ON_PA_BIT)
640
641 #if SER2_PA_BITSUM != -4
642 # if CONFIG_ETRAX_SER2_DTR_ON_PA_BIT == -1
643 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
644 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
645 # endif
646 # endif
647 # if CONFIG_ETRAX_SER2_RI_ON_PA_BIT == -1
648 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
649 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
650 # endif
651 # endif
652 # if CONFIG_ETRAX_SER2_DSR_ON_PA_BIT == -1
653 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
654 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
655 # endif
656 # endif
657 # if CONFIG_ETRAX_SER2_CD_ON_PA_BIT == -1
658 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
659 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
660 # endif
661 # endif
662 #endif
663
664 #define SER2_PB_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PB_BIT+CONFIG_ETRAX_SER2_RI_ON_PB_BIT+CONFIG_ETRAX_SER2_DSR_ON_PB_BIT+CONFIG_ETRAX_SER2_CD_ON_PB_BIT)
665
666 #if SER2_PB_BITSUM != -4
667 # if CONFIG_ETRAX_SER2_DTR_ON_PB_BIT == -1
668 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
669 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
670 # endif
671 # endif
672 # if CONFIG_ETRAX_SER2_RI_ON_PB_BIT == -1
673 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
674 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
675 # endif
676 # endif
677 # if CONFIG_ETRAX_SER2_DSR_ON_PB_BIT == -1
678 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
679 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
680 # endif
681 # endif
682 # if CONFIG_ETRAX_SER2_CD_ON_PB_BIT == -1
683 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
684 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
685 # endif
686 # endif
687 #endif
688
689 #endif /* PORT2 */
690
691 #ifdef CONFIG_ETRAX_SERIAL_PORT3
692
693 #define SER3_PA_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PA_BIT+CONFIG_ETRAX_SER3_RI_ON_PA_BIT+CONFIG_ETRAX_SER3_DSR_ON_PA_BIT+CONFIG_ETRAX_SER3_CD_ON_PA_BIT)
694
695 #if SER3_PA_BITSUM != -4
696 # if CONFIG_ETRAX_SER3_DTR_ON_PA_BIT == -1
697 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
698 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
699 # endif
700 # endif
701 # if CONFIG_ETRAX_SER3_RI_ON_PA_BIT == -1
702 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
703 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
704 # endif
705 # endif
706 # if CONFIG_ETRAX_SER3_DSR_ON_PA_BIT == -1
707 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
708 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
709 # endif
710 # endif
711 # if CONFIG_ETRAX_SER3_CD_ON_PA_BIT == -1
712 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
713 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
714 # endif
715 # endif
716 #endif
717
718 #define SER3_PB_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PB_BIT+CONFIG_ETRAX_SER3_RI_ON_PB_BIT+CONFIG_ETRAX_SER3_DSR_ON_PB_BIT+CONFIG_ETRAX_SER3_CD_ON_PB_BIT)
719
720 #if SER3_PB_BITSUM != -4
721 # if CONFIG_ETRAX_SER3_DTR_ON_PB_BIT == -1
722 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
723 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
724 # endif
725 # endif
726 # if CONFIG_ETRAX_SER3_RI_ON_PB_BIT == -1
727 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
728 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
729 # endif
730 # endif
731 # if CONFIG_ETRAX_SER3_DSR_ON_PB_BIT == -1
732 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
733 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
734 # endif
735 # endif
736 # if CONFIG_ETRAX_SER3_CD_ON_PB_BIT == -1
737 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
738 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
739 # endif
740 # endif
741 #endif
742
743 #endif /* PORT3 */
744
745
746 #if defined(CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED) || \
747 defined(CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED) || \
748 defined(CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED) || \
749 defined(CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED)
750 #define CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
751 #endif
752
753 #ifdef CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
754 /* The pins can be mixed on PA and PB */
755 #define CONTROL_PINS_PORT_NOT_USED(line) \
756 &dummy_ser[line], &dummy_ser[line], \
757 &dummy_ser[line], &dummy_ser[line], \
758 &dummy_ser[line], &dummy_ser[line], \
759 &dummy_ser[line], &dummy_ser[line], \
760 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
761
762
763 struct control_pins
764 {
765 volatile unsigned char *dtr_port;
766 unsigned char *dtr_shadow;
767 volatile unsigned char *ri_port;
768 unsigned char *ri_shadow;
769 volatile unsigned char *dsr_port;
770 unsigned char *dsr_shadow;
771 volatile unsigned char *cd_port;
772 unsigned char *cd_shadow;
773
774 unsigned char dtr_mask;
775 unsigned char ri_mask;
776 unsigned char dsr_mask;
777 unsigned char cd_mask;
778 };
779
780 static const struct control_pins e100_modem_pins[NR_PORTS] =
781 {
782 /* Ser 0 */
783 {
784 #ifdef CONFIG_ETRAX_SERIAL_PORT0
785 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
786 E100_STRUCT_PORT(0,RI), E100_STRUCT_SHADOW(0,RI),
787 E100_STRUCT_PORT(0,DSR), E100_STRUCT_SHADOW(0,DSR),
788 E100_STRUCT_PORT(0,CD), E100_STRUCT_SHADOW(0,CD),
789 E100_STRUCT_MASK(0,DTR),
790 E100_STRUCT_MASK(0,RI),
791 E100_STRUCT_MASK(0,DSR),
792 E100_STRUCT_MASK(0,CD)
793 #else
794 CONTROL_PINS_PORT_NOT_USED(0)
795 #endif
796 },
797
798 /* Ser 1 */
799 {
800 #ifdef CONFIG_ETRAX_SERIAL_PORT1
801 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
802 E100_STRUCT_PORT(1,RI), E100_STRUCT_SHADOW(1,RI),
803 E100_STRUCT_PORT(1,DSR), E100_STRUCT_SHADOW(1,DSR),
804 E100_STRUCT_PORT(1,CD), E100_STRUCT_SHADOW(1,CD),
805 E100_STRUCT_MASK(1,DTR),
806 E100_STRUCT_MASK(1,RI),
807 E100_STRUCT_MASK(1,DSR),
808 E100_STRUCT_MASK(1,CD)
809 #else
810 CONTROL_PINS_PORT_NOT_USED(1)
811 #endif
812 },
813
814 /* Ser 2 */
815 {
816 #ifdef CONFIG_ETRAX_SERIAL_PORT2
817 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
818 E100_STRUCT_PORT(2,RI), E100_STRUCT_SHADOW(2,RI),
819 E100_STRUCT_PORT(2,DSR), E100_STRUCT_SHADOW(2,DSR),
820 E100_STRUCT_PORT(2,CD), E100_STRUCT_SHADOW(2,CD),
821 E100_STRUCT_MASK(2,DTR),
822 E100_STRUCT_MASK(2,RI),
823 E100_STRUCT_MASK(2,DSR),
824 E100_STRUCT_MASK(2,CD)
825 #else
826 CONTROL_PINS_PORT_NOT_USED(2)
827 #endif
828 },
829
830 /* Ser 3 */
831 {
832 #ifdef CONFIG_ETRAX_SERIAL_PORT3
833 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
834 E100_STRUCT_PORT(3,RI), E100_STRUCT_SHADOW(3,RI),
835 E100_STRUCT_PORT(3,DSR), E100_STRUCT_SHADOW(3,DSR),
836 E100_STRUCT_PORT(3,CD), E100_STRUCT_SHADOW(3,CD),
837 E100_STRUCT_MASK(3,DTR),
838 E100_STRUCT_MASK(3,RI),
839 E100_STRUCT_MASK(3,DSR),
840 E100_STRUCT_MASK(3,CD)
841 #else
842 CONTROL_PINS_PORT_NOT_USED(3)
843 #endif
844 }
845 };
846 #else /* CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
847
848 /* All pins are on either PA or PB for each serial port */
849 #define CONTROL_PINS_PORT_NOT_USED(line) \
850 &dummy_ser[line], &dummy_ser[line], \
851 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
852
853
854 struct control_pins
855 {
856 volatile unsigned char *port;
857 unsigned char *shadow;
858
859 unsigned char dtr_mask;
860 unsigned char ri_mask;
861 unsigned char dsr_mask;
862 unsigned char cd_mask;
863 };
864
865 #define dtr_port port
866 #define dtr_shadow shadow
867 #define ri_port port
868 #define ri_shadow shadow
869 #define dsr_port port
870 #define dsr_shadow shadow
871 #define cd_port port
872 #define cd_shadow shadow
873
874 static const struct control_pins e100_modem_pins[NR_PORTS] =
875 {
876 /* Ser 0 */
877 {
878 #ifdef CONFIG_ETRAX_SERIAL_PORT0
879 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
880 E100_STRUCT_MASK(0,DTR),
881 E100_STRUCT_MASK(0,RI),
882 E100_STRUCT_MASK(0,DSR),
883 E100_STRUCT_MASK(0,CD)
884 #else
885 CONTROL_PINS_PORT_NOT_USED(0)
886 #endif
887 },
888
889 /* Ser 1 */
890 {
891 #ifdef CONFIG_ETRAX_SERIAL_PORT1
892 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
893 E100_STRUCT_MASK(1,DTR),
894 E100_STRUCT_MASK(1,RI),
895 E100_STRUCT_MASK(1,DSR),
896 E100_STRUCT_MASK(1,CD)
897 #else
898 CONTROL_PINS_PORT_NOT_USED(1)
899 #endif
900 },
901
902 /* Ser 2 */
903 {
904 #ifdef CONFIG_ETRAX_SERIAL_PORT2
905 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
906 E100_STRUCT_MASK(2,DTR),
907 E100_STRUCT_MASK(2,RI),
908 E100_STRUCT_MASK(2,DSR),
909 E100_STRUCT_MASK(2,CD)
910 #else
911 CONTROL_PINS_PORT_NOT_USED(2)
912 #endif
913 },
914
915 /* Ser 3 */
916 {
917 #ifdef CONFIG_ETRAX_SERIAL_PORT3
918 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
919 E100_STRUCT_MASK(3,DTR),
920 E100_STRUCT_MASK(3,RI),
921 E100_STRUCT_MASK(3,DSR),
922 E100_STRUCT_MASK(3,CD)
923 #else
924 CONTROL_PINS_PORT_NOT_USED(3)
925 #endif
926 }
927 };
928 #endif /* !CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
929
930 #define E100_RTS_MASK 0x20
931 #define E100_CTS_MASK 0x40
932
933 /* All serial port signals are active low:
934 * active = 0 -> 3.3V to RS-232 driver -> -12V on RS-232 level
935 * inactive = 1 -> 0V to RS-232 driver -> +12V on RS-232 level
936 *
937 * These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip
938 */
939
940 /* Output */
941 #define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK)
942 /* Input */
943 #define E100_CTS_GET(info) ((info)->ioport[REG_STATUS] & E100_CTS_MASK)
944
945 /* These are typically PA or PB and 0 means 0V, 1 means 3.3V */
946 /* Is an output */
947 #define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask)
948
949 /* Normally inputs */
950 #define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask)
951 #define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask)
952
953 /* Input */
954 #define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask)
955
956
957 /*
958 * tmp_buf is used as a temporary buffer by serial_write. We need to
959 * lock it in case the memcpy_fromfs blocks while swapping in a page,
960 * and some other program tries to do a serial write at the same time.
961 * Since the lock will only come under contention when the system is
962 * swapping and available memory is low, it makes sense to share one
963 * buffer across all the serial ports, since it significantly saves
964 * memory if large numbers of serial ports are open.
965 */
966 static unsigned char *tmp_buf;
967 static DEFINE_MUTEX(tmp_buf_mutex);
968
969 /* Calculate the chartime depending on baudrate, numbor of bits etc. */
970 static void update_char_time(struct e100_serial * info)
971 {
972 tcflag_t cflags = info->port.tty->termios->c_cflag;
973 int bits;
974
975 /* calc. number of bits / data byte */
976 /* databits + startbit and 1 stopbit */
977 if ((cflags & CSIZE) == CS7)
978 bits = 9;
979 else
980 bits = 10;
981
982 if (cflags & CSTOPB) /* 2 stopbits ? */
983 bits++;
984
985 if (cflags & PARENB) /* parity bit ? */
986 bits++;
987
988 /* calc timeout */
989 info->char_time_usec = ((bits * 1000000) / info->baud) + 1;
990 info->flush_time_usec = 4*info->char_time_usec;
991 if (info->flush_time_usec < MIN_FLUSH_TIME_USEC)
992 info->flush_time_usec = MIN_FLUSH_TIME_USEC;
993
994 }
995
996 /*
997 * This function maps from the Bxxxx defines in asm/termbits.h into real
998 * baud rates.
999 */
1000
1001 static int
1002 cflag_to_baud(unsigned int cflag)
1003 {
1004 static int baud_table[] = {
1005 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
1006 4800, 9600, 19200, 38400 };
1007
1008 static int ext_baud_table[] = {
1009 0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000,
1010 0, 0, 0, 0, 0, 0, 0, 0 };
1011
1012 if (cflag & CBAUDEX)
1013 return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1014 else
1015 return baud_table[cflag & CBAUD];
1016 }
1017
1018 /* and this maps to an etrax100 hardware baud constant */
1019
1020 static unsigned char
1021 cflag_to_etrax_baud(unsigned int cflag)
1022 {
1023 char retval;
1024
1025 static char baud_table[] = {
1026 -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 };
1027
1028 static char ext_baud_table[] = {
1029 -1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 };
1030
1031 if (cflag & CBAUDEX)
1032 retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1033 else
1034 retval = baud_table[cflag & CBAUD];
1035
1036 if (retval < 0) {
1037 printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag);
1038 retval = 5; /* choose default 9600 instead */
1039 }
1040
1041 return retval | (retval << 4); /* choose same for both TX and RX */
1042 }
1043
1044
1045 /* Various static support functions */
1046
1047 /* Functions to set or clear DTR/RTS on the requested line */
1048 /* It is complicated by the fact that RTS is a serial port register, while
1049 * DTR might not be implemented in the HW at all, and if it is, it can be on
1050 * any general port.
1051 */
1052
1053
1054 static inline void
1055 e100_dtr(struct e100_serial *info, int set)
1056 {
1057 #ifndef CONFIG_SVINTO_SIM
1058 unsigned char mask = e100_modem_pins[info->line].dtr_mask;
1059
1060 #ifdef SERIAL_DEBUG_IO
1061 printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask);
1062 printk("ser%i shadow before 0x%02X get: %i\n",
1063 info->line, *e100_modem_pins[info->line].dtr_shadow,
1064 E100_DTR_GET(info));
1065 #endif
1066 /* DTR is active low */
1067 {
1068 unsigned long flags;
1069
1070 local_irq_save(flags);
1071 *e100_modem_pins[info->line].dtr_shadow &= ~mask;
1072 *e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask);
1073 *e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow;
1074 local_irq_restore(flags);
1075 }
1076
1077 #ifdef SERIAL_DEBUG_IO
1078 printk("ser%i shadow after 0x%02X get: %i\n",
1079 info->line, *e100_modem_pins[info->line].dtr_shadow,
1080 E100_DTR_GET(info));
1081 #endif
1082 #endif
1083 }
1084
1085 /* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive
1086 * 0=0V , 1=3.3V
1087 */
1088 static inline void
1089 e100_rts(struct e100_serial *info, int set)
1090 {
1091 #ifndef CONFIG_SVINTO_SIM
1092 unsigned long flags;
1093 local_irq_save(flags);
1094 info->rx_ctrl &= ~E100_RTS_MASK;
1095 info->rx_ctrl |= (set ? 0 : E100_RTS_MASK); /* RTS is active low */
1096 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
1097 local_irq_restore(flags);
1098 #ifdef SERIAL_DEBUG_IO
1099 printk("ser%i rts %i\n", info->line, set);
1100 #endif
1101 #endif
1102 }
1103
1104
1105 /* If this behaves as a modem, RI and CD is an output */
1106 static inline void
1107 e100_ri_out(struct e100_serial *info, int set)
1108 {
1109 #ifndef CONFIG_SVINTO_SIM
1110 /* RI is active low */
1111 {
1112 unsigned char mask = e100_modem_pins[info->line].ri_mask;
1113 unsigned long flags;
1114
1115 local_irq_save(flags);
1116 *e100_modem_pins[info->line].ri_shadow &= ~mask;
1117 *e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask);
1118 *e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow;
1119 local_irq_restore(flags);
1120 }
1121 #endif
1122 }
1123 static inline void
1124 e100_cd_out(struct e100_serial *info, int set)
1125 {
1126 #ifndef CONFIG_SVINTO_SIM
1127 /* CD is active low */
1128 {
1129 unsigned char mask = e100_modem_pins[info->line].cd_mask;
1130 unsigned long flags;
1131
1132 local_irq_save(flags);
1133 *e100_modem_pins[info->line].cd_shadow &= ~mask;
1134 *e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask);
1135 *e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow;
1136 local_irq_restore(flags);
1137 }
1138 #endif
1139 }
1140
1141 static inline void
1142 e100_disable_rx(struct e100_serial *info)
1143 {
1144 #ifndef CONFIG_SVINTO_SIM
1145 /* disable the receiver */
1146 info->ioport[REG_REC_CTRL] =
1147 (info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1148 #endif
1149 }
1150
1151 static inline void
1152 e100_enable_rx(struct e100_serial *info)
1153 {
1154 #ifndef CONFIG_SVINTO_SIM
1155 /* enable the receiver */
1156 info->ioport[REG_REC_CTRL] =
1157 (info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1158 #endif
1159 }
1160
1161 /* the rx DMA uses both the dma_descr and the dma_eop interrupts */
1162
1163 static inline void
1164 e100_disable_rxdma_irq(struct e100_serial *info)
1165 {
1166 #ifdef SERIAL_DEBUG_INTR
1167 printk("rxdma_irq(%d): 0\n",info->line);
1168 #endif
1169 DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line));
1170 *R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3);
1171 }
1172
1173 static inline void
1174 e100_enable_rxdma_irq(struct e100_serial *info)
1175 {
1176 #ifdef SERIAL_DEBUG_INTR
1177 printk("rxdma_irq(%d): 1\n",info->line);
1178 #endif
1179 DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line));
1180 *R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3);
1181 }
1182
1183 /* the tx DMA uses only dma_descr interrupt */
1184
1185 static void e100_disable_txdma_irq(struct e100_serial *info)
1186 {
1187 #ifdef SERIAL_DEBUG_INTR
1188 printk("txdma_irq(%d): 0\n",info->line);
1189 #endif
1190 DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line));
1191 *R_IRQ_MASK2_CLR = info->irq;
1192 }
1193
1194 static void e100_enable_txdma_irq(struct e100_serial *info)
1195 {
1196 #ifdef SERIAL_DEBUG_INTR
1197 printk("txdma_irq(%d): 1\n",info->line);
1198 #endif
1199 DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line));
1200 *R_IRQ_MASK2_SET = info->irq;
1201 }
1202
1203 static void e100_disable_txdma_channel(struct e100_serial *info)
1204 {
1205 unsigned long flags;
1206
1207 /* Disable output DMA channel for the serial port in question
1208 * ( set to something other than serialX)
1209 */
1210 local_irq_save(flags);
1211 DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line));
1212 if (info->line == 0) {
1213 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==
1214 IO_STATE(R_GEN_CONFIG, dma6, serial0)) {
1215 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1216 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
1217 }
1218 } else if (info->line == 1) {
1219 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==
1220 IO_STATE(R_GEN_CONFIG, dma8, serial1)) {
1221 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1222 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
1223 }
1224 } else if (info->line == 2) {
1225 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==
1226 IO_STATE(R_GEN_CONFIG, dma2, serial2)) {
1227 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1228 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
1229 }
1230 } else if (info->line == 3) {
1231 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==
1232 IO_STATE(R_GEN_CONFIG, dma4, serial3)) {
1233 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1234 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
1235 }
1236 }
1237 *R_GEN_CONFIG = genconfig_shadow;
1238 local_irq_restore(flags);
1239 }
1240
1241
1242 static void e100_enable_txdma_channel(struct e100_serial *info)
1243 {
1244 unsigned long flags;
1245
1246 local_irq_save(flags);
1247 DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line));
1248 /* Enable output DMA channel for the serial port in question */
1249 if (info->line == 0) {
1250 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1251 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0);
1252 } else if (info->line == 1) {
1253 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1254 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1);
1255 } else if (info->line == 2) {
1256 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1257 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2);
1258 } else if (info->line == 3) {
1259 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1260 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3);
1261 }
1262 *R_GEN_CONFIG = genconfig_shadow;
1263 local_irq_restore(flags);
1264 }
1265
1266 static void e100_disable_rxdma_channel(struct e100_serial *info)
1267 {
1268 unsigned long flags;
1269
1270 /* Disable input DMA channel for the serial port in question
1271 * ( set to something other than serialX)
1272 */
1273 local_irq_save(flags);
1274 if (info->line == 0) {
1275 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==
1276 IO_STATE(R_GEN_CONFIG, dma7, serial0)) {
1277 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1278 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused);
1279 }
1280 } else if (info->line == 1) {
1281 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==
1282 IO_STATE(R_GEN_CONFIG, dma9, serial1)) {
1283 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1284 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb);
1285 }
1286 } else if (info->line == 2) {
1287 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==
1288 IO_STATE(R_GEN_CONFIG, dma3, serial2)) {
1289 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1290 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0);
1291 }
1292 } else if (info->line == 3) {
1293 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==
1294 IO_STATE(R_GEN_CONFIG, dma5, serial3)) {
1295 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1296 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1);
1297 }
1298 }
1299 *R_GEN_CONFIG = genconfig_shadow;
1300 local_irq_restore(flags);
1301 }
1302
1303
1304 static void e100_enable_rxdma_channel(struct e100_serial *info)
1305 {
1306 unsigned long flags;
1307
1308 local_irq_save(flags);
1309 /* Enable input DMA channel for the serial port in question */
1310 if (info->line == 0) {
1311 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1312 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0);
1313 } else if (info->line == 1) {
1314 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1315 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1);
1316 } else if (info->line == 2) {
1317 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1318 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2);
1319 } else if (info->line == 3) {
1320 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1321 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3);
1322 }
1323 *R_GEN_CONFIG = genconfig_shadow;
1324 local_irq_restore(flags);
1325 }
1326
1327 #ifdef SERIAL_HANDLE_EARLY_ERRORS
1328 /* in order to detect and fix errors on the first byte
1329 we have to use the serial interrupts as well. */
1330
1331 static inline void
1332 e100_disable_serial_data_irq(struct e100_serial *info)
1333 {
1334 #ifdef SERIAL_DEBUG_INTR
1335 printk("ser_irq(%d): 0\n",info->line);
1336 #endif
1337 DINTR1(DEBUG_LOG(info->line,"IRQ disable data_irq %i\n", info->line));
1338 *R_IRQ_MASK1_CLR = (1U << (8+2*info->line));
1339 }
1340
1341 static inline void
1342 e100_enable_serial_data_irq(struct e100_serial *info)
1343 {
1344 #ifdef SERIAL_DEBUG_INTR
1345 printk("ser_irq(%d): 1\n",info->line);
1346 printk("**** %d = %d\n",
1347 (8+2*info->line),
1348 (1U << (8+2*info->line)));
1349 #endif
1350 DINTR1(DEBUG_LOG(info->line,"IRQ enable data_irq %i\n", info->line));
1351 *R_IRQ_MASK1_SET = (1U << (8+2*info->line));
1352 }
1353 #endif
1354
1355 static inline void
1356 e100_disable_serial_tx_ready_irq(struct e100_serial *info)
1357 {
1358 #ifdef SERIAL_DEBUG_INTR
1359 printk("ser_tx_irq(%d): 0\n",info->line);
1360 #endif
1361 DINTR1(DEBUG_LOG(info->line,"IRQ disable ready_irq %i\n", info->line));
1362 *R_IRQ_MASK1_CLR = (1U << (8+1+2*info->line));
1363 }
1364
1365 static inline void
1366 e100_enable_serial_tx_ready_irq(struct e100_serial *info)
1367 {
1368 #ifdef SERIAL_DEBUG_INTR
1369 printk("ser_tx_irq(%d): 1\n",info->line);
1370 printk("**** %d = %d\n",
1371 (8+1+2*info->line),
1372 (1U << (8+1+2*info->line)));
1373 #endif
1374 DINTR2(DEBUG_LOG(info->line,"IRQ enable ready_irq %i\n", info->line));
1375 *R_IRQ_MASK1_SET = (1U << (8+1+2*info->line));
1376 }
1377
1378 static inline void e100_enable_rx_irq(struct e100_serial *info)
1379 {
1380 if (info->uses_dma_in)
1381 e100_enable_rxdma_irq(info);
1382 else
1383 e100_enable_serial_data_irq(info);
1384 }
1385 static inline void e100_disable_rx_irq(struct e100_serial *info)
1386 {
1387 if (info->uses_dma_in)
1388 e100_disable_rxdma_irq(info);
1389 else
1390 e100_disable_serial_data_irq(info);
1391 }
1392
1393 #if defined(CONFIG_ETRAX_RS485)
1394 /* Enable RS-485 mode on selected port. This is UGLY. */
1395 static int
1396 e100_enable_rs485(struct tty_struct *tty, struct serial_rs485 *r)
1397 {
1398 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1399
1400 #if defined(CONFIG_ETRAX_RS485_ON_PA)
1401 *R_PORT_PA_DATA = port_pa_data_shadow |= (1 << rs485_pa_bit);
1402 #endif
1403 #if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
1404 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1405 rs485_port_g_bit, 1);
1406 #endif
1407 #if defined(CONFIG_ETRAX_RS485_LTC1387)
1408 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1409 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 1);
1410 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1411 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 1);
1412 #endif
1413
1414 info->rs485.flags = r->flags;
1415 if (r->delay_rts_before_send >= 1000)
1416 info->rs485.delay_rts_before_send = 1000;
1417 else
1418 info->rs485.delay_rts_before_send = r->delay_rts_before_send;
1419 /* printk("rts: on send = %i, after = %i, enabled = %i",
1420 info->rs485.rts_on_send,
1421 info->rs485.rts_after_sent,
1422 info->rs485.enabled
1423 );
1424 */
1425 return 0;
1426 }
1427
1428 static int
1429 e100_write_rs485(struct tty_struct *tty,
1430 const unsigned char *buf, int count)
1431 {
1432 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1433 int old_value = (info->rs485.flags) & SER_RS485_ENABLED;
1434
1435 /* rs485 is always implicitly enabled if we're using the ioctl()
1436 * but it doesn't have to be set in the serial_rs485
1437 * (to be backward compatible with old apps)
1438 * So we store, set and restore it.
1439 */
1440 info->rs485.flags |= SER_RS485_ENABLED;
1441 /* rs_write now deals with RS485 if enabled */
1442 count = rs_write(tty, buf, count);
1443 if (!old_value)
1444 info->rs485.flags &= ~(SER_RS485_ENABLED);
1445 return count;
1446 }
1447
1448 #ifdef CONFIG_ETRAX_FAST_TIMER
1449 /* Timer function to toggle RTS when using FAST_TIMER */
1450 static void rs485_toggle_rts_timer_function(unsigned long data)
1451 {
1452 struct e100_serial *info = (struct e100_serial *)data;
1453
1454 fast_timers_rs485[info->line].function = NULL;
1455 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1456 #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
1457 e100_enable_rx(info);
1458 e100_enable_rx_irq(info);
1459 #endif
1460 }
1461 #endif
1462 #endif /* CONFIG_ETRAX_RS485 */
1463
1464 /*
1465 * ------------------------------------------------------------
1466 * rs_stop() and rs_start()
1467 *
1468 * This routines are called before setting or resetting tty->stopped.
1469 * They enable or disable transmitter using the XOFF registers, as necessary.
1470 * ------------------------------------------------------------
1471 */
1472
1473 static void
1474 rs_stop(struct tty_struct *tty)
1475 {
1476 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1477 if (info) {
1478 unsigned long flags;
1479 unsigned long xoff;
1480
1481 local_irq_save(flags);
1482 DFLOW(DEBUG_LOG(info->line, "XOFF rs_stop xmit %i\n",
1483 CIRC_CNT(info->xmit.head,
1484 info->xmit.tail,SERIAL_XMIT_SIZE)));
1485
1486 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char,
1487 STOP_CHAR(info->port.tty));
1488 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop);
1489 if (tty->termios->c_iflag & IXON ) {
1490 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1491 }
1492
1493 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1494 local_irq_restore(flags);
1495 }
1496 }
1497
1498 static void
1499 rs_start(struct tty_struct *tty)
1500 {
1501 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1502 if (info) {
1503 unsigned long flags;
1504 unsigned long xoff;
1505
1506 local_irq_save(flags);
1507 DFLOW(DEBUG_LOG(info->line, "XOFF rs_start xmit %i\n",
1508 CIRC_CNT(info->xmit.head,
1509 info->xmit.tail,SERIAL_XMIT_SIZE)));
1510 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty));
1511 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
1512 if (tty->termios->c_iflag & IXON ) {
1513 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1514 }
1515
1516 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1517 if (!info->uses_dma_out &&
1518 info->xmit.head != info->xmit.tail && info->xmit.buf)
1519 e100_enable_serial_tx_ready_irq(info);
1520
1521 local_irq_restore(flags);
1522 }
1523 }
1524
1525 /*
1526 * ----------------------------------------------------------------------
1527 *
1528 * Here starts the interrupt handling routines. All of the following
1529 * subroutines are declared as inline and are folded into
1530 * rs_interrupt(). They were separated out for readability's sake.
1531 *
1532 * Note: rs_interrupt() is a "fast" interrupt, which means that it
1533 * runs with interrupts turned off. People who may want to modify
1534 * rs_interrupt() should try to keep the interrupt handler as fast as
1535 * possible. After you are done making modifications, it is not a bad
1536 * idea to do:
1537 *
1538 * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
1539 *
1540 * and look at the resulting assemble code in serial.s.
1541 *
1542 * - Ted Ts'o (tytso@mit.edu), 7-Mar-93
1543 * -----------------------------------------------------------------------
1544 */
1545
1546 /*
1547 * This routine is used by the interrupt handler to schedule
1548 * processing in the software interrupt portion of the driver.
1549 */
1550 static void rs_sched_event(struct e100_serial *info, int event)
1551 {
1552 if (info->event & (1 << event))
1553 return;
1554 info->event |= 1 << event;
1555 schedule_work(&info->work);
1556 }
1557
1558 /* The output DMA channel is free - use it to send as many chars as possible
1559 * NOTES:
1560 * We don't pay attention to info->x_char, which means if the TTY wants to
1561 * use XON/XOFF it will set info->x_char but we won't send any X char!
1562 *
1563 * To implement this, we'd just start a DMA send of 1 byte pointing at a
1564 * buffer containing the X char, and skip updating xmit. We'd also have to
1565 * check if the last sent char was the X char when we enter this function
1566 * the next time, to avoid updating xmit with the sent X value.
1567 */
1568
1569 static void
1570 transmit_chars_dma(struct e100_serial *info)
1571 {
1572 unsigned int c, sentl;
1573 struct etrax_dma_descr *descr;
1574
1575 #ifdef CONFIG_SVINTO_SIM
1576 /* This will output too little if tail is not 0 always since
1577 * we don't reloop to send the other part. Anyway this SHOULD be a
1578 * no-op - transmit_chars_dma would never really be called during sim
1579 * since rs_write does not write into the xmit buffer then.
1580 */
1581 if (info->xmit.tail)
1582 printk("Error in serial.c:transmit_chars-dma(), tail!=0\n");
1583 if (info->xmit.head != info->xmit.tail) {
1584 SIMCOUT(info->xmit.buf + info->xmit.tail,
1585 CIRC_CNT(info->xmit.head,
1586 info->xmit.tail,
1587 SERIAL_XMIT_SIZE));
1588 info->xmit.head = info->xmit.tail; /* move back head */
1589 info->tr_running = 0;
1590 }
1591 return;
1592 #endif
1593 /* acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1594 *info->oclrintradr =
1595 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1596 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1597
1598 #ifdef SERIAL_DEBUG_INTR
1599 if (info->line == SERIAL_DEBUG_LINE)
1600 printk("tc\n");
1601 #endif
1602 if (!info->tr_running) {
1603 /* weirdo... we shouldn't get here! */
1604 printk(KERN_WARNING "Achtung: transmit_chars_dma with !tr_running\n");
1605 return;
1606 }
1607
1608 descr = &info->tr_descr;
1609
1610 /* first get the amount of bytes sent during the last DMA transfer,
1611 and update xmit accordingly */
1612
1613 /* if the stop bit was not set, all data has been sent */
1614 if (!(descr->status & d_stop)) {
1615 sentl = descr->sw_len;
1616 } else
1617 /* otherwise we find the amount of data sent here */
1618 sentl = descr->hw_len;
1619
1620 DFLOW(DEBUG_LOG(info->line, "TX %i done\n", sentl));
1621
1622 /* update stats */
1623 info->icount.tx += sentl;
1624
1625 /* update xmit buffer */
1626 info->xmit.tail = (info->xmit.tail + sentl) & (SERIAL_XMIT_SIZE - 1);
1627
1628 /* if there is only a few chars left in the buf, wake up the blocked
1629 write if any */
1630 if (CIRC_CNT(info->xmit.head,
1631 info->xmit.tail,
1632 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
1633 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
1634
1635 /* find out the largest amount of consecutive bytes we want to send now */
1636
1637 c = CIRC_CNT_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
1638
1639 /* Don't send all in one DMA transfer - divide it so we wake up
1640 * application before all is sent
1641 */
1642
1643 if (c >= 4*WAKEUP_CHARS)
1644 c = c/2;
1645
1646 if (c <= 0) {
1647 /* our job here is done, don't schedule any new DMA transfer */
1648 info->tr_running = 0;
1649
1650 #if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
1651 if (info->rs485.flags & SER_RS485_ENABLED) {
1652 /* Set a short timer to toggle RTS */
1653 start_one_shot_timer(&fast_timers_rs485[info->line],
1654 rs485_toggle_rts_timer_function,
1655 (unsigned long)info,
1656 info->char_time_usec*2,
1657 "RS-485");
1658 }
1659 #endif /* RS485 */
1660 return;
1661 }
1662
1663 /* ok we can schedule a dma send of c chars starting at info->xmit.tail */
1664 /* set up the descriptor correctly for output */
1665 DFLOW(DEBUG_LOG(info->line, "TX %i\n", c));
1666 descr->ctrl = d_int | d_eol | d_wait; /* Wait needed for tty_wait_until_sent() */
1667 descr->sw_len = c;
1668 descr->buf = virt_to_phys(info->xmit.buf + info->xmit.tail);
1669 descr->status = 0;
1670
1671 *info->ofirstadr = virt_to_phys(descr); /* write to R_DMAx_FIRST */
1672 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1673
1674 /* DMA is now running (hopefully) */
1675 } /* transmit_chars_dma */
1676
1677 static void
1678 start_transmit(struct e100_serial *info)
1679 {
1680 #if 0
1681 if (info->line == SERIAL_DEBUG_LINE)
1682 printk("x\n");
1683 #endif
1684
1685 info->tr_descr.sw_len = 0;
1686 info->tr_descr.hw_len = 0;
1687 info->tr_descr.status = 0;
1688 info->tr_running = 1;
1689 if (info->uses_dma_out)
1690 transmit_chars_dma(info);
1691 else
1692 e100_enable_serial_tx_ready_irq(info);
1693 } /* start_transmit */
1694
1695 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
1696 static int serial_fast_timer_started = 0;
1697 static int serial_fast_timer_expired = 0;
1698 static void flush_timeout_function(unsigned long data);
1699 #define START_FLUSH_FAST_TIMER_TIME(info, string, usec) {\
1700 unsigned long timer_flags; \
1701 local_irq_save(timer_flags); \
1702 if (fast_timers[info->line].function == NULL) { \
1703 serial_fast_timer_started++; \
1704 TIMERD(DEBUG_LOG(info->line, "start_timer %i ", info->line)); \
1705 TIMERD(DEBUG_LOG(info->line, "num started: %i\n", serial_fast_timer_started)); \
1706 start_one_shot_timer(&fast_timers[info->line], \
1707 flush_timeout_function, \
1708 (unsigned long)info, \
1709 (usec), \
1710 string); \
1711 } \
1712 else { \
1713 TIMERD(DEBUG_LOG(info->line, "timer %i already running\n", info->line)); \
1714 } \
1715 local_irq_restore(timer_flags); \
1716 }
1717 #define START_FLUSH_FAST_TIMER(info, string) START_FLUSH_FAST_TIMER_TIME(info, string, info->flush_time_usec)
1718
1719 #else
1720 #define START_FLUSH_FAST_TIMER_TIME(info, string, usec)
1721 #define START_FLUSH_FAST_TIMER(info, string)
1722 #endif
1723
1724 static struct etrax_recv_buffer *
1725 alloc_recv_buffer(unsigned int size)
1726 {
1727 struct etrax_recv_buffer *buffer;
1728
1729 if (!(buffer = kmalloc(sizeof *buffer + size, GFP_ATOMIC)))
1730 return NULL;
1731
1732 buffer->next = NULL;
1733 buffer->length = 0;
1734 buffer->error = TTY_NORMAL;
1735
1736 return buffer;
1737 }
1738
1739 static void
1740 append_recv_buffer(struct e100_serial *info, struct etrax_recv_buffer *buffer)
1741 {
1742 unsigned long flags;
1743
1744 local_irq_save(flags);
1745
1746 if (!info->first_recv_buffer)
1747 info->first_recv_buffer = buffer;
1748 else
1749 info->last_recv_buffer->next = buffer;
1750
1751 info->last_recv_buffer = buffer;
1752
1753 info->recv_cnt += buffer->length;
1754 if (info->recv_cnt > info->max_recv_cnt)
1755 info->max_recv_cnt = info->recv_cnt;
1756
1757 local_irq_restore(flags);
1758 }
1759
1760 static int
1761 add_char_and_flag(struct e100_serial *info, unsigned char data, unsigned char flag)
1762 {
1763 struct etrax_recv_buffer *buffer;
1764 if (info->uses_dma_in) {
1765 if (!(buffer = alloc_recv_buffer(4)))
1766 return 0;
1767
1768 buffer->length = 1;
1769 buffer->error = flag;
1770 buffer->buffer[0] = data;
1771
1772 append_recv_buffer(info, buffer);
1773
1774 info->icount.rx++;
1775 } else {
1776 struct tty_struct *tty = info->port.tty;
1777 tty_insert_flip_char(tty, data, flag);
1778 info->icount.rx++;
1779 }
1780
1781 return 1;
1782 }
1783
1784 static unsigned int handle_descr_data(struct e100_serial *info,
1785 struct etrax_dma_descr *descr,
1786 unsigned int recvl)
1787 {
1788 struct etrax_recv_buffer *buffer = phys_to_virt(descr->buf) - sizeof *buffer;
1789
1790 if (info->recv_cnt + recvl > 65536) {
1791 printk(KERN_CRIT
1792 "%s: Too much pending incoming serial data! Dropping %u bytes.\n", __func__, recvl);
1793 return 0;
1794 }
1795
1796 buffer->length = recvl;
1797
1798 if (info->errorcode == ERRCODE_SET_BREAK)
1799 buffer->error = TTY_BREAK;
1800 info->errorcode = 0;
1801
1802 append_recv_buffer(info, buffer);
1803
1804 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
1805 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1806
1807 descr->buf = virt_to_phys(buffer->buffer);
1808
1809 return recvl;
1810 }
1811
1812 static unsigned int handle_all_descr_data(struct e100_serial *info)
1813 {
1814 struct etrax_dma_descr *descr;
1815 unsigned int recvl;
1816 unsigned int ret = 0;
1817
1818 while (1)
1819 {
1820 descr = &info->rec_descr[info->cur_rec_descr];
1821
1822 if (descr == phys_to_virt(*info->idescradr))
1823 break;
1824
1825 if (++info->cur_rec_descr == SERIAL_RECV_DESCRIPTORS)
1826 info->cur_rec_descr = 0;
1827
1828 /* find out how many bytes were read */
1829
1830 /* if the eop bit was not set, all data has been received */
1831 if (!(descr->status & d_eop)) {
1832 recvl = descr->sw_len;
1833 } else {
1834 /* otherwise we find the amount of data received here */
1835 recvl = descr->hw_len;
1836 }
1837
1838 /* Reset the status information */
1839 descr->status = 0;
1840
1841 DFLOW( DEBUG_LOG(info->line, "RX %lu\n", recvl);
1842 if (info->port.tty->stopped) {
1843 unsigned char *buf = phys_to_virt(descr->buf);
1844 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[0]);
1845 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[1]);
1846 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[2]);
1847 }
1848 );
1849
1850 /* update stats */
1851 info->icount.rx += recvl;
1852
1853 ret += handle_descr_data(info, descr, recvl);
1854 }
1855
1856 return ret;
1857 }
1858
1859 static void receive_chars_dma(struct e100_serial *info)
1860 {
1861 struct tty_struct *tty;
1862 unsigned char rstat;
1863
1864 #ifdef CONFIG_SVINTO_SIM
1865 /* No receive in the simulator. Will probably be when the rest of
1866 * the serial interface works, and this piece will just be removed.
1867 */
1868 return;
1869 #endif
1870
1871 /* Acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1872 *info->iclrintradr =
1873 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1874 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1875
1876 tty = info->port.tty;
1877 if (!tty) /* Something wrong... */
1878 return;
1879
1880 #ifdef SERIAL_HANDLE_EARLY_ERRORS
1881 if (info->uses_dma_in)
1882 e100_enable_serial_data_irq(info);
1883 #endif
1884
1885 if (info->errorcode == ERRCODE_INSERT_BREAK)
1886 add_char_and_flag(info, '\0', TTY_BREAK);
1887
1888 handle_all_descr_data(info);
1889
1890 /* Read the status register to detect errors */
1891 rstat = info->ioport[REG_STATUS];
1892 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
1893 DFLOW(DEBUG_LOG(info->line, "XOFF detect stat %x\n", rstat));
1894 }
1895
1896 if (rstat & SER_ERROR_MASK) {
1897 /* If we got an error, we must reset it by reading the
1898 * data_in field
1899 */
1900 unsigned char data = info->ioport[REG_DATA];
1901
1902 PROCSTAT(ser_stat[info->line].errors_cnt++);
1903 DEBUG_LOG(info->line, "#dERR: s d 0x%04X\n",
1904 ((rstat & SER_ERROR_MASK) << 8) | data);
1905
1906 if (rstat & SER_PAR_ERR_MASK)
1907 add_char_and_flag(info, data, TTY_PARITY);
1908 else if (rstat & SER_OVERRUN_MASK)
1909 add_char_and_flag(info, data, TTY_OVERRUN);
1910 else if (rstat & SER_FRAMING_ERR_MASK)
1911 add_char_and_flag(info, data, TTY_FRAME);
1912 }
1913
1914 START_FLUSH_FAST_TIMER(info, "receive_chars");
1915
1916 /* Restart the receiving DMA */
1917 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
1918 }
1919
1920 static int start_recv_dma(struct e100_serial *info)
1921 {
1922 struct etrax_dma_descr *descr = info->rec_descr;
1923 struct etrax_recv_buffer *buffer;
1924 int i;
1925
1926 /* Set up the receiving descriptors */
1927 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) {
1928 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
1929 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1930
1931 descr[i].ctrl = d_int;
1932 descr[i].buf = virt_to_phys(buffer->buffer);
1933 descr[i].sw_len = SERIAL_DESCR_BUF_SIZE;
1934 descr[i].hw_len = 0;
1935 descr[i].status = 0;
1936 descr[i].next = virt_to_phys(&descr[i+1]);
1937 }
1938
1939 /* Link the last descriptor to the first */
1940 descr[i-1].next = virt_to_phys(&descr[0]);
1941
1942 /* Start with the first descriptor in the list */
1943 info->cur_rec_descr = 0;
1944
1945 /* Start the DMA */
1946 *info->ifirstadr = virt_to_phys(&descr[info->cur_rec_descr]);
1947 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1948
1949 /* Input DMA should be running now */
1950 return 1;
1951 }
1952
1953 static void
1954 start_receive(struct e100_serial *info)
1955 {
1956 #ifdef CONFIG_SVINTO_SIM
1957 /* No receive in the simulator. Will probably be when the rest of
1958 * the serial interface works, and this piece will just be removed.
1959 */
1960 return;
1961 #endif
1962 if (info->uses_dma_in) {
1963 /* reset the input dma channel to be sure it works */
1964
1965 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
1966 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
1967 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
1968
1969 start_recv_dma(info);
1970 }
1971 }
1972
1973
1974 /* the bits in the MASK2 register are laid out like this:
1975 DMAI_EOP DMAI_DESCR DMAO_EOP DMAO_DESCR
1976 where I is the input channel and O is the output channel for the port.
1977 info->irq is the bit number for the DMAO_DESCR so to check the others we
1978 shift info->irq to the left.
1979 */
1980
1981 /* dma output channel interrupt handler
1982 this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or
1983 DMA8(ser1) when they have finished a descriptor with the intr flag set.
1984 */
1985
1986 static irqreturn_t
1987 tr_interrupt(int irq, void *dev_id)
1988 {
1989 struct e100_serial *info;
1990 unsigned long ireg;
1991 int i;
1992 int handled = 0;
1993
1994 #ifdef CONFIG_SVINTO_SIM
1995 /* No receive in the simulator. Will probably be when the rest of
1996 * the serial interface works, and this piece will just be removed.
1997 */
1998 {
1999 const char *s = "What? tr_interrupt in simulator??\n";
2000 SIMCOUT(s,strlen(s));
2001 }
2002 return IRQ_HANDLED;
2003 #endif
2004
2005 /* find out the line that caused this irq and get it from rs_table */
2006
2007 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2008
2009 for (i = 0; i < NR_PORTS; i++) {
2010 info = rs_table + i;
2011 if (!info->enabled || !info->uses_dma_out)
2012 continue;
2013 /* check for dma_descr (don't need to check for dma_eop in output dma for serial */
2014 if (ireg & info->irq) {
2015 handled = 1;
2016 /* we can send a new dma bunch. make it so. */
2017 DINTR2(DEBUG_LOG(info->line, "tr_interrupt %i\n", i));
2018 /* Read jiffies_usec first,
2019 * we want this time to be as late as possible
2020 */
2021 PROCSTAT(ser_stat[info->line].tx_dma_ints++);
2022 info->last_tx_active_usec = GET_JIFFIES_USEC();
2023 info->last_tx_active = jiffies;
2024 transmit_chars_dma(info);
2025 }
2026
2027 /* FIXME: here we should really check for a change in the
2028 status lines and if so call status_handle(info) */
2029 }
2030 return IRQ_RETVAL(handled);
2031 } /* tr_interrupt */
2032
2033 /* dma input channel interrupt handler */
2034
2035 static irqreturn_t
2036 rec_interrupt(int irq, void *dev_id)
2037 {
2038 struct e100_serial *info;
2039 unsigned long ireg;
2040 int i;
2041 int handled = 0;
2042
2043 #ifdef CONFIG_SVINTO_SIM
2044 /* No receive in the simulator. Will probably be when the rest of
2045 * the serial interface works, and this piece will just be removed.
2046 */
2047 {
2048 const char *s = "What? rec_interrupt in simulator??\n";
2049 SIMCOUT(s,strlen(s));
2050 }
2051 return IRQ_HANDLED;
2052 #endif
2053
2054 /* find out the line that caused this irq and get it from rs_table */
2055
2056 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2057
2058 for (i = 0; i < NR_PORTS; i++) {
2059 info = rs_table + i;
2060 if (!info->enabled || !info->uses_dma_in)
2061 continue;
2062 /* check for both dma_eop and dma_descr for the input dma channel */
2063 if (ireg & ((info->irq << 2) | (info->irq << 3))) {
2064 handled = 1;
2065 /* we have received something */
2066 receive_chars_dma(info);
2067 }
2068
2069 /* FIXME: here we should really check for a change in the
2070 status lines and if so call status_handle(info) */
2071 }
2072 return IRQ_RETVAL(handled);
2073 } /* rec_interrupt */
2074
2075 static int force_eop_if_needed(struct e100_serial *info)
2076 {
2077 /* We check data_avail bit to determine if data has
2078 * arrived since last time
2079 */
2080 unsigned char rstat = info->ioport[REG_STATUS];
2081
2082 /* error or datavail? */
2083 if (rstat & SER_ERROR_MASK) {
2084 /* Some error has occurred. If there has been valid data, an
2085 * EOP interrupt will be made automatically. If no data, the
2086 * normal ser_interrupt should be enabled and handle it.
2087 * So do nothing!
2088 */
2089 DEBUG_LOG(info->line, "timeout err: rstat 0x%03X\n",
2090 rstat | (info->line << 8));
2091 return 0;
2092 }
2093
2094 if (rstat & SER_DATA_AVAIL_MASK) {
2095 /* Ok data, no error, count it */
2096 TIMERD(DEBUG_LOG(info->line, "timeout: rstat 0x%03X\n",
2097 rstat | (info->line << 8)));
2098 /* Read data to clear status flags */
2099 (void)info->ioport[REG_DATA];
2100
2101 info->forced_eop = 0;
2102 START_FLUSH_FAST_TIMER(info, "magic");
2103 return 0;
2104 }
2105
2106 /* hit the timeout, force an EOP for the input
2107 * dma channel if we haven't already
2108 */
2109 if (!info->forced_eop) {
2110 info->forced_eop = 1;
2111 PROCSTAT(ser_stat[info->line].timeout_flush_cnt++);
2112 TIMERD(DEBUG_LOG(info->line, "timeout EOP %i\n", info->line));
2113 FORCE_EOP(info);
2114 }
2115
2116 return 1;
2117 }
2118
2119 static void flush_to_flip_buffer(struct e100_serial *info)
2120 {
2121 struct tty_struct *tty;
2122 struct etrax_recv_buffer *buffer;
2123 unsigned long flags;
2124
2125 local_irq_save(flags);
2126 tty = info->port.tty;
2127
2128 if (!tty) {
2129 local_irq_restore(flags);
2130 return;
2131 }
2132
2133 while ((buffer = info->first_recv_buffer) != NULL) {
2134 unsigned int count = buffer->length;
2135
2136 tty_insert_flip_string(tty, buffer->buffer, count);
2137 info->recv_cnt -= count;
2138
2139 if (count == buffer->length) {
2140 info->first_recv_buffer = buffer->next;
2141 kfree(buffer);
2142 } else {
2143 buffer->length -= count;
2144 memmove(buffer->buffer, buffer->buffer + count, buffer->length);
2145 buffer->error = TTY_NORMAL;
2146 }
2147 }
2148
2149 if (!info->first_recv_buffer)
2150 info->last_recv_buffer = NULL;
2151
2152 local_irq_restore(flags);
2153
2154 /* This includes a check for low-latency */
2155 tty_flip_buffer_push(tty);
2156 }
2157
2158 static void check_flush_timeout(struct e100_serial *info)
2159 {
2160 /* Flip what we've got (if we can) */
2161 flush_to_flip_buffer(info);
2162
2163 /* We might need to flip later, but not to fast
2164 * since the system is busy processing input... */
2165 if (info->first_recv_buffer)
2166 START_FLUSH_FAST_TIMER_TIME(info, "flip", 2000);
2167
2168 /* Force eop last, since data might have come while we're processing
2169 * and if we started the slow timer above, we won't start a fast
2170 * below.
2171 */
2172 force_eop_if_needed(info);
2173 }
2174
2175 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
2176 static void flush_timeout_function(unsigned long data)
2177 {
2178 struct e100_serial *info = (struct e100_serial *)data;
2179
2180 fast_timers[info->line].function = NULL;
2181 serial_fast_timer_expired++;
2182 TIMERD(DEBUG_LOG(info->line, "flush_timout %i ", info->line));
2183 TIMERD(DEBUG_LOG(info->line, "num expired: %i\n", serial_fast_timer_expired));
2184 check_flush_timeout(info);
2185 }
2186
2187 #else
2188
2189 /* dma fifo/buffer timeout handler
2190 forces an end-of-packet for the dma input channel if no chars
2191 have been received for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS/100 s.
2192 */
2193
2194 static struct timer_list flush_timer;
2195
2196 static void
2197 timed_flush_handler(unsigned long ptr)
2198 {
2199 struct e100_serial *info;
2200 int i;
2201
2202 #ifdef CONFIG_SVINTO_SIM
2203 return;
2204 #endif
2205
2206 for (i = 0; i < NR_PORTS; i++) {
2207 info = rs_table + i;
2208 if (info->uses_dma_in)
2209 check_flush_timeout(info);
2210 }
2211
2212 /* restart flush timer */
2213 mod_timer(&flush_timer, jiffies + CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS);
2214 }
2215 #endif
2216
2217 #ifdef SERIAL_HANDLE_EARLY_ERRORS
2218
2219 /* If there is an error (ie break) when the DMA is running and
2220 * there are no bytes in the fifo the DMA is stopped and we get no
2221 * eop interrupt. Thus we have to monitor the first bytes on a DMA
2222 * transfer, and if it is without error we can turn the serial
2223 * interrupts off.
2224 */
2225
2226 /*
2227 BREAK handling on ETRAX 100:
2228 ETRAX will generate interrupt although there is no stop bit between the
2229 characters.
2230
2231 Depending on how long the break sequence is, the end of the breaksequence
2232 will look differently:
2233 | indicates start/end of a character.
2234
2235 B= Break character (0x00) with framing error.
2236 E= Error byte with parity error received after B characters.
2237 F= "Faked" valid byte received immediately after B characters.
2238 V= Valid byte
2239
2240 1.
2241 B BL ___________________________ V
2242 .._|__________|__________| |valid data |
2243
2244 Multiple frame errors with data == 0x00 (B),
2245 the timing matches up "perfectly" so no extra ending char is detected.
2246 The RXD pin is 1 in the last interrupt, in that case
2247 we set info->errorcode = ERRCODE_INSERT_BREAK, but we can't really
2248 know if another byte will come and this really is case 2. below
2249 (e.g F=0xFF or 0xFE)
2250 If RXD pin is 0 we can expect another character (see 2. below).
2251
2252
2253 2.
2254
2255 B B E or F__________________..__ V
2256 .._|__________|__________|______ | |valid data
2257 "valid" or
2258 parity error
2259
2260 Multiple frame errors with data == 0x00 (B),
2261 but the part of the break trigs is interpreted as a start bit (and possibly
2262 some 0 bits followed by a number of 1 bits and a stop bit).
2263 Depending on parity settings etc. this last character can be either
2264 a fake "valid" char (F) or have a parity error (E).
2265
2266 If the character is valid it will be put in the buffer,
2267 we set info->errorcode = ERRCODE_SET_BREAK so the receive interrupt
2268 will set the flags so the tty will handle it,
2269 if it's an error byte it will not be put in the buffer
2270 and we set info->errorcode = ERRCODE_INSERT_BREAK.
2271
2272 To distinguish a V byte in 1. from an F byte in 2. we keep a timestamp
2273 of the last faulty char (B) and compares it with the current time:
2274 If the time elapsed time is less then 2*char_time_usec we will assume
2275 it's a faked F char and not a Valid char and set
2276 info->errorcode = ERRCODE_SET_BREAK.
2277
2278 Flaws in the above solution:
2279 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2280 We use the timer to distinguish a F character from a V character,
2281 if a V character is to close after the break we might make the wrong decision.
2282
2283 TODO: The break will be delayed until an F or V character is received.
2284
2285 */
2286
2287 static
2288 struct e100_serial * handle_ser_rx_interrupt_no_dma(struct e100_serial *info)
2289 {
2290 unsigned long data_read;
2291 struct tty_struct *tty = info->port.tty;
2292
2293 if (!tty) {
2294 printk("!NO TTY!\n");
2295 return info;
2296 }
2297
2298 /* Read data and status at the same time */
2299 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
2300 more_data:
2301 if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {
2302 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2303 }
2304 DINTR2(DEBUG_LOG(info->line, "ser_rx %c\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read)));
2305
2306 if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |
2307 IO_MASK(R_SERIAL0_READ, par_err) |
2308 IO_MASK(R_SERIAL0_READ, overrun) )) {
2309 /* An error */
2310 info->last_rx_active_usec = GET_JIFFIES_USEC();
2311 info->last_rx_active = jiffies;
2312 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat_data %04X\n", data_read));
2313 DLOG_INT_TRIG(
2314 if (!log_int_trig1_pos) {
2315 log_int_trig1_pos = log_int_pos;
2316 log_int(rdpc(), 0, 0);
2317 }
2318 );
2319
2320
2321 if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&
2322 (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {
2323 /* Most likely a break, but we get interrupts over and
2324 * over again.
2325 */
2326
2327 if (!info->break_detected_cnt) {
2328 DEBUG_LOG(info->line, "#BRK start\n", 0);
2329 }
2330 if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {
2331 /* The RX pin is high now, so the break
2332 * must be over, but....
2333 * we can't really know if we will get another
2334 * last byte ending the break or not.
2335 * And we don't know if the byte (if any) will
2336 * have an error or look valid.
2337 */
2338 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2339 info->errorcode = ERRCODE_INSERT_BREAK;
2340 }
2341 info->break_detected_cnt++;
2342 } else {
2343 /* The error does not look like a break, but could be
2344 * the end of one
2345 */
2346 if (info->break_detected_cnt) {
2347 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2348 info->errorcode = ERRCODE_INSERT_BREAK;
2349 } else {
2350 unsigned char data = IO_EXTRACT(R_SERIAL0_READ,
2351 data_in, data_read);
2352 char flag = TTY_NORMAL;
2353 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2354 struct tty_struct *tty = info->port.tty;
2355 tty_insert_flip_char(tty, 0, flag);
2356 info->icount.rx++;
2357 }
2358
2359 if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {
2360 info->icount.parity++;
2361 flag = TTY_PARITY;
2362 } else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {
2363 info->icount.overrun++;
2364 flag = TTY_OVERRUN;
2365 } else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {
2366 info->icount.frame++;
2367 flag = TTY_FRAME;
2368 }
2369 tty_insert_flip_char(tty, data, flag);
2370 info->errorcode = 0;
2371 }
2372 info->break_detected_cnt = 0;
2373 }
2374 } else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2375 /* No error */
2376 DLOG_INT_TRIG(
2377 if (!log_int_trig1_pos) {
2378 if (log_int_pos >= log_int_size) {
2379 log_int_pos = 0;
2380 }
2381 log_int_trig0_pos = log_int_pos;
2382 log_int(rdpc(), 0, 0);
2383 }
2384 );
2385 tty_insert_flip_char(tty,
2386 IO_EXTRACT(R_SERIAL0_READ, data_in, data_read),
2387 TTY_NORMAL);
2388 } else {
2389 DEBUG_LOG(info->line, "ser_rx int but no data_avail %08lX\n", data_read);
2390 }
2391
2392
2393 info->icount.rx++;
2394 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
2395 if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2396 DEBUG_LOG(info->line, "ser_rx %c in loop\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read));
2397 goto more_data;
2398 }
2399
2400 tty_flip_buffer_push(info->port.tty);
2401 return info;
2402 }
2403
2404 static struct e100_serial* handle_ser_rx_interrupt(struct e100_serial *info)
2405 {
2406 unsigned char rstat;
2407
2408 #ifdef SERIAL_DEBUG_INTR
2409 printk("Interrupt from serport %d\n", i);
2410 #endif
2411 /* DEBUG_LOG(info->line, "ser_interrupt stat %03X\n", rstat | (i << 8)); */
2412 if (!info->uses_dma_in) {
2413 return handle_ser_rx_interrupt_no_dma(info);
2414 }
2415 /* DMA is used */
2416 rstat = info->ioport[REG_STATUS];
2417 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
2418 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2419 }
2420
2421 if (rstat & SER_ERROR_MASK) {
2422 unsigned char data;
2423
2424 info->last_rx_active_usec = GET_JIFFIES_USEC();
2425 info->last_rx_active = jiffies;
2426 /* If we got an error, we must reset it by reading the
2427 * data_in field
2428 */
2429 data = info->ioport[REG_DATA];
2430 DINTR1(DEBUG_LOG(info->line, "ser_rx! %c\n", data));
2431 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat %02X\n", rstat));
2432 if (!data && (rstat & SER_FRAMING_ERR_MASK)) {
2433 /* Most likely a break, but we get interrupts over and
2434 * over again.
2435 */
2436
2437 if (!info->break_detected_cnt) {
2438 DEBUG_LOG(info->line, "#BRK start\n", 0);
2439 }
2440 if (rstat & SER_RXD_MASK) {
2441 /* The RX pin is high now, so the break
2442 * must be over, but....
2443 * we can't really know if we will get another
2444 * last byte ending the break or not.
2445 * And we don't know if the byte (if any) will
2446 * have an error or look valid.
2447 */
2448 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2449 info->errorcode = ERRCODE_INSERT_BREAK;
2450 }
2451 info->break_detected_cnt++;
2452 } else {
2453 /* The error does not look like a break, but could be
2454 * the end of one
2455 */
2456 if (info->break_detected_cnt) {
2457 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2458 info->errorcode = ERRCODE_INSERT_BREAK;
2459 } else {
2460 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2461 info->icount.brk++;
2462 add_char_and_flag(info, '\0', TTY_BREAK);
2463 }
2464
2465 if (rstat & SER_PAR_ERR_MASK) {
2466 info->icount.parity++;
2467 add_char_and_flag(info, data, TTY_PARITY);
2468 } else if (rstat & SER_OVERRUN_MASK) {
2469 info->icount.overrun++;
2470 add_char_and_flag(info, data, TTY_OVERRUN);
2471 } else if (rstat & SER_FRAMING_ERR_MASK) {
2472 info->icount.frame++;
2473 add_char_and_flag(info, data, TTY_FRAME);
2474 }
2475
2476 info->errorcode = 0;
2477 }
2478 info->break_detected_cnt = 0;
2479 DEBUG_LOG(info->line, "#iERR s d %04X\n",
2480 ((rstat & SER_ERROR_MASK) << 8) | data);
2481 }
2482 PROCSTAT(ser_stat[info->line].early_errors_cnt++);
2483 } else { /* It was a valid byte, now let the DMA do the rest */
2484 unsigned long curr_time_u = GET_JIFFIES_USEC();
2485 unsigned long curr_time = jiffies;
2486
2487 if (info->break_detected_cnt) {
2488 /* Detect if this character is a new valid char or the
2489 * last char in a break sequence: If LSBits are 0 and
2490 * MSBits are high AND the time is close to the
2491 * previous interrupt we should discard it.
2492 */
2493 long elapsed_usec =
2494 (curr_time - info->last_rx_active) * (1000000/HZ) +
2495 curr_time_u - info->last_rx_active_usec;
2496 if (elapsed_usec < 2*info->char_time_usec) {
2497 DEBUG_LOG(info->line, "FBRK %i\n", info->line);
2498 /* Report as BREAK (error) and let
2499 * receive_chars_dma() handle it
2500 */
2501 info->errorcode = ERRCODE_SET_BREAK;
2502 } else {
2503 DEBUG_LOG(info->line, "Not end of BRK (V)%i\n", info->line);
2504 }
2505 DEBUG_LOG(info->line, "num brk %i\n", info->break_detected_cnt);
2506 }
2507
2508 #ifdef SERIAL_DEBUG_INTR
2509 printk("** OK, disabling ser_interrupts\n");
2510 #endif
2511 e100_disable_serial_data_irq(info);
2512 DINTR2(DEBUG_LOG(info->line, "ser_rx OK %d\n", info->line));
2513 info->break_detected_cnt = 0;
2514
2515 PROCSTAT(ser_stat[info->line].ser_ints_ok_cnt++);
2516 }
2517 /* Restarting the DMA never hurts */
2518 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
2519 START_FLUSH_FAST_TIMER(info, "ser_int");
2520 return info;
2521 } /* handle_ser_rx_interrupt */
2522
2523 static void handle_ser_tx_interrupt(struct e100_serial *info)
2524 {
2525 unsigned long flags;
2526
2527 if (info->x_char) {
2528 unsigned char rstat;
2529 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar 0x%02X\n", info->x_char));
2530 local_irq_save(flags);
2531 rstat = info->ioport[REG_STATUS];
2532 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2533
2534 info->ioport[REG_TR_DATA] = info->x_char;
2535 info->icount.tx++;
2536 info->x_char = 0;
2537 /* We must enable since it is disabled in ser_interrupt */
2538 e100_enable_serial_tx_ready_irq(info);
2539 local_irq_restore(flags);
2540 return;
2541 }
2542 if (info->uses_dma_out) {
2543 unsigned char rstat;
2544 int i;
2545 /* We only use normal tx interrupt when sending x_char */
2546 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar sent\n", 0));
2547 local_irq_save(flags);
2548 rstat = info->ioport[REG_STATUS];
2549 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2550 e100_disable_serial_tx_ready_irq(info);
2551 if (info->port.tty->stopped)
2552 rs_stop(info->port.tty);
2553 /* Enable the DMA channel and tell it to continue */
2554 e100_enable_txdma_channel(info);
2555 /* Wait 12 cycles before doing the DMA command */
2556 for(i = 6; i > 0; i--)
2557 nop();
2558
2559 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, continue);
2560 local_irq_restore(flags);
2561 return;
2562 }
2563 /* Normal char-by-char interrupt */
2564 if (info->xmit.head == info->xmit.tail
2565 || info->port.tty->stopped
2566 || info->port.tty->hw_stopped) {
2567 DFLOW(DEBUG_LOG(info->line, "tx_int: stopped %i\n",
2568 info->port.tty->stopped));
2569 e100_disable_serial_tx_ready_irq(info);
2570 info->tr_running = 0;
2571 return;
2572 }
2573 DINTR2(DEBUG_LOG(info->line, "tx_int %c\n", info->xmit.buf[info->xmit.tail]));
2574 /* Send a byte, rs485 timing is critical so turn of ints */
2575 local_irq_save(flags);
2576 info->ioport[REG_TR_DATA] = info->xmit.buf[info->xmit.tail];
2577 info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1);
2578 info->icount.tx++;
2579 if (info->xmit.head == info->xmit.tail) {
2580 #if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
2581 if (info->rs485.flags & SER_RS485_ENABLED) {
2582 /* Set a short timer to toggle RTS */
2583 start_one_shot_timer(&fast_timers_rs485[info->line],
2584 rs485_toggle_rts_timer_function,
2585 (unsigned long)info,
2586 info->char_time_usec*2,
2587 "RS-485");
2588 }
2589 #endif /* RS485 */
2590 info->last_tx_active_usec = GET_JIFFIES_USEC();
2591 info->last_tx_active = jiffies;
2592 e100_disable_serial_tx_ready_irq(info);
2593 info->tr_running = 0;
2594 DFLOW(DEBUG_LOG(info->line, "tx_int: stop2\n", 0));
2595 } else {
2596 /* We must enable since it is disabled in ser_interrupt */
2597 e100_enable_serial_tx_ready_irq(info);
2598 }
2599 local_irq_restore(flags);
2600
2601 if (CIRC_CNT(info->xmit.head,
2602 info->xmit.tail,
2603 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
2604 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
2605
2606 } /* handle_ser_tx_interrupt */
2607
2608 /* result of time measurements:
2609 * RX duration 54-60 us when doing something, otherwise 6-9 us
2610 * ser_int duration: just sending: 8-15 us normally, up to 73 us
2611 */
2612 static irqreturn_t
2613 ser_interrupt(int irq, void *dev_id)
2614 {
2615 static volatile int tx_started = 0;
2616 struct e100_serial *info;
2617 int i;
2618 unsigned long flags;
2619 unsigned long irq_mask1_rd;
2620 unsigned long data_mask = (1 << (8+2*0)); /* ser0 data_avail */
2621 int handled = 0;
2622 static volatile unsigned long reentered_ready_mask = 0;
2623
2624 local_irq_save(flags);
2625 irq_mask1_rd = *R_IRQ_MASK1_RD;
2626 /* First handle all rx interrupts with ints disabled */
2627 info = rs_table;
2628 irq_mask1_rd &= e100_ser_int_mask;
2629 for (i = 0; i < NR_PORTS; i++) {
2630 /* Which line caused the data irq? */
2631 if (irq_mask1_rd & data_mask) {
2632 handled = 1;
2633 handle_ser_rx_interrupt(info);
2634 }
2635 info += 1;
2636 data_mask <<= 2;
2637 }
2638 /* Handle tx interrupts with interrupts enabled so we
2639 * can take care of new data interrupts while transmitting
2640 * We protect the tx part with the tx_started flag.
2641 * We disable the tr_ready interrupts we are about to handle and
2642 * unblock the serial interrupt so new serial interrupts may come.
2643 *
2644 * If we get a new interrupt:
2645 * - it migth be due to synchronous serial ports.
2646 * - serial irq will be blocked by general irq handler.
2647 * - async data will be handled above (sync will be ignored).
2648 * - tx_started flag will prevent us from trying to send again and
2649 * we will exit fast - no need to unblock serial irq.
2650 * - Next (sync) serial interrupt handler will be runned with
2651 * disabled interrupt due to restore_flags() at end of function,
2652 * so sync handler will not be preempted or reentered.
2653 */
2654 if (!tx_started) {
2655 unsigned long ready_mask;
2656 unsigned long
2657 tx_started = 1;
2658 /* Only the tr_ready interrupts left */
2659 irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2660 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2661 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2662 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2663 while (irq_mask1_rd) {
2664 /* Disable those we are about to handle */
2665 *R_IRQ_MASK1_CLR = irq_mask1_rd;
2666 /* Unblock the serial interrupt */
2667 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
2668
2669 local_irq_enable();
2670 ready_mask = (1 << (8+1+2*0)); /* ser0 tr_ready */
2671 info = rs_table;
2672 for (i = 0; i < NR_PORTS; i++) {
2673 /* Which line caused the ready irq? */
2674 if (irq_mask1_rd & ready_mask) {
2675 handled = 1;
2676 handle_ser_tx_interrupt(info);
2677 }
2678 info += 1;
2679 ready_mask <<= 2;
2680 }
2681 /* handle_ser_tx_interrupt enables tr_ready interrupts */
2682 local_irq_disable();
2683 /* Handle reentered TX interrupt */
2684 irq_mask1_rd = reentered_ready_mask;
2685 }
2686 local_irq_disable();
2687 tx_started = 0;
2688 } else {
2689 unsigned long ready_mask;
2690 ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2691 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2692 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2693 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2694 if (ready_mask) {
2695 reentered_ready_mask |= ready_mask;
2696 /* Disable those we are about to handle */
2697 *R_IRQ_MASK1_CLR = ready_mask;
2698 DFLOW(DEBUG_LOG(SERIAL_DEBUG_LINE, "ser_int reentered with TX %X\n", ready_mask));
2699 }
2700 }
2701
2702 local_irq_restore(flags);
2703 return IRQ_RETVAL(handled);
2704 } /* ser_interrupt */
2705 #endif
2706
2707 /*
2708 * -------------------------------------------------------------------
2709 * Here ends the serial interrupt routines.
2710 * -------------------------------------------------------------------
2711 */
2712
2713 /*
2714 * This routine is used to handle the "bottom half" processing for the
2715 * serial driver, known also the "software interrupt" processing.
2716 * This processing is done at the kernel interrupt level, after the
2717 * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
2718 * is where time-consuming activities which can not be done in the
2719 * interrupt driver proper are done; the interrupt driver schedules
2720 * them using rs_sched_event(), and they get done here.
2721 */
2722 static void
2723 do_softint(struct work_struct *work)
2724 {
2725 struct e100_serial *info;
2726 struct tty_struct *tty;
2727
2728 info = container_of(work, struct e100_serial, work);
2729
2730 tty = info->port.tty;
2731 if (!tty)
2732 return;
2733
2734 if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event))
2735 tty_wakeup(tty);
2736 }
2737
2738 static int
2739 startup(struct e100_serial * info)
2740 {
2741 unsigned long flags;
2742 unsigned long xmit_page;
2743 int i;
2744
2745 xmit_page = get_zeroed_page(GFP_KERNEL);
2746 if (!xmit_page)
2747 return -ENOMEM;
2748
2749 local_irq_save(flags);
2750
2751 /* if it was already initialized, skip this */
2752
2753 if (info->flags & ASYNC_INITIALIZED) {
2754 local_irq_restore(flags);
2755 free_page(xmit_page);
2756 return 0;
2757 }
2758
2759 if (info->xmit.buf)
2760 free_page(xmit_page);
2761 else
2762 info->xmit.buf = (unsigned char *) xmit_page;
2763
2764 #ifdef SERIAL_DEBUG_OPEN
2765 printk("starting up ttyS%d (xmit_buf 0x%p)...\n", info->line, info->xmit.buf);
2766 #endif
2767
2768 #ifdef CONFIG_SVINTO_SIM
2769 /* Bits and pieces collected from below. Better to have them
2770 in one ifdef:ed clause than to mix in a lot of ifdefs,
2771 right? */
2772 if (info->port.tty)
2773 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2774
2775 info->xmit.head = info->xmit.tail = 0;
2776 info->first_recv_buffer = info->last_recv_buffer = NULL;
2777 info->recv_cnt = info->max_recv_cnt = 0;
2778
2779 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2780 info->rec_descr[i].buf = NULL;
2781
2782 /* No real action in the simulator, but may set info important
2783 to ioctl. */
2784 change_speed(info);
2785 #else
2786
2787 /*
2788 * Clear the FIFO buffers and disable them
2789 * (they will be reenabled in change_speed())
2790 */
2791
2792 /*
2793 * Reset the DMA channels and make sure their interrupts are cleared
2794 */
2795
2796 if (info->dma_in_enabled) {
2797 info->uses_dma_in = 1;
2798 e100_enable_rxdma_channel(info);
2799
2800 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2801
2802 /* Wait until reset cycle is complete */
2803 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
2804 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2805
2806 /* Make sure the irqs are cleared */
2807 *info->iclrintradr =
2808 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2809 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2810 } else {
2811 e100_disable_rxdma_channel(info);
2812 }
2813
2814 if (info->dma_out_enabled) {
2815 info->uses_dma_out = 1;
2816 e100_enable_txdma_channel(info);
2817 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2818
2819 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) ==
2820 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2821
2822 /* Make sure the irqs are cleared */
2823 *info->oclrintradr =
2824 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2825 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2826 } else {
2827 e100_disable_txdma_channel(info);
2828 }
2829
2830 if (info->port.tty)
2831 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2832
2833 info->xmit.head = info->xmit.tail = 0;
2834 info->first_recv_buffer = info->last_recv_buffer = NULL;
2835 info->recv_cnt = info->max_recv_cnt = 0;
2836
2837 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2838 info->rec_descr[i].buf = 0;
2839
2840 /*
2841 * and set the speed and other flags of the serial port
2842 * this will start the rx/tx as well
2843 */
2844 #ifdef SERIAL_HANDLE_EARLY_ERRORS
2845 e100_enable_serial_data_irq(info);
2846 #endif
2847 change_speed(info);
2848
2849 /* dummy read to reset any serial errors */
2850
2851 (void)info->ioport[REG_DATA];
2852
2853 /* enable the interrupts */
2854 if (info->uses_dma_out)
2855 e100_enable_txdma_irq(info);
2856
2857 e100_enable_rx_irq(info);
2858
2859 info->tr_running = 0; /* to be sure we don't lock up the transmitter */
2860
2861 /* setup the dma input descriptor and start dma */
2862
2863 start_receive(info);
2864
2865 /* for safety, make sure the descriptors last result is 0 bytes written */
2866
2867 info->tr_descr.sw_len = 0;
2868 info->tr_descr.hw_len = 0;
2869 info->tr_descr.status = 0;
2870
2871 /* enable RTS/DTR last */
2872
2873 e100_rts(info, 1);
2874 e100_dtr(info, 1);
2875
2876 #endif /* CONFIG_SVINTO_SIM */
2877
2878 info->flags |= ASYNC_INITIALIZED;
2879
2880 local_irq_restore(flags);
2881 return 0;
2882 }
2883
2884 /*
2885 * This routine will shutdown a serial port; interrupts are disabled, and
2886 * DTR is dropped if the hangup on close termio flag is on.
2887 */
2888 static void
2889 shutdown(struct e100_serial * info)
2890 {
2891 unsigned long flags;
2892 struct etrax_dma_descr *descr = info->rec_descr;
2893 struct etrax_recv_buffer *buffer;
2894 int i;
2895
2896 #ifndef CONFIG_SVINTO_SIM
2897 /* shut down the transmitter and receiver */
2898 DFLOW(DEBUG_LOG(info->line, "shutdown %i\n", info->line));
2899 e100_disable_rx(info);
2900 info->ioport[REG_TR_CTRL] = (info->tx_ctrl &= ~0x40);
2901
2902 /* disable interrupts, reset dma channels */
2903 if (info->uses_dma_in) {
2904 e100_disable_rxdma_irq(info);
2905 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2906 info->uses_dma_in = 0;
2907 } else {
2908 e100_disable_serial_data_irq(info);
2909 }
2910
2911 if (info->uses_dma_out) {
2912 e100_disable_txdma_irq(info);
2913 info->tr_running = 0;
2914 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2915 info->uses_dma_out = 0;
2916 } else {
2917 e100_disable_serial_tx_ready_irq(info);
2918 info->tr_running = 0;
2919 }
2920
2921 #endif /* CONFIG_SVINTO_SIM */
2922
2923 if (!(info->flags & ASYNC_INITIALIZED))
2924 return;
2925
2926 #ifdef SERIAL_DEBUG_OPEN
2927 printk("Shutting down serial port %d (irq %d)....\n", info->line,
2928 info->irq);
2929 #endif
2930
2931 local_irq_save(flags);
2932
2933 if (info->xmit.buf) {
2934 free_page((unsigned long)info->xmit.buf);
2935 info->xmit.buf = NULL;
2936 }
2937
2938 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2939 if (descr[i].buf) {
2940 buffer = phys_to_virt(descr[i].buf) - sizeof *buffer;
2941 kfree(buffer);
2942 descr[i].buf = 0;
2943 }
2944
2945 if (!info->port.tty || (info->port.tty->termios->c_cflag & HUPCL)) {
2946 /* hang up DTR and RTS if HUPCL is enabled */
2947 e100_dtr(info, 0);
2948 e100_rts(info, 0); /* could check CRTSCTS before doing this */
2949 }
2950
2951 if (info->port.tty)
2952 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2953
2954 info->flags &= ~ASYNC_INITIALIZED;
2955 local_irq_restore(flags);
2956 }
2957
2958
2959 /* change baud rate and other assorted parameters */
2960
2961 static void
2962 change_speed(struct e100_serial *info)
2963 {
2964 unsigned int cflag;
2965 unsigned long xoff;
2966 unsigned long flags;
2967 /* first some safety checks */
2968
2969 if (!info->port.tty || !info->port.tty->termios)
2970 return;
2971 if (!info->ioport)
2972 return;
2973
2974 cflag = info->port.tty->termios->c_cflag;
2975
2976 /* possibly, the tx/rx should be disabled first to do this safely */
2977
2978 /* change baud-rate and write it to the hardware */
2979 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST) {
2980 /* Special baudrate */
2981 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2982 unsigned long alt_source =
2983 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2984 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2985 /* R_ALT_SER_BAUDRATE selects the source */
2986 DBAUD(printk("Custom baudrate: baud_base/divisor %lu/%i\n",
2987 (unsigned long)info->baud_base, info->custom_divisor));
2988 if (info->baud_base == SERIAL_PRESCALE_BASE) {
2989 /* 0, 2-65535 (0=65536) */
2990 u16 divisor = info->custom_divisor;
2991 /* R_SERIAL_PRESCALE (upper 16 bits of R_CLOCK_PRESCALE) */
2992 /* baudrate is 3.125MHz/custom_divisor */
2993 alt_source =
2994 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, prescale) |
2995 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, prescale);
2996 alt_source = 0x11;
2997 DBAUD(printk("Writing SERIAL_PRESCALE: divisor %i\n", divisor));
2998 *R_SERIAL_PRESCALE = divisor;
2999 info->baud = SERIAL_PRESCALE_BASE/divisor;
3000 }
3001 #ifdef CONFIG_ETRAX_EXTERN_PB6CLK_ENABLED
3002 else if ((info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8 &&
3003 info->custom_divisor == 1) ||
3004 (info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ &&
3005 info->custom_divisor == 8)) {
3006 /* ext_clk selected */
3007 alt_source =
3008 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, extern) |
3009 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, extern);
3010 DBAUD(printk("using external baudrate: %lu\n", CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8));
3011 info->baud = CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8;
3012 }
3013 #endif
3014 else
3015 {
3016 /* Bad baudbase, we don't support using timer0
3017 * for baudrate.
3018 */
3019 printk(KERN_WARNING "Bad baud_base/custom_divisor: %lu/%i\n",
3020 (unsigned long)info->baud_base, info->custom_divisor);
3021 }
3022 r_alt_ser_baudrate_shadow &= ~mask;
3023 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3024 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3025 } else {
3026 /* Normal baudrate */
3027 /* Make sure we use normal baudrate */
3028 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
3029 unsigned long alt_source =
3030 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
3031 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
3032 r_alt_ser_baudrate_shadow &= ~mask;
3033 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3034 #ifndef CONFIG_SVINTO_SIM
3035 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3036 #endif /* CONFIG_SVINTO_SIM */
3037
3038 info->baud = cflag_to_baud(cflag);
3039 #ifndef CONFIG_SVINTO_SIM
3040 info->ioport[REG_BAUD] = cflag_to_etrax_baud(cflag);
3041 #endif /* CONFIG_SVINTO_SIM */
3042 }
3043
3044 #ifndef CONFIG_SVINTO_SIM
3045 /* start with default settings and then fill in changes */
3046 local_irq_save(flags);
3047 /* 8 bit, no/even parity */
3048 info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |
3049 IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |
3050 IO_MASK(R_SERIAL0_REC_CTRL, rec_par));
3051
3052 /* 8 bit, no/even parity, 1 stop bit, no cts */
3053 info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |
3054 IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |
3055 IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |
3056 IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |
3057 IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));
3058
3059 if ((cflag & CSIZE) == CS7) {
3060 /* set 7 bit mode */
3061 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit);
3062 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit);
3063 }
3064
3065 if (cflag & CSTOPB) {
3066 /* set 2 stop bit mode */
3067 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits);
3068 }
3069
3070 if (cflag & PARENB) {
3071 /* enable parity */
3072 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
3073 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
3074 }
3075
3076 if (cflag & CMSPAR) {
3077 /* enable stick parity, PARODD mean Mark which matches ETRAX */
3078 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick);
3079 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, stick);
3080 }
3081 if (cflag & PARODD) {
3082 /* set odd parity (or Mark if CMSPAR) */
3083 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd);
3084 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd);
3085 }
3086
3087 if (cflag & CRTSCTS) {
3088 /* enable automatic CTS handling */
3089 DFLOW(DEBUG_LOG(info->line, "FLOW auto_cts enabled\n", 0));
3090 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, active);
3091 }
3092
3093 /* make sure the tx and rx are enabled */
3094
3095 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable);
3096 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
3097
3098 /* actually write the control regs to the hardware */
3099
3100 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
3101 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
3102 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->port.tty));
3103 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
3104 if (info->port.tty->termios->c_iflag & IXON ) {
3105 DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n",
3106 STOP_CHAR(info->port.tty)));
3107 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
3108 }
3109
3110 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
3111 local_irq_restore(flags);
3112 #endif /* !CONFIG_SVINTO_SIM */
3113
3114 update_char_time(info);
3115
3116 } /* change_speed */
3117
3118 /* start transmitting chars NOW */
3119
3120 static void
3121 rs_flush_chars(struct tty_struct *tty)
3122 {
3123 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3124 unsigned long flags;
3125
3126 if (info->tr_running ||
3127 info->xmit.head == info->xmit.tail ||
3128 tty->stopped ||
3129 tty->hw_stopped ||
3130 !info->xmit.buf)
3131 return;
3132
3133 #ifdef SERIAL_DEBUG_FLOW
3134 printk("rs_flush_chars\n");
3135 #endif
3136
3137 /* this protection might not exactly be necessary here */
3138
3139 local_irq_save(flags);
3140 start_transmit(info);
3141 local_irq_restore(flags);
3142 }
3143
3144 static int rs_raw_write(struct tty_struct *tty,
3145 const unsigned char *buf, int count)
3146 {
3147 int c, ret = 0;
3148 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3149 unsigned long flags;
3150
3151 /* first some sanity checks */
3152
3153 if (!tty || !info->xmit.buf || !tmp_buf)
3154 return 0;
3155
3156 #ifdef SERIAL_DEBUG_DATA
3157 if (info->line == SERIAL_DEBUG_LINE)
3158 printk("rs_raw_write (%d), status %d\n",
3159 count, info->ioport[REG_STATUS]);
3160 #endif
3161
3162 #ifdef CONFIG_SVINTO_SIM
3163 /* Really simple. The output is here and now. */
3164 SIMCOUT(buf, count);
3165 return count;
3166 #endif
3167 local_save_flags(flags);
3168 DFLOW(DEBUG_LOG(info->line, "write count %i ", count));
3169 DFLOW(DEBUG_LOG(info->line, "ldisc %i\n", tty->ldisc.chars_in_buffer(tty)));
3170
3171
3172 /* The local_irq_disable/restore_flags pairs below are needed
3173 * because the DMA interrupt handler moves the info->xmit values.
3174 * the memcpy needs to be in the critical region unfortunately,
3175 * because we need to read xmit values, memcpy, write xmit values
3176 * in one atomic operation... this could perhaps be avoided by
3177 * more clever design.
3178 */
3179 local_irq_disable();
3180 while (count) {
3181 c = CIRC_SPACE_TO_END(info->xmit.head,
3182 info->xmit.tail,
3183 SERIAL_XMIT_SIZE);
3184
3185 if (count < c)
3186 c = count;
3187 if (c <= 0)
3188 break;
3189
3190 memcpy(info->xmit.buf + info->xmit.head, buf, c);
3191 info->xmit.head = (info->xmit.head + c) &
3192 (SERIAL_XMIT_SIZE-1);
3193 buf += c;
3194 count -= c;
3195 ret += c;
3196 }
3197 local_irq_restore(flags);
3198
3199 /* enable transmitter if not running, unless the tty is stopped
3200 * this does not need IRQ protection since if tr_running == 0
3201 * the IRQ's are not running anyway for this port.
3202 */
3203 DFLOW(DEBUG_LOG(info->line, "write ret %i\n", ret));
3204
3205 if (info->xmit.head != info->xmit.tail &&
3206 !tty->stopped &&
3207 !tty->hw_stopped &&
3208 !info->tr_running) {
3209 start_transmit(info);
3210 }
3211
3212 return ret;
3213 } /* raw_raw_write() */
3214
3215 static int
3216 rs_write(struct tty_struct *tty,
3217 const unsigned char *buf, int count)
3218 {
3219 #if defined(CONFIG_ETRAX_RS485)
3220 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3221
3222 if (info->rs485.flags & SER_RS485_ENABLED)
3223 {
3224 /* If we are in RS-485 mode, we need to toggle RTS and disable
3225 * the receiver before initiating a DMA transfer
3226 */
3227 #ifdef CONFIG_ETRAX_FAST_TIMER
3228 /* Abort any started timer */
3229 fast_timers_rs485[info->line].function = NULL;
3230 del_fast_timer(&fast_timers_rs485[info->line]);
3231 #endif
3232 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_ON_SEND));
3233 #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3234 e100_disable_rx(info);
3235 e100_enable_rx_irq(info);
3236 #endif
3237
3238 if (info->rs485.delay_rts_before_send > 0)
3239 msleep(info->rs485.delay_rts_before_send);
3240 }
3241 #endif /* CONFIG_ETRAX_RS485 */
3242
3243 count = rs_raw_write(tty, buf, count);
3244
3245 #if defined(CONFIG_ETRAX_RS485)
3246 if (info->rs485.flags & SER_RS485_ENABLED)
3247 {
3248 unsigned int val;
3249 /* If we are in RS-485 mode the following has to be done:
3250 * wait until DMA is ready
3251 * wait on transmit shift register
3252 * toggle RTS
3253 * enable the receiver
3254 */
3255
3256 /* Sleep until all sent */
3257 tty_wait_until_sent(tty, 0);
3258 #ifdef CONFIG_ETRAX_FAST_TIMER
3259 /* Now sleep a little more so that shift register is empty */
3260 schedule_usleep(info->char_time_usec * 2);
3261 #endif
3262 /* wait on transmit shift register */
3263 do{
3264 get_lsr_info(info, &val);
3265 }while (!(val & TIOCSER_TEMT));
3266
3267 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
3268
3269 #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3270 e100_enable_rx(info);
3271 e100_enable_rxdma_irq(info);
3272 #endif
3273 }
3274 #endif /* CONFIG_ETRAX_RS485 */
3275
3276 return count;
3277 } /* rs_write */
3278
3279
3280 /* how much space is available in the xmit buffer? */
3281
3282 static int
3283 rs_write_room(struct tty_struct *tty)
3284 {
3285 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3286
3287 return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3288 }
3289
3290 /* How many chars are in the xmit buffer?
3291 * This does not include any chars in the transmitter FIFO.
3292 * Use wait_until_sent for waiting for FIFO drain.
3293 */
3294
3295 static int
3296 rs_chars_in_buffer(struct tty_struct *tty)
3297 {
3298 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3299
3300 return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3301 }
3302
3303 /* discard everything in the xmit buffer */
3304
3305 static void
3306 rs_flush_buffer(struct tty_struct *tty)
3307 {
3308 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3309 unsigned long flags;
3310
3311 local_irq_save(flags);
3312 info->xmit.head = info->xmit.tail = 0;
3313 local_irq_restore(flags);
3314
3315 tty_wakeup(tty);
3316 }
3317
3318 /*
3319 * This function is used to send a high-priority XON/XOFF character to
3320 * the device
3321 *
3322 * Since we use DMA we don't check for info->x_char in transmit_chars_dma(),
3323 * but we do it in handle_ser_tx_interrupt().
3324 * We disable DMA channel and enable tx ready interrupt and write the
3325 * character when possible.
3326 */
3327 static void rs_send_xchar(struct tty_struct *tty, char ch)
3328 {
3329 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3330 unsigned long flags;
3331 local_irq_save(flags);
3332 if (info->uses_dma_out) {
3333 /* Put the DMA on hold and disable the channel */
3334 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, hold);
3335 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) !=
3336 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, hold));
3337 e100_disable_txdma_channel(info);
3338 }
3339
3340 /* Must make sure transmitter is not stopped before we can transmit */
3341 if (tty->stopped)
3342 rs_start(tty);
3343
3344 /* Enable manual transmit interrupt and send from there */
3345 DFLOW(DEBUG_LOG(info->line, "rs_send_xchar 0x%02X\n", ch));
3346 info->x_char = ch;
3347 e100_enable_serial_tx_ready_irq(info);
3348 local_irq_restore(flags);
3349 }
3350
3351 /*
3352 * ------------------------------------------------------------
3353 * rs_throttle()
3354 *
3355 * This routine is called by the upper-layer tty layer to signal that
3356 * incoming characters should be throttled.
3357 * ------------------------------------------------------------
3358 */
3359 static void
3360 rs_throttle(struct tty_struct * tty)
3361 {
3362 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3363 #ifdef SERIAL_DEBUG_THROTTLE
3364 char buf[64];
3365
3366 printk("throttle %s: %lu....\n", tty_name(tty, buf),
3367 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3368 #endif
3369 DFLOW(DEBUG_LOG(info->line,"rs_throttle %lu\n", tty->ldisc.chars_in_buffer(tty)));
3370
3371 /* Do RTS before XOFF since XOFF might take some time */
3372 if (tty->termios->c_cflag & CRTSCTS) {
3373 /* Turn off RTS line */
3374 e100_rts(info, 0);
3375 }
3376 if (I_IXOFF(tty))
3377 rs_send_xchar(tty, STOP_CHAR(tty));
3378
3379 }
3380
3381 static void
3382 rs_unthrottle(struct tty_struct * tty)
3383 {
3384 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3385 #ifdef SERIAL_DEBUG_THROTTLE
3386 char buf[64];
3387
3388 printk("unthrottle %s: %lu....\n", tty_name(tty, buf),
3389 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3390 #endif
3391 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc %d\n", tty->ldisc.chars_in_buffer(tty)));
3392 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count));
3393 /* Do RTS before XOFF since XOFF might take some time */
3394 if (tty->termios->c_cflag & CRTSCTS) {
3395 /* Assert RTS line */
3396 e100_rts(info, 1);
3397 }
3398
3399 if (I_IXOFF(tty)) {
3400 if (info->x_char)
3401 info->x_char = 0;
3402 else
3403 rs_send_xchar(tty, START_CHAR(tty));
3404 }
3405
3406 }
3407
3408 /*
3409 * ------------------------------------------------------------
3410 * rs_ioctl() and friends
3411 * ------------------------------------------------------------
3412 */
3413
3414 static int
3415 get_serial_info(struct e100_serial * info,
3416 struct serial_struct * retinfo)
3417 {
3418 struct serial_struct tmp;
3419
3420 /* this is all probably wrong, there are a lot of fields
3421 * here that we don't have in e100_serial and maybe we
3422 * should set them to something else than 0.
3423 */
3424
3425 if (!retinfo)
3426 return -EFAULT;
3427 memset(&tmp, 0, sizeof(tmp));
3428 tmp.type = info->type;
3429 tmp.line = info->line;
3430 tmp.port = (int)info->ioport;
3431 tmp.irq = info->irq;
3432 tmp.flags = info->flags;
3433 tmp.baud_base = info->baud_base;
3434 tmp.close_delay = info->close_delay;
3435 tmp.closing_wait = info->closing_wait;
3436 tmp.custom_divisor = info->custom_divisor;
3437 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
3438 return -EFAULT;
3439 return 0;
3440 }
3441
3442 static int
3443 set_serial_info(struct e100_serial *info,
3444 struct serial_struct *new_info)
3445 {
3446 struct serial_struct new_serial;
3447 struct e100_serial old_info;
3448 int retval = 0;
3449
3450 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
3451 return -EFAULT;
3452
3453 old_info = *info;
3454
3455 if (!capable(CAP_SYS_ADMIN)) {
3456 if ((new_serial.type != info->type) ||
3457 (new_serial.close_delay != info->close_delay) ||
3458 ((new_serial.flags & ~ASYNC_USR_MASK) !=
3459 (info->flags & ~ASYNC_USR_MASK)))
3460 return -EPERM;
3461 info->flags = ((info->flags & ~ASYNC_USR_MASK) |
3462 (new_serial.flags & ASYNC_USR_MASK));
3463 goto check_and_exit;
3464 }
3465
3466 if (info->count > 1)
3467 return -EBUSY;
3468
3469 /*
3470 * OK, past this point, all the error checking has been done.
3471 * At this point, we start making changes.....
3472 */
3473
3474 info->baud_base = new_serial.baud_base;
3475 info->flags = ((info->flags & ~ASYNC_FLAGS) |
3476 (new_serial.flags & ASYNC_FLAGS));
3477 info->custom_divisor = new_serial.custom_divisor;
3478 info->type = new_serial.type;
3479 info->close_delay = new_serial.close_delay;
3480 info->closing_wait = new_serial.closing_wait;
3481 info->port.tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3482
3483 check_and_exit:
3484 if (info->flags & ASYNC_INITIALIZED) {
3485 change_speed(info);
3486 } else
3487 retval = startup(info);
3488 return retval;
3489 }
3490
3491 /*
3492 * get_lsr_info - get line status register info
3493 *
3494 * Purpose: Let user call ioctl() to get info when the UART physically
3495 * is emptied. On bus types like RS485, the transmitter must
3496 * release the bus after transmitting. This must be done when
3497 * the transmit shift register is empty, not be done when the
3498 * transmit holding register is empty. This functionality
3499 * allows an RS485 driver to be written in user space.
3500 */
3501 static int
3502 get_lsr_info(struct e100_serial * info, unsigned int *value)
3503 {
3504 unsigned int result = TIOCSER_TEMT;
3505 #ifndef CONFIG_SVINTO_SIM
3506 unsigned long curr_time = jiffies;
3507 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3508 unsigned long elapsed_usec =
3509 (curr_time - info->last_tx_active) * 1000000/HZ +
3510 curr_time_usec - info->last_tx_active_usec;
3511
3512 if (info->xmit.head != info->xmit.tail ||
3513 elapsed_usec < 2*info->char_time_usec) {
3514 result = 0;
3515 }
3516 #endif
3517
3518 if (copy_to_user(value, &result, sizeof(int)))
3519 return -EFAULT;
3520 return 0;
3521 }
3522
3523 #ifdef SERIAL_DEBUG_IO
3524 struct state_str
3525 {
3526 int state;
3527 const char *str;
3528 };
3529
3530 const struct state_str control_state_str[] = {
3531 {TIOCM_DTR, "DTR" },
3532 {TIOCM_RTS, "RTS"},
3533 {TIOCM_ST, "ST?" },
3534 {TIOCM_SR, "SR?" },
3535 {TIOCM_CTS, "CTS" },
3536 {TIOCM_CD, "CD" },
3537 {TIOCM_RI, "RI" },
3538 {TIOCM_DSR, "DSR" },
3539 {0, NULL }
3540 };
3541
3542 char *get_control_state_str(int MLines, char *s)
3543 {
3544 int i = 0;
3545
3546 s[0]='\0';
3547 while (control_state_str[i].str != NULL) {
3548 if (MLines & control_state_str[i].state) {
3549 if (s[0] != '\0') {
3550 strcat(s, ", ");
3551 }
3552 strcat(s, control_state_str[i].str);
3553 }
3554 i++;
3555 }
3556 return s;
3557 }
3558 #endif
3559
3560 static int
3561 rs_break(struct tty_struct *tty, int break_state)
3562 {
3563 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3564 unsigned long flags;
3565
3566 if (!info->ioport)
3567 return -EIO;
3568
3569 local_irq_save(flags);
3570 if (break_state == -1) {
3571 /* Go to manual mode and set the txd pin to 0 */
3572 /* Clear bit 7 (txd) and 6 (tr_enable) */
3573 info->tx_ctrl &= 0x3F;
3574 } else {
3575 /* Set bit 7 (txd) and 6 (tr_enable) */
3576 info->tx_ctrl |= (0x80 | 0x40);
3577 }
3578 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
3579 local_irq_restore(flags);
3580 return 0;
3581 }
3582
3583 static int
3584 rs_tiocmset(struct tty_struct *tty, struct file *file,
3585 unsigned int set, unsigned int clear)
3586 {
3587 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3588 unsigned long flags;
3589
3590 local_irq_save(flags);
3591
3592 if (clear & TIOCM_RTS)
3593 e100_rts(info, 0);
3594 if (clear & TIOCM_DTR)
3595 e100_dtr(info, 0);
3596 /* Handle FEMALE behaviour */
3597 if (clear & TIOCM_RI)
3598 e100_ri_out(info, 0);
3599 if (clear & TIOCM_CD)
3600 e100_cd_out(info, 0);
3601
3602 if (set & TIOCM_RTS)
3603 e100_rts(info, 1);
3604 if (set & TIOCM_DTR)
3605 e100_dtr(info, 1);
3606 /* Handle FEMALE behaviour */
3607 if (set & TIOCM_RI)
3608 e100_ri_out(info, 1);
3609 if (set & TIOCM_CD)
3610 e100_cd_out(info, 1);
3611
3612 local_irq_restore(flags);
3613 return 0;
3614 }
3615
3616 static int
3617 rs_tiocmget(struct tty_struct *tty, struct file *file)
3618 {
3619 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3620 unsigned int result;
3621 unsigned long flags;
3622
3623 local_irq_save(flags);
3624
3625 result =
3626 (!E100_RTS_GET(info) ? TIOCM_RTS : 0)
3627 | (!E100_DTR_GET(info) ? TIOCM_DTR : 0)
3628 | (!E100_RI_GET(info) ? TIOCM_RNG : 0)
3629 | (!E100_DSR_GET(info) ? TIOCM_DSR : 0)
3630 | (!E100_CD_GET(info) ? TIOCM_CAR : 0)
3631 | (!E100_CTS_GET(info) ? TIOCM_CTS : 0);
3632
3633 local_irq_restore(flags);
3634
3635 #ifdef SERIAL_DEBUG_IO
3636 printk(KERN_DEBUG "ser%i: modem state: %i 0x%08X\n",
3637 info->line, result, result);
3638 {
3639 char s[100];
3640
3641 get_control_state_str(result, s);
3642 printk(KERN_DEBUG "state: %s\n", s);
3643 }
3644 #endif
3645 return result;
3646
3647 }
3648
3649
3650 static int
3651 rs_ioctl(struct tty_struct *tty, struct file * file,
3652 unsigned int cmd, unsigned long arg)
3653 {
3654 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3655
3656 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
3657 (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) &&
3658 (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) {
3659 if (tty->flags & (1 << TTY_IO_ERROR))
3660 return -EIO;
3661 }
3662
3663 switch (cmd) {
3664 case TIOCGSERIAL:
3665 return get_serial_info(info,
3666 (struct serial_struct *) arg);
3667 case TIOCSSERIAL:
3668 return set_serial_info(info,
3669 (struct serial_struct *) arg);
3670 case TIOCSERGETLSR: /* Get line status register */
3671 return get_lsr_info(info, (unsigned int *) arg);
3672
3673 case TIOCSERGSTRUCT:
3674 if (copy_to_user((struct e100_serial *) arg,
3675 info, sizeof(struct e100_serial)))
3676 return -EFAULT;
3677 return 0;
3678
3679 #if defined(CONFIG_ETRAX_RS485)
3680 case TIOCSERSETRS485:
3681 {
3682 /* In this ioctl we still use the old structure
3683 * rs485_control for backward compatibility
3684 * (if we use serial_rs485, then old user-level code
3685 * wouldn't work anymore...).
3686 * The use of this ioctl is deprecated: use TIOCSRS485
3687 * instead.*/
3688 struct rs485_control rs485ctrl;
3689 struct serial_rs485 rs485data;
3690 printk(KERN_DEBUG "The use of this ioctl is deprecated. Use TIOCSRS485 instead\n");
3691 if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg,
3692 sizeof(rs485ctrl)))
3693 return -EFAULT;
3694
3695 rs485data.delay_rts_before_send = rs485ctrl.delay_rts_before_send;
3696 rs485data.flags = 0;
3697 if (rs485ctrl.enabled)
3698 rs485data.flags |= SER_RS485_ENABLED;
3699 else
3700 rs485data.flags &= ~(SER_RS485_ENABLED);
3701
3702 if (rs485ctrl.rts_on_send)
3703 rs485data.flags |= SER_RS485_RTS_ON_SEND;
3704 else
3705 rs485data.flags &= ~(SER_RS485_RTS_ON_SEND);
3706
3707 if (rs485ctrl.rts_after_sent)
3708 rs485data.flags |= SER_RS485_RTS_AFTER_SEND;
3709 else
3710 rs485data.flags &= ~(SER_RS485_RTS_AFTER_SEND);
3711
3712 return e100_enable_rs485(tty, &rs485data);
3713 }
3714
3715 case TIOCSRS485:
3716 {
3717 /* This is the new version of TIOCSRS485, with new
3718 * data structure serial_rs485 */
3719 struct serial_rs485 rs485data;
3720 if (copy_from_user(&rs485data, (struct rs485_control *)arg,
3721 sizeof(rs485data)))
3722 return -EFAULT;
3723
3724 return e100_enable_rs485(tty, &rs485data);
3725 }
3726
3727
3728 case TIOCSERWRRS485:
3729 {
3730 struct rs485_write rs485wr;
3731 if (copy_from_user(&rs485wr, (struct rs485_write *)arg,
3732 sizeof(rs485wr)))
3733 return -EFAULT;
3734
3735 return e100_write_rs485(tty, rs485wr.outc, rs485wr.outc_size);
3736 }
3737 #endif
3738
3739 default:
3740 return -ENOIOCTLCMD;
3741 }
3742 return 0;
3743 }
3744
3745 static void
3746 rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3747 {
3748 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3749
3750 change_speed(info);
3751
3752 /* Handle turning off CRTSCTS */
3753 if ((old_termios->c_cflag & CRTSCTS) &&
3754 !(tty->termios->c_cflag & CRTSCTS)) {
3755 tty->hw_stopped = 0;
3756 rs_start(tty);
3757 }
3758
3759 }
3760
3761 /*
3762 * ------------------------------------------------------------
3763 * rs_close()
3764 *
3765 * This routine is called when the serial port gets closed. First, we
3766 * wait for the last remaining data to be sent. Then, we unlink its
3767 * S structure from the interrupt chain if necessary, and we free
3768 * that IRQ if nothing is left in the chain.
3769 * ------------------------------------------------------------
3770 */
3771 static void
3772 rs_close(struct tty_struct *tty, struct file * filp)
3773 {
3774 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3775 unsigned long flags;
3776
3777 if (!info)
3778 return;
3779
3780 /* interrupts are disabled for this entire function */
3781
3782 local_irq_save(flags);
3783
3784 if (tty_hung_up_p(filp)) {
3785 local_irq_restore(flags);
3786 return;
3787 }
3788
3789 #ifdef SERIAL_DEBUG_OPEN
3790 printk("[%d] rs_close ttyS%d, count = %d\n", current->pid,
3791 info->line, info->count);
3792 #endif
3793 if ((tty->count == 1) && (info->count != 1)) {
3794 /*
3795 * Uh, oh. tty->count is 1, which means that the tty
3796 * structure will be freed. Info->count should always
3797 * be one in these conditions. If it's greater than
3798 * one, we've got real problems, since it means the
3799 * serial port won't be shutdown.
3800 */
3801 printk(KERN_CRIT
3802 "rs_close: bad serial port count; tty->count is 1, "
3803 "info->count is %d\n", info->count);
3804 info->count = 1;
3805 }
3806 if (--info->count < 0) {
3807 printk(KERN_CRIT "rs_close: bad serial port count for ttyS%d: %d\n",
3808 info->line, info->count);
3809 info->count = 0;
3810 }
3811 if (info->count) {
3812 local_irq_restore(flags);
3813 return;
3814 }
3815 info->flags |= ASYNC_CLOSING;
3816 /*
3817 * Save the termios structure, since this port may have
3818 * separate termios for callout and dialin.
3819 */
3820 if (info->flags & ASYNC_NORMAL_ACTIVE)
3821 info->normal_termios = *tty->termios;
3822 /*
3823 * Now we wait for the transmit buffer to clear; and we notify
3824 * the line discipline to only process XON/XOFF characters.
3825 */
3826 tty->closing = 1;
3827 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE)
3828 tty_wait_until_sent(tty, info->closing_wait);
3829 /*
3830 * At this point we stop accepting input. To do this, we
3831 * disable the serial receiver and the DMA receive interrupt.
3832 */
3833 #ifdef SERIAL_HANDLE_EARLY_ERRORS
3834 e100_disable_serial_data_irq(info);
3835 #endif
3836
3837 #ifndef CONFIG_SVINTO_SIM
3838 e100_disable_rx(info);
3839 e100_disable_rx_irq(info);
3840
3841 if (info->flags & ASYNC_INITIALIZED) {
3842 /*
3843 * Before we drop DTR, make sure the UART transmitter
3844 * has completely drained; this is especially
3845 * important as we have a transmit FIFO!
3846 */
3847 rs_wait_until_sent(tty, HZ);
3848 }
3849 #endif
3850
3851 shutdown(info);
3852 rs_flush_buffer(tty);
3853 tty_ldisc_flush(tty);
3854 tty->closing = 0;
3855 info->event = 0;
3856 info->port.tty = NULL;
3857 if (info->blocked_open) {
3858 if (info->close_delay)
3859 schedule_timeout_interruptible(info->close_delay);
3860 wake_up_interruptible(&info->open_wait);
3861 }
3862 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3863 wake_up_interruptible(&info->close_wait);
3864 local_irq_restore(flags);
3865
3866 /* port closed */
3867
3868 #if defined(CONFIG_ETRAX_RS485)
3869 if (info->rs485.flags & SER_RS485_ENABLED) {
3870 info->rs485.flags &= ~(SER_RS485_ENABLED);
3871 #if defined(CONFIG_ETRAX_RS485_ON_PA)
3872 *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit);
3873 #endif
3874 #if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
3875 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3876 rs485_port_g_bit, 0);
3877 #endif
3878 #if defined(CONFIG_ETRAX_RS485_LTC1387)
3879 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3880 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 0);
3881 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3882 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 0);
3883 #endif
3884 }
3885 #endif
3886
3887 /*
3888 * Release any allocated DMA irq's.
3889 */
3890 if (info->dma_in_enabled) {
3891 free_irq(info->dma_in_irq_nbr, info);
3892 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3893 info->uses_dma_in = 0;
3894 #ifdef SERIAL_DEBUG_OPEN
3895 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3896 info->dma_in_irq_description);
3897 #endif
3898 }
3899 if (info->dma_out_enabled) {
3900 free_irq(info->dma_out_irq_nbr, info);
3901 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3902 info->uses_dma_out = 0;
3903 #ifdef SERIAL_DEBUG_OPEN
3904 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3905 info->dma_out_irq_description);
3906 #endif
3907 }
3908 }
3909
3910 /*
3911 * rs_wait_until_sent() --- wait until the transmitter is empty
3912 */
3913 static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
3914 {
3915 unsigned long orig_jiffies;
3916 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3917 unsigned long curr_time = jiffies;
3918 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3919 long elapsed_usec =
3920 (curr_time - info->last_tx_active) * (1000000/HZ) +
3921 curr_time_usec - info->last_tx_active_usec;
3922
3923 /*
3924 * Check R_DMA_CHx_STATUS bit 0-6=number of available bytes in FIFO
3925 * R_DMA_CHx_HWSW bit 31-16=nbr of bytes left in DMA buffer (0=64k)
3926 */
3927 lock_kernel();
3928 orig_jiffies = jiffies;
3929 while (info->xmit.head != info->xmit.tail || /* More in send queue */
3930 (*info->ostatusadr & 0x007f) || /* more in FIFO */
3931 (elapsed_usec < 2*info->char_time_usec)) {
3932 schedule_timeout_interruptible(1);
3933 if (signal_pending(current))
3934 break;
3935 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3936 break;
3937 curr_time = jiffies;
3938 curr_time_usec = GET_JIFFIES_USEC();
3939 elapsed_usec =
3940 (curr_time - info->last_tx_active) * (1000000/HZ) +
3941 curr_time_usec - info->last_tx_active_usec;
3942 }
3943 set_current_state(TASK_RUNNING);
3944 unlock_kernel();
3945 }
3946
3947 /*
3948 * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
3949 */
3950 void
3951 rs_hangup(struct tty_struct *tty)
3952 {
3953 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3954
3955 rs_flush_buffer(tty);
3956 shutdown(info);
3957 info->event = 0;
3958 info->count = 0;
3959 info->flags &= ~ASYNC_NORMAL_ACTIVE;
3960 info->port.tty = NULL;
3961 wake_up_interruptible(&info->open_wait);
3962 }
3963
3964 /*
3965 * ------------------------------------------------------------
3966 * rs_open() and friends
3967 * ------------------------------------------------------------
3968 */
3969 static int
3970 block_til_ready(struct tty_struct *tty, struct file * filp,
3971 struct e100_serial *info)
3972 {
3973 DECLARE_WAITQUEUE(wait, current);
3974 unsigned long flags;
3975 int retval;
3976 int do_clocal = 0, extra_count = 0;
3977
3978 /*
3979 * If the device is in the middle of being closed, then block
3980 * until it's done, and then try again.
3981 */
3982 if (tty_hung_up_p(filp) ||
3983 (info->flags & ASYNC_CLOSING)) {
3984 wait_event_interruptible(info->close_wait,
3985 !(info->flags & ASYNC_CLOSING));
3986 #ifdef SERIAL_DO_RESTART
3987 if (info->flags & ASYNC_HUP_NOTIFY)
3988 return -EAGAIN;
3989 else
3990 return -ERESTARTSYS;
3991 #else
3992 return -EAGAIN;
3993 #endif
3994 }
3995
3996 /*
3997 * If non-blocking mode is set, or the port is not enabled,
3998 * then make the check up front and then exit.
3999 */
4000 if ((filp->f_flags & O_NONBLOCK) ||
4001 (tty->flags & (1 << TTY_IO_ERROR))) {
4002 info->flags |= ASYNC_NORMAL_ACTIVE;
4003 return 0;
4004 }
4005
4006 if (tty->termios->c_cflag & CLOCAL) {
4007 do_clocal = 1;
4008 }
4009
4010 /*
4011 * Block waiting for the carrier detect and the line to become
4012 * free (i.e., not in use by the callout). While we are in
4013 * this loop, info->count is dropped by one, so that
4014 * rs_close() knows when to free things. We restore it upon
4015 * exit, either normal or abnormal.
4016 */
4017 retval = 0;
4018 add_wait_queue(&info->open_wait, &wait);
4019 #ifdef SERIAL_DEBUG_OPEN
4020 printk("block_til_ready before block: ttyS%d, count = %d\n",
4021 info->line, info->count);
4022 #endif
4023 local_irq_save(flags);
4024 if (!tty_hung_up_p(filp)) {
4025 extra_count++;
4026 info->count--;
4027 }
4028 local_irq_restore(flags);
4029 info->blocked_open++;
4030 while (1) {
4031 local_irq_save(flags);
4032 /* assert RTS and DTR */
4033 e100_rts(info, 1);
4034 e100_dtr(info, 1);
4035 local_irq_restore(flags);
4036 set_current_state(TASK_INTERRUPTIBLE);
4037 if (tty_hung_up_p(filp) ||
4038 !(info->flags & ASYNC_INITIALIZED)) {
4039 #ifdef SERIAL_DO_RESTART
4040 if (info->flags & ASYNC_HUP_NOTIFY)
4041 retval = -EAGAIN;
4042 else
4043 retval = -ERESTARTSYS;
4044 #else
4045 retval = -EAGAIN;
4046 #endif
4047 break;
4048 }
4049 if (!(info->flags & ASYNC_CLOSING) && do_clocal)
4050 /* && (do_clocal || DCD_IS_ASSERTED) */
4051 break;
4052 if (signal_pending(current)) {
4053 retval = -ERESTARTSYS;
4054 break;
4055 }
4056 #ifdef SERIAL_DEBUG_OPEN
4057 printk("block_til_ready blocking: ttyS%d, count = %d\n",
4058 info->line, info->count);
4059 #endif
4060 schedule();
4061 }
4062 set_current_state(TASK_RUNNING);
4063 remove_wait_queue(&info->open_wait, &wait);
4064 if (extra_count)
4065 info->count++;
4066 info->blocked_open--;
4067 #ifdef SERIAL_DEBUG_OPEN
4068 printk("block_til_ready after blocking: ttyS%d, count = %d\n",
4069 info->line, info->count);
4070 #endif
4071 if (retval)
4072 return retval;
4073 info->flags |= ASYNC_NORMAL_ACTIVE;
4074 return 0;
4075 }
4076
4077 static void
4078 deinit_port(struct e100_serial *info)
4079 {
4080 if (info->dma_out_enabled) {
4081 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
4082 free_irq(info->dma_out_irq_nbr, info);
4083 }
4084 if (info->dma_in_enabled) {
4085 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
4086 free_irq(info->dma_in_irq_nbr, info);
4087 }
4088 }
4089
4090 /*
4091 * This routine is called whenever a serial port is opened.
4092 * It performs the serial-specific initialization for the tty structure.
4093 */
4094 static int
4095 rs_open(struct tty_struct *tty, struct file * filp)
4096 {
4097 struct e100_serial *info;
4098 int retval, line;
4099 unsigned long page;
4100 int allocated_resources = 0;
4101
4102 /* find which port we want to open */
4103 line = tty->index;
4104
4105 if (line < 0 || line >= NR_PORTS)
4106 return -ENODEV;
4107
4108 /* find the corresponding e100_serial struct in the table */
4109 info = rs_table + line;
4110
4111 /* don't allow the opening of ports that are not enabled in the HW config */
4112 if (!info->enabled)
4113 return -ENODEV;
4114
4115 #ifdef SERIAL_DEBUG_OPEN
4116 printk("[%d] rs_open %s, count = %d\n", current->pid, tty->name,
4117 info->count);
4118 #endif
4119
4120 info->count++;
4121 tty->driver_data = info;
4122 info->port.tty = tty;
4123
4124 info->port.tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
4125
4126 if (!tmp_buf) {
4127 page = get_zeroed_page(GFP_KERNEL);
4128 if (!page) {
4129 return -ENOMEM;
4130 }
4131 if (tmp_buf)
4132 free_page(page);
4133 else
4134 tmp_buf = (unsigned char *) page;
4135 }
4136
4137 /*
4138 * If the port is in the middle of closing, bail out now
4139 */
4140 if (tty_hung_up_p(filp) ||
4141 (info->flags & ASYNC_CLOSING)) {
4142 wait_event_interruptible(info->close_wait,
4143 !(info->flags & ASYNC_CLOSING));
4144 #ifdef SERIAL_DO_RESTART
4145 return ((info->flags & ASYNC_HUP_NOTIFY) ?
4146 -EAGAIN : -ERESTARTSYS);
4147 #else
4148 return -EAGAIN;
4149 #endif
4150 }
4151
4152 /*
4153 * If DMA is enabled try to allocate the irq's.
4154 */
4155 if (info->count == 1) {
4156 allocated_resources = 1;
4157 if (info->dma_in_enabled) {
4158 if (request_irq(info->dma_in_irq_nbr,
4159 rec_interrupt,
4160 info->dma_in_irq_flags,
4161 info->dma_in_irq_description,
4162 info)) {
4163 printk(KERN_WARNING "DMA irq '%s' busy; "
4164 "falling back to non-DMA mode\n",
4165 info->dma_in_irq_description);
4166 /* Make sure we never try to use DMA in */
4167 /* for the port again. */
4168 info->dma_in_enabled = 0;
4169 } else if (cris_request_dma(info->dma_in_nbr,
4170 info->dma_in_irq_description,
4171 DMA_VERBOSE_ON_ERROR,
4172 info->dma_owner)) {
4173 free_irq(info->dma_in_irq_nbr, info);
4174 printk(KERN_WARNING "DMA '%s' busy; "
4175 "falling back to non-DMA mode\n",
4176 info->dma_in_irq_description);
4177 /* Make sure we never try to use DMA in */
4178 /* for the port again. */
4179 info->dma_in_enabled = 0;
4180 }
4181 #ifdef SERIAL_DEBUG_OPEN
4182 else
4183 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4184 info->dma_in_irq_description);
4185 #endif
4186 }
4187 if (info->dma_out_enabled) {
4188 if (request_irq(info->dma_out_irq_nbr,
4189 tr_interrupt,
4190 info->dma_out_irq_flags,
4191 info->dma_out_irq_description,
4192 info)) {
4193 printk(KERN_WARNING "DMA irq '%s' busy; "
4194 "falling back to non-DMA mode\n",
4195 info->dma_out_irq_description);
4196 /* Make sure we never try to use DMA out */
4197 /* for the port again. */
4198 info->dma_out_enabled = 0;
4199 } else if (cris_request_dma(info->dma_out_nbr,
4200 info->dma_out_irq_description,
4201 DMA_VERBOSE_ON_ERROR,
4202 info->dma_owner)) {
4203 free_irq(info->dma_out_irq_nbr, info);
4204 printk(KERN_WARNING "DMA '%s' busy; "
4205 "falling back to non-DMA mode\n",
4206 info->dma_out_irq_description);
4207 /* Make sure we never try to use DMA out */
4208 /* for the port again. */
4209 info->dma_out_enabled = 0;
4210 }
4211 #ifdef SERIAL_DEBUG_OPEN
4212 else
4213 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4214 info->dma_out_irq_description);
4215 #endif
4216 }
4217 }
4218
4219 /*
4220 * Start up the serial port
4221 */
4222
4223 retval = startup(info);
4224 if (retval) {
4225 if (allocated_resources)
4226 deinit_port(info);
4227
4228 /* FIXME Decrease count info->count here too? */
4229 return retval;
4230 }
4231
4232
4233 retval = block_til_ready(tty, filp, info);
4234 if (retval) {
4235 #ifdef SERIAL_DEBUG_OPEN
4236 printk("rs_open returning after block_til_ready with %d\n",
4237 retval);
4238 #endif
4239 if (allocated_resources)
4240 deinit_port(info);
4241
4242 return retval;
4243 }
4244
4245 if ((info->count == 1) && (info->flags & ASYNC_SPLIT_TERMIOS)) {
4246 *tty->termios = info->normal_termios;
4247 change_speed(info);
4248 }
4249
4250 #ifdef SERIAL_DEBUG_OPEN
4251 printk("rs_open ttyS%d successful...\n", info->line);
4252 #endif
4253 DLOG_INT_TRIG( log_int_pos = 0);
4254
4255 DFLIP( if (info->line == SERIAL_DEBUG_LINE) {
4256 info->icount.rx = 0;
4257 } );
4258
4259 return 0;
4260 }
4261
4262 #ifdef CONFIG_PROC_FS
4263 /*
4264 * /proc fs routines....
4265 */
4266
4267 static void seq_line_info(struct seq_file *m, struct e100_serial *info)
4268 {
4269 unsigned long tmp;
4270
4271 seq_printf(m, "%d: uart:E100 port:%lX irq:%d",
4272 info->line, (unsigned long)info->ioport, info->irq);
4273
4274 if (!info->ioport || (info->type == PORT_UNKNOWN)) {
4275 seq_printf(m, "\n");
4276 return;
4277 }
4278
4279 seq_printf(m, " baud:%d", info->baud);
4280 seq_printf(m, " tx:%lu rx:%lu",
4281 (unsigned long)info->icount.tx,
4282 (unsigned long)info->icount.rx);
4283 tmp = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
4284 if (tmp)
4285 seq_printf(m, " tx_pend:%lu/%lu",
4286 (unsigned long)tmp,
4287 (unsigned long)SERIAL_XMIT_SIZE);
4288
4289 seq_printf(m, " rx_pend:%lu/%lu",
4290 (unsigned long)info->recv_cnt,
4291 (unsigned long)info->max_recv_cnt);
4292
4293 #if 1
4294 if (info->port.tty) {
4295 if (info->port.tty->stopped)
4296 seq_printf(m, " stopped:%i",
4297 (int)info->port.tty->stopped);
4298 if (info->port.tty->hw_stopped)
4299 seq_printf(m, " hw_stopped:%i",
4300 (int)info->port.tty->hw_stopped);
4301 }
4302
4303 {
4304 unsigned char rstat = info->ioport[REG_STATUS];
4305 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect))
4306 seq_printf(m, " xoff_detect:1");
4307 }
4308
4309 #endif
4310
4311 if (info->icount.frame)
4312 seq_printf(m, " fe:%lu", (unsigned long)info->icount.frame);
4313
4314 if (info->icount.parity)
4315 seq_printf(m, " pe:%lu", (unsigned long)info->icount.parity);
4316
4317 if (info->icount.brk)
4318 seq_printf(m, " brk:%lu", (unsigned long)info->icount.brk);
4319
4320 if (info->icount.overrun)
4321 seq_printf(m, " oe:%lu", (unsigned long)info->icount.overrun);
4322
4323 /*
4324 * Last thing is the RS-232 status lines
4325 */
4326 if (!E100_RTS_GET(info))
4327 seq_puts(m, "|RTS");
4328 if (!E100_CTS_GET(info))
4329 seq_puts(m, "|CTS");
4330 if (!E100_DTR_GET(info))
4331 seq_puts(m, "|DTR");
4332 if (!E100_DSR_GET(info))
4333 seq_puts(m, "|DSR");
4334 if (!E100_CD_GET(info))
4335 seq_puts(m, "|CD");
4336 if (!E100_RI_GET(info))
4337 seq_puts(m, "|RI");
4338 seq_puts(m, "\n");
4339 }
4340
4341
4342 static int crisv10_proc_show(struct seq_file *m, void *v)
4343 {
4344 int i;
4345
4346 seq_printf(m, "serinfo:1.0 driver:%s\n", serial_version);
4347
4348 for (i = 0; i < NR_PORTS; i++) {
4349 if (!rs_table[i].enabled)
4350 continue;
4351 seq_line_info(m, &rs_table[i]);
4352 }
4353 #ifdef DEBUG_LOG_INCLUDED
4354 for (i = 0; i < debug_log_pos; i++) {
4355 seq_printf(m, "%-4i %lu.%lu ",
4356 i, debug_log[i].time,
4357 timer_data_to_ns(debug_log[i].timer_data));
4358 seq_printf(m, debug_log[i].string, debug_log[i].value);
4359 }
4360 seq_printf(m, "debug_log %i/%i\n", i, DEBUG_LOG_SIZE);
4361 debug_log_pos = 0;
4362 #endif
4363 return 0;
4364 }
4365
4366 static int crisv10_proc_open(struct inode *inode, struct file *file)
4367 {
4368 return single_open(file, crisv10_proc_show, NULL);
4369 }
4370
4371 static const struct file_operations crisv10_proc_fops = {
4372 .owner = THIS_MODULE,
4373 .open = crisv10_proc_open,
4374 .read = seq_read,
4375 .llseek = seq_lseek,
4376 .release = single_release,
4377 };
4378 #endif
4379
4380
4381 /* Finally, routines used to initialize the serial driver. */
4382
4383 static void show_serial_version(void)
4384 {
4385 printk(KERN_INFO
4386 "ETRAX 100LX serial-driver %s, "
4387 "(c) 2000-2004 Axis Communications AB\r\n",
4388 &serial_version[11]); /* "$Revision: x.yy" */
4389 }
4390
4391 /* rs_init inits the driver at boot (using the module_init chain) */
4392
4393 static const struct tty_operations rs_ops = {
4394 .open = rs_open,
4395 .close = rs_close,
4396 .write = rs_write,
4397 .flush_chars = rs_flush_chars,
4398 .write_room = rs_write_room,
4399 .chars_in_buffer = rs_chars_in_buffer,
4400 .flush_buffer = rs_flush_buffer,
4401 .ioctl = rs_ioctl,
4402 .throttle = rs_throttle,
4403 .unthrottle = rs_unthrottle,
4404 .set_termios = rs_set_termios,
4405 .stop = rs_stop,
4406 .start = rs_start,
4407 .hangup = rs_hangup,
4408 .break_ctl = rs_break,
4409 .send_xchar = rs_send_xchar,
4410 .wait_until_sent = rs_wait_until_sent,
4411 .tiocmget = rs_tiocmget,
4412 .tiocmset = rs_tiocmset,
4413 #ifdef CONFIG_PROC_FS
4414 .proc_fops = &crisv10_proc_fops,
4415 #endif
4416 };
4417
4418 static int __init rs_init(void)
4419 {
4420 int i;
4421 struct e100_serial *info;
4422 struct tty_driver *driver = alloc_tty_driver(NR_PORTS);
4423
4424 if (!driver)
4425 return -ENOMEM;
4426
4427 show_serial_version();
4428
4429 /* Setup the timed flush handler system */
4430
4431 #if !defined(CONFIG_ETRAX_SERIAL_FAST_TIMER)
4432 setup_timer(&flush_timer, timed_flush_handler, 0);
4433 mod_timer(&flush_timer, jiffies + 5);
4434 #endif
4435
4436 #if defined(CONFIG_ETRAX_RS485)
4437 #if defined(CONFIG_ETRAX_RS485_ON_PA)
4438 if (cris_io_interface_allocate_pins(if_ser0, 'a', rs485_pa_bit,
4439 rs485_pa_bit)) {
4440 printk(KERN_CRIT "ETRAX100LX serial: Could not allocate "
4441 "RS485 pin\n");
4442 put_tty_driver(driver);
4443 return -EBUSY;
4444 }
4445 #endif
4446 #if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
4447 if (cris_io_interface_allocate_pins(if_ser0, 'g', rs485_pa_bit,
4448 rs485_port_g_bit)) {
4449 printk(KERN_CRIT "ETRAX100LX serial: Could not allocate "
4450 "RS485 pin\n");
4451 put_tty_driver(driver);
4452 return -EBUSY;
4453 }
4454 #endif
4455 #endif
4456
4457 /* Initialize the tty_driver structure */
4458
4459 driver->driver_name = "serial";
4460 driver->name = "ttyS";
4461 driver->major = TTY_MAJOR;
4462 driver->minor_start = 64;
4463 driver->type = TTY_DRIVER_TYPE_SERIAL;
4464 driver->subtype = SERIAL_TYPE_NORMAL;
4465 driver->init_termios = tty_std_termios;
4466 driver->init_termios.c_cflag =
4467 B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
4468 driver->init_termios.c_ispeed = 115200;
4469 driver->init_termios.c_ospeed = 115200;
4470 driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
4471
4472 tty_set_operations(driver, &rs_ops);
4473 serial_driver = driver;
4474 if (tty_register_driver(driver))
4475 panic("Couldn't register serial driver\n");
4476 /* do some initializing for the separate ports */
4477
4478 for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) {
4479 if (info->enabled) {
4480 if (cris_request_io_interface(info->io_if,
4481 info->io_if_description)) {
4482 printk(KERN_CRIT "ETRAX100LX async serial: "
4483 "Could not allocate IO pins for "
4484 "%s, port %d\n",
4485 info->io_if_description, i);
4486 info->enabled = 0;
4487 }
4488 }
4489 info->uses_dma_in = 0;
4490 info->uses_dma_out = 0;
4491 info->line = i;
4492 info->port.tty = NULL;
4493 info->type = PORT_ETRAX;
4494 info->tr_running = 0;
4495 info->forced_eop = 0;
4496 info->baud_base = DEF_BAUD_BASE;
4497 info->custom_divisor = 0;
4498 info->flags = 0;
4499 info->close_delay = 5*HZ/10;
4500 info->closing_wait = 30*HZ;
4501 info->x_char = 0;
4502 info->event = 0;
4503 info->count = 0;
4504 info->blocked_open = 0;
4505 info->normal_termios = driver->init_termios;
4506 init_waitqueue_head(&info->open_wait);
4507 init_waitqueue_head(&info->close_wait);
4508 info->xmit.buf = NULL;
4509 info->xmit.tail = info->xmit.head = 0;
4510 info->first_recv_buffer = info->last_recv_buffer = NULL;
4511 info->recv_cnt = info->max_recv_cnt = 0;
4512 info->last_tx_active_usec = 0;
4513 info->last_tx_active = 0;
4514
4515 #if defined(CONFIG_ETRAX_RS485)
4516 /* Set sane defaults */
4517 info->rs485.flags &= ~(SER_RS485_RTS_ON_SEND);
4518 info->rs485.flags |= SER_RS485_RTS_AFTER_SEND;
4519 info->rs485.delay_rts_before_send = 0;
4520 info->rs485.flags &= ~(SER_RS485_ENABLED);
4521 #endif
4522 INIT_WORK(&info->work, do_softint);
4523
4524 if (info->enabled) {
4525 printk(KERN_INFO "%s%d at 0x%x is a builtin UART with DMA\n",
4526 serial_driver->name, info->line, (unsigned int)info->ioport);
4527 }
4528 }
4529 #ifdef CONFIG_ETRAX_FAST_TIMER
4530 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
4531 memset(fast_timers, 0, sizeof(fast_timers));
4532 #endif
4533 #ifdef CONFIG_ETRAX_RS485
4534 memset(fast_timers_rs485, 0, sizeof(fast_timers_rs485));
4535 #endif
4536 fast_timer_init();
4537 #endif
4538
4539 #ifndef CONFIG_SVINTO_SIM
4540 #ifndef CONFIG_ETRAX_KGDB
4541 /* Not needed in simulator. May only complicate stuff. */
4542 /* hook the irq's for DMA channel 6 and 7, serial output and input, and some more... */
4543
4544 if (request_irq(SERIAL_IRQ_NBR, ser_interrupt,
4545 IRQF_SHARED | IRQF_DISABLED, "serial ", driver))
4546 panic("%s: Failed to request irq8", __func__);
4547
4548 #endif
4549 #endif /* CONFIG_SVINTO_SIM */
4550
4551 return 0;
4552 }
4553
4554 /* this makes sure that rs_init is called during kernel boot */
4555
4556 module_init(rs_init);
Linux with added FPC-III support