Documentation/devicetree/bindings/display/msm/gmu.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only
   2 # Copyright 2019-2020, The Linux Foundation, All Rights Reserved
   3 %YAML 1.2
   4 ---
   5
   6 $id: "http://devicetree.org/schemas/display/msm/gmu.yaml#"
   7 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   8
   9 title: Devicetree bindings for the GMU attached to certain Adreno GPUs
  10
  11 maintainers:
  12   - Rob Clark <robdclark@gmail.com>
  13
  14 description: |
  15   These bindings describe the Graphics Management Unit (GMU) that is attached
  16   to members of the Adreno A6xx GPU family. The GMU provides on-device power
  17   management and support to improve power efficiency and reduce the load on
  18   the CPU.
  19
  20 properties:
  21   compatible:
  22     items:
  23       - enum:
  24           - qcom,adreno-gmu-630.2
  25       - const: qcom,adreno-gmu
  26
  27   reg:
  28     items:
  29       - description: Core GMU registers
  30       - description: GMU PDC registers
  31       - description: GMU PDC sequence registers
  32
  33   reg-names:
  34     items:
  35       - const: gmu
  36       - const: gmu_pdc
  37       - const: gmu_pdc_seq
  38
  39   clocks:
  40     items:
  41      - description: GMU clock
  42      - description: GPU CX clock
  43      - description: GPU AXI clock
  44      - description: GPU MEMNOC clock
  45
  46   clock-names:
  47     items:
  48       - const: gmu
  49       - const: cxo
  50       - const: axi
  51       - const: memnoc
  52
  53   interrupts:
  54     items:
  55      - description: GMU HFI interrupt
  56      - description: GMU interrupt
  57
  58
  59   interrupt-names:
  60     items:
  61       - const: hfi
  62       - const: gmu
  63
  64   power-domains:
  65      items:
  66        - description: CX power domain
  67        - description: GX power domain
  68
  69   power-domain-names:
  70      items:
  71        - const: cx
  72        - const: gx
  73
  74   iommus:
  75     maxItems: 1
  76
  77   operating-points-v2: true
  78
  79 required:
  80   - compatible
  81   - reg
  82   - reg-names
  83   - clocks
  84   - clock-names
  85   - interrupts
  86   - interrupt-names
  87   - power-domains
  88   - power-domain-names
  89   - iommus
  90   - operating-points-v2
  91
  92 examples:
  93  - |
  94    #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
  95    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  96    #include <dt-bindings/interrupt-controller/irq.h>
  97    #include <dt-bindings/interrupt-controller/arm-gic.h>
  98
  99    gmu: gmu@506a000 {
 100         compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
 101
 102         reg = <0x506a000 0x30000>,
 103               <0xb280000 0x10000>,
 104               <0xb480000 0x10000>;
 105         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
 106
 107         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
 108                  <&gpucc GPU_CC_CXO_CLK>,
 109                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
 110                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
 111         clock-names = "gmu", "cxo", "axi", "memnoc";
 112
 113         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
 114                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
 115         interrupt-names = "hfi", "gmu";
 116
 117         power-domains = <&gpucc GPU_CX_GDSC>,
 118                         <&gpucc GPU_GX_GDSC>;
 119         power-domain-names = "cx", "gx";
 120
 121         iommus = <&adreno_smmu 5>;
 122         operating-points-v2 = <&gmu_opp_table>;
 123    };