Documentation/devicetree/bindings/display/msm/gpu.txt

   1 Qualcomm adreno/snapdragon GPU
   2
   3 Required properties:
   4 - compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or
   5               "amd,imageon-XYZ.W", "amd,imageon"
   6     for example: "qcom,adreno-306.0", "qcom,adreno"
   7   Note that you need to list the less specific "qcom,adreno" (since this
   8   is what the device is matched on), in addition to the more specific
   9   with the chip-id.
  10   If "amd,imageon" is used, there should be no top level msm device.
  11 - reg: Physical base address and length of the controller's registers.
  12 - interrupts: The interrupt signal from the gpu.
  13 - clocks: device clocks (if applicable)
  14   See ../clocks/clock-bindings.txt for details.
  15 - clock-names: the following clocks are required by a3xx, a4xx and a5xx
  16   cores:
  17   * "core"
  18   * "iface"
  19   * "mem_iface"
  20   For GMU attached devices the GPU clocks are not used and are not required. The
  21   following devices should not list clocks:
  22    - qcom,adreno-630.2
  23 - iommus: optional phandle to an adreno iommu instance
  24 - operating-points-v2: optional phandle to the OPP operating points
  25 - interconnects: optional phandle to an interconnect provider.  See
  26   ../interconnect/interconnect.txt for details. Some A3xx and all A4xx platforms
  27   will have two paths; all others will have one path.
  28 - interconnect-names: The names of the interconnect paths that correspond to the
  29   interconnects property. Values must be gfx-mem and ocmem.
  30 - qcom,gmu: For GMU attached devices a phandle to the GMU device that will
  31   control the power for the GPU. Applicable targets:
  32     - qcom,adreno-630.2
  33 - zap-shader: For a5xx and a6xx devices this node contains a memory-region that
  34   points to reserved memory to store the zap shader that can be used to help
  35   bring the GPU out of secure mode.
  36 - firmware-name: optional property of the 'zap-shader' node, listing the
  37   relative path of the device specific zap firmware.
  38 - sram: phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
  39         a4xx Snapdragon SoCs. See
  40         Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.
  41
  42 Example 3xx/4xx:
  43
  44 / {
  45         ...
  46
  47         gpu: adreno@fdb00000 {
  48                 compatible = "qcom,adreno-330.2",
  49                              "qcom,adreno";
  50                 reg = <0xfdb00000 0x10000>;
  51                 reg-names = "kgsl_3d0_reg_memory";
  52                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  53                 interrupt-names = "kgsl_3d0_irq";
  54                 clock-names = "core",
  55                               "iface",
  56                               "mem_iface";
  57                 clocks = <&mmcc OXILI_GFX3D_CLK>,
  58                          <&mmcc OXILICX_AHB_CLK>,
  59                          <&mmcc OXILICX_AXI_CLK>;
  60                 sram = <&gpu_sram>;
  61                 power-domains = <&mmcc OXILICX_GDSC>;
  62                 operating-points-v2 = <&gpu_opp_table>;
  63                 iommus = <&gpu_iommu 0>;
  64         };
  65
  66         gpu_sram: ocmem@fdd00000 {
  67                 compatible = "qcom,msm8974-ocmem";
  68
  69                 reg = <0xfdd00000 0x2000>,
  70                       <0xfec00000 0x180000>;
  71                 reg-names = "ctrl",
  72                             "mem";
  73
  74                 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
  75                          <&mmcc OCMEMCX_OCMEMNOC_CLK>;
  76                 clock-names = "core",
  77                               "iface";
  78
  79                 #address-cells = <1>;
  80                 #size-cells = <1>;
  81
  82                 gpu_sram: gpu-sram@0 {
  83                         reg = <0x0 0x100000>;
  84                         ranges = <0 0 0xfec00000 0x100000>;
  85                 };
  86         };
  87 };
  88
  89 Example a6xx (with GMU):
  90
  91 / {
  92         ...
  93
  94         gpu@5000000 {
  95                 compatible = "qcom,adreno-630.2", "qcom,adreno";
  96                 #stream-id-cells = <16>;
  97
  98                 reg = <0x5000000 0x40000>, <0x509e000 0x10>;
  99                 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
 100
 101                 /*
 102                  * Look ma, no clocks! The GPU clocks and power are
 103                  * controlled entirely by the GMU
 104                  */
 105
 106                 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
 107
 108                 iommus = <&adreno_smmu 0>;
 109
 110                 operating-points-v2 = <&gpu_opp_table>;
 111
 112                 interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
 113                 interconnect-names = "gfx-mem";
 114
 115                 qcom,gmu = <&gmu>;
 116
 117                 zap-shader {
 118                         memory-region = <&zap_shader_region>;
 119                         firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"
 120                 };
 121         };
 122 };