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1 * Renesas R-Car Display Unit (DU)
3 Required Properties:
5 - compatible: must be one of the following.
6 - "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU
7 - "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU
8 - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU
9 - "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU
10 - "renesas,du-r8a774a1" for R8A774A1 (RZ/G2M) compatible DU
11 - "renesas,du-r8a774b1" for R8A774B1 (RZ/G2N) compatible DU
12 - "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU
13 - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
14 - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
15 - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
16 - "renesas,du-r8a7792" for R8A7792 (R-Car V2H) compatible DU
17 - "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU
18 - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
19 - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
20 - "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
21 - "renesas,du-r8a77965" for R8A77965 (R-Car M3-N) compatible DU
22 - "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU
23 - "renesas,du-r8a77980" for R8A77980 (R-Car V3H) compatible DU
24 - "renesas,du-r8a77990" for R8A77990 (R-Car E3) compatible DU
25 - "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU
27 - reg: the memory-mapped I/O registers base address and length
29 - interrupts: Interrupt specifiers for the DU interrupts.
31 - clocks: A list of phandles + clock-specifier pairs, one for each entry in
32 the clock-names property.
33 - clock-names: Name of the clocks. This property is model-dependent.
34 - R8A7779 uses a single functional clock. The clock doesn't need to be
35 named.
36 - All other DU instances use one functional clock per channel The
37 functional clocks must be named "du.x" with "x" being the channel
38 numerical index.
39 - In addition to the functional clocks, all DU versions also support
40 externally supplied pixel clocks. Those clocks are optional. When
41 supplied they must be named "dclkin.x" with "x" being the input clock
42 numerical index.
44 - renesas,cmms: A list of phandles to the CMM instances present in the SoC,
45 one for each available DU channel. The property shall not be specified for
46 SoCs that do not provide any CMM (such as V3M and V3H).
48 - renesas,vsps: A list of phandle and channel index tuples to the VSPs that
49 handle the memory interfaces for the DU channels. The phandle identifies the
50 VSP instance that serves the DU channel, and the channel index identifies
51 the LIF instance in that VSP.
53 Required nodes:
55 The connections to the DU output video ports are modeled using the OF graph
56 bindings specified in Documentation/devicetree/bindings/graph.txt.
58 The following table lists for each supported model the port number
59 corresponding to each DU output.
61 Port0 Port1 Port2 Port3
62 -----------------------------------------------------------------------------
63 R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - -
64 R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - -
65 R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - -
66 R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 -
67 R8A774A1 (RZ/G2M) DPAD 0 HDMI 0 LVDS 0 -
68 R8A774B1 (RZ/G2N) DPAD 0 HDMI 0 LVDS 0 -
69 R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 -
70 R8A7779 (R-Car H1) DPAD 0 DPAD 1 - -
71 R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 -
72 R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - -
73 R8A7792 (R-Car V2H) DPAD 0 DPAD 1 - -
74 R8A7793 (R-Car M2-N) DPAD 0 LVDS 0 - -
75 R8A7794 (R-Car E2) DPAD 0 DPAD 1 - -
76 R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0
77 R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 -
78 R8A77965 (R-Car M3-N) DPAD 0 HDMI 0 LVDS 0 -
79 R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - -
80 R8A77980 (R-Car V3H) DPAD 0 LVDS 0 - -
81 R8A77990 (R-Car E3) DPAD 0 LVDS 0 LVDS 1 -
82 R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 -
85 Example: R8A7795 (R-Car H3) ES2.0 DU
87 du: display@feb00000 {
88 compatible = "renesas,du-r8a7795";
89 reg = <0 0xfeb00000 0 0x80000>;
90 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
94 clocks = <&cpg CPG_MOD 724>,
95 <&cpg CPG_MOD 723>,
96 <&cpg CPG_MOD 722>,
97 <&cpg CPG_MOD 721>;
98 clock-names = "du.0", "du.1", "du.2", "du.3";
99 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
100 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
102 ports {
103 #address-cells = <1>;
104 #size-cells = <0>;
106 port@0 {
107 reg = <0>;
108 du_out_rgb: endpoint {
109 };
110 };
111 port@1 {
112 reg = <1>;
113 du_out_hdmi0: endpoint {
114 remote-endpoint = <&dw_hdmi0_in>;
115 };
116 };
117 port@2 {
118 reg = <2>;
119 du_out_hdmi1: endpoint {
120 remote-endpoint = <&dw_hdmi1_in>;
121 };
122 };
123 port@3 {
124 reg = <3>;
125 du_out_lvds0: endpoint {
126 };
127 };
128 };
129 };