Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt

   1 Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
   2
   3 This file documents the properties in addition to those available in
   4 the MTD NAND bindings.
   5
   6 Required properties:
   7 - compatible : contains one of:
   8   - "amlogic,meson-gxl-nfc"
   9   - "amlogic,meson-axg-nfc"
  10 - clocks     :
  11         A list of phandle + clock-specifier pairs for the clocks listed
  12         in clock-names.
  13
  14 - clock-names: Should contain the following:
  15         "core" - NFC module gate clock
  16         "device" - device clock from eMMC sub clock controller
  17         "rx" - rx clock phase
  18         "tx" - tx clock phase
  19
  20 - amlogic,mmc-syscon    : Required for NAND clocks, it's shared with SD/eMMC
  21                                 controller port C
  22
  23 Optional children nodes:
  24 Children nodes represent the available nand chips.
  25
  26 Other properties:
  27 see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.
  28
  29 Example demonstrate on AXG SoC:
  30
  31         sd_emmc_c_clkc: mmc@7000 {
  32                 compatible = "amlogic,meson-axg-mmc-clkc", "syscon";
  33                 reg = <0x0 0x7000 0x0 0x800>;
  34         };
  35
  36         nand-controller@7800 {
  37                 compatible = "amlogic,meson-axg-nfc";
  38                 reg = <0x0 0x7800 0x0 0x100>;
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41                 interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
  42
  43                 clocks = <&clkc CLKID_SD_EMMC_C>,
  44                         <&sd_emmc_c_clkc CLKID_MMC_DIV>,
  45                         <&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>,
  46                         <&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>;
  47                 clock-names = "core", "device", "rx", "tx";
  48                 amlogic,mmc-syscon = <&sd_emmc_c_clkc>;
  49
  50                 pinctrl-names = "default";
  51                 pinctrl-0 = <&nand_pins>;
  52
  53                 nand@0 {
  54                         reg = <0>;
  55                         #address-cells = <1>;
  56                         #size-cells = <1>;
  57
  58                         nand-on-flash-bbt;
  59                 };
  60         };