1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner H6 CPU OPP Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 For some SoCs, the CPU frequency subset and voltage value of each
15 OPP varies based on the silicon variant in use. Allwinner Process
16 Voltage Scaling Tables defines the voltage and frequency value based
17 on the speedbin blown in the efuse combination. The
18 sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
19 provide the OPP framework with required information.
23 const: allwinner,sun50i-h6-operating-points
27 A phandle pointing to a nvmem-cells node representing the efuse
28 registers that has information about the speedbin that is used
29 to select the right frequency/voltage value pair. Please refer
30 the for nvmem-cells bindings
31 Documentation/devicetree/bindings/nvmem/nvmem.txt and also
46 "opp-microvolt-.*": true
50 - opp-microvolt-speed0
51 - opp-microvolt-speed1
52 - opp-microvolt-speed2
54 unevaluatedProperties: false
56 unevaluatedProperties: false
60 cpu_opp_table: opp-table {
61 compatible = "allwinner,sun50i-h6-operating-points";
62 nvmem-cells = <&speedbin_efuse>;
66 clock-latency-ns = <244144>; /* 8 32k periods */
67 opp-hz = /bits/ 64 <480000000>;
69 opp-microvolt-speed0 = <880000>;
70 opp-microvolt-speed1 = <820000>;
71 opp-microvolt-speed2 = <800000>;
75 clock-latency-ns = <244144>; /* 8 32k periods */
76 opp-hz = /bits/ 64 <720000000>;
78 opp-microvolt-speed0 = <880000>;
79 opp-microvolt-speed1 = <820000>;
80 opp-microvolt-speed2 = <800000>;
84 clock-latency-ns = <244144>; /* 8 32k periods */
85 opp-hz = /bits/ 64 <816000000>;
87 opp-microvolt-speed0 = <880000>;
88 opp-microvolt-speed1 = <820000>;
89 opp-microvolt-speed2 = <800000>;
93 clock-latency-ns = <244144>; /* 8 32k periods */
94 opp-hz = /bits/ 64 <888000000>;
96 opp-microvolt-speed0 = <940000>;
97 opp-microvolt-speed1 = <820000>;
98 opp-microvolt-speed2 = <800000>;
102 clock-latency-ns = <244144>; /* 8 32k periods */
103 opp-hz = /bits/ 64 <1080000000>;
105 opp-microvolt-speed0 = <1060000>;
106 opp-microvolt-speed1 = <880000>;
107 opp-microvolt-speed2 = <840000>;
111 clock-latency-ns = <244144>; /* 8 32k periods */
112 opp-hz = /bits/ 64 <1320000000>;
114 opp-microvolt-speed0 = <1160000>;
115 opp-microvolt-speed1 = <940000>;
116 opp-microvolt-speed2 = <900000>;
120 clock-latency-ns = <244144>; /* 8 32k periods */
121 opp-hz = /bits/ 64 <1488000000>;
123 opp-microvolt-speed0 = <1160000>;
124 opp-microvolt-speed1 = <1000000>;
125 opp-microvolt-speed2 = <960000>;