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1 Device tree binding for NVIDIA Tegra XUSB pad controller
2 ========================================================
4 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
5 signals) which connect directly to pins/pads on the SoC package. Each lane
6 is controlled by a HW block referred to as a "pad" in the Tegra hardware
7 documentation. Each such "pad" may control either one or multiple lanes,
8 and thus contains any logic common to all its lanes. Each lane can be
9 separately configured and powered up.
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
15 ports (e.g. PCIe) and the lanes.
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
21 device tree node. Each lane exposed by the pad will be represented by its
22 own subnode and can be referenced by users of the lane using the standard
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
25 The Tegra hardware documentation refers to the connection between the XUSB
26 pad controller and the XUSB controller as "ports". This is confusing since
27 "port" is typically used to denote the physical USB receptacle. The device
28 tree binding in this document uses the term "port" to refer to the logical
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
30 for the USB signal, the VBUS power supply, the USB 2.0 companion port for
31 USB 3.0 receptacles, ...).
33 Required properties:
34 --------------------
35 - compatible: Must be:
36 - Tegra124: "nvidia,tegra124-xusb-padctl"
37 - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
38 - Tegra210: "nvidia,tegra210-xusb-padctl"
39 - Tegra186: "nvidia,tegra186-xusb-padctl"
40 - Tegra194: "nvidia,tegra194-xusb-padctl"
41 - reg: Physical base address and length of the controller's registers.
42 - resets: Must contain an entry for each entry in reset-names.
43 - reset-names: Must include the following entries:
44 - "padctl"
46 For Tegra124:
47 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
48 - avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
49 - avdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
50 - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.
52 For Tegra210:
53 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
54 - avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
55 - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
56 - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
58 For Tegra186:
59 - avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY
60 power supply. Must supply 1.8 V.
61 - avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
62 3.3 V.
63 - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
64 - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
66 For Tegra194:
67 - avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
68 3.3 V.
69 - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
71 Pad nodes:
72 ==========
74 A required child node named "pads" contains a list of subnodes, one for each
75 of the pads exposed by the XUSB pad controller. Each pad may need additional
76 resources that can be referenced in its pad node.
78 The "status" property is used to enable or disable the use of a pad. If set
79 to "disabled", the pad will not be used on the given board. In order to use
80 the pad and any of its lanes, this property must be set to "okay".
82 For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
83 and sata. No extra resources are required for operation of these pads.
85 For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
86 a description of the properties of each pad.
88 UTMI pad:
89 ---------
91 Required properties:
92 - clocks: Must contain an entry for each entry in clock-names.
93 - clock-names: Must contain the following entries:
94 - "trk": phandle and specifier referring to the USB2 tracking clock
96 HSIC pad:
97 ---------
99 Required properties:
100 - clocks: Must contain an entry for each entry in clock-names.
101 - clock-names: Must contain the following entries:
102 - "trk": phandle and specifier referring to the HSIC tracking clock
104 PCIe pad:
105 ---------
107 Required properties:
108 - clocks: Must contain an entry for each entry in clock-names.
109 - clock-names: Must contain the following entries:
110 - "pll": phandle and specifier referring to the PLLE
111 - resets: Must contain an entry for each entry in reset-names.
112 - reset-names: Must contain the following entries:
113 - "phy": reset for the PCIe UPHY block
115 SATA pad:
116 ---------
118 Required properties:
119 - resets: Must contain an entry for each entry in reset-names.
120 - reset-names: Must contain the following entries:
121 - "phy": reset for the SATA UPHY block
124 PHY nodes:
125 ==========
127 Each pad node has a child named "lanes" that contains one or more children of
128 its own, each representing one of the lanes controlled by the pad.
130 Required properties:
131 --------------------
132 - status: Defines the operation status of the PHY. Valid values are:
133 - "disabled": the PHY is disabled
134 - "okay": the PHY is enabled
135 - #phy-cells: Should be 0. Since each lane represents a single PHY, there is
136 no need for an additional specifier.
137 - nvidia,function: The output function of the PHY. See below for a list of
138 valid functions per SoC generation.
140 For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
141 - usb2: usb2-0, usb2-1, usb2-2
142 - functions: "snps", "xusb", "uart"
143 - ulpi: ulpi-0
144 - functions: "snps", "xusb"
145 - hsic: hsic-0, hsic-1
146 - functions: "snps", "xusb"
147 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4
148 - functions: "pcie", "usb3-ss"
149 - sata: sata-0
150 - functions: "usb3-ss", "sata"
152 For Tegra210, the list of valid PHY nodes is given below:
153 - usb2: usb2-0, usb2-1, usb2-2, usb2-3
154 - functions: "snps", "xusb", "uart"
155 - hsic: hsic-0, hsic-1
156 - functions: "snps", "xusb"
157 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6
158 - functions: "pcie-x1", "usb3-ss", "pcie-x4"
159 - sata: sata-0
160 - functions: "usb3-ss", "sata"
162 For Tegra194, the list of valid PHY nodes is given below:
163 - usb2: usb2-0, usb2-1, usb2-2, usb2-3
164 - functions: "xusb"
165 - usb3: usb3-0, usb3-1, usb3-2, usb3-3
166 - functions: "xusb"
168 Port nodes:
169 ===========
171 A required child node named "ports" contains a list of all the ports exposed
172 by the XUSB pad controller. Per-port configuration is only required for USB.
174 USB2 ports:
175 -----------
177 Required properties:
178 - status: Defines the operation status of the port. Valid values are:
179 - "disabled": the port is disabled
180 - "okay": the port is enabled
181 - mode: A string that determines the mode in which to run the port. Valid
182 values are:
183 - "host": for USB host mode
184 - "device": for USB device mode
185 - "otg": for USB OTG mode
187 Required properties for OTG/Peripheral capable USB2 ports:
188 - usb-role-switch: Boolean property to indicate that the port support OTG or
189 peripheral mode. If present, the port supports switching between USB host
190 and peripheral roles. Connector should be added as subnode.
191 See usb/usb-conn-gpio.txt.
193 Optional properties:
194 - nvidia,internal: A boolean property whose presence determines that a port
195 is internal. In the absence of this property the port is considered to be
196 external.
197 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
199 ULPI ports:
200 -----------
202 Optional properties:
203 - status: Defines the operation status of the port. Valid values are:
204 - "disabled": the port is disabled
205 - "okay": the port is enabled
206 - nvidia,internal: A boolean property whose presence determines that a port
207 is internal. In the absence of this property the port is considered to be
208 external.
209 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
211 HSIC ports:
212 -----------
214 Required properties:
215 - status: Defines the operation status of the port. Valid values are:
216 - "disabled": the port is disabled
217 - "okay": the port is enabled
219 Optional properties:
220 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
222 Super-speed USB ports:
223 ----------------------
225 Required properties:
226 - status: Defines the operation status of the port. Valid values are:
227 - "disabled": the port is disabled
228 - "okay": the port is enabled
229 - nvidia,usb2-companion: A single cell that specifies the physical port number
230 to map this super-speed USB port to. The range of valid port numbers varies
231 with the SoC generation:
232 - 0-2: for Tegra124 and Tegra132
233 - 0-3: for Tegra210
235 Optional properties:
236 - nvidia,internal: A boolean property whose presence determines that a port
237 is internal. In the absence of this property the port is considered to be
238 external.
240 - maximum-speed: Only for Tegra194. A string property that specifies maximum
241 supported speed of a usb3 port. Valid values are:
242 - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed.
243 - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only.
245 For Tegra124 and Tegra132, the XUSB pad controller exposes the following
246 ports:
247 - 3x USB2: usb2-0, usb2-1, usb2-2
248 - 1x ULPI: ulpi-0
249 - 2x HSIC: hsic-0, hsic-1
250 - 2x super-speed USB: usb3-0, usb3-1
252 For Tegra210, the XUSB pad controller exposes the following ports:
253 - 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
254 - 2x HSIC: hsic-0, hsic-1
255 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
257 For Tegra194, the XUSB pad controller exposes the following ports:
258 - 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
259 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
261 Examples:
262 =========
264 Tegra124 and Tegra132:
265 ----------------------
267 SoC include:
269 padctl@7009f000 {
270 /* for Tegra124 */
271 compatible = "nvidia,tegra124-xusb-padctl";
272 /* for Tegra132 */
273 compatible = "nvidia,tegra132-xusb-padctl",
274 "nvidia,tegra124-xusb-padctl";
275 reg = <0x0 0x7009f000 0x0 0x1000>;
276 resets = <&tegra_car 142>;
277 reset-names = "padctl";
279 pads {
280 usb2 {
281 status = "disabled";
283 lanes {
284 usb2-0 {
285 status = "disabled";
286 #phy-cells = <0>;
287 };
289 usb2-1 {
290 status = "disabled";
291 #phy-cells = <0>;
292 };
294 usb2-2 {
295 status = "disabled";
296 #phy-cells = <0>;
297 };
298 };
299 };
301 ulpi {
302 status = "disabled";
304 lanes {
305 ulpi-0 {
306 status = "disabled";
307 #phy-cells = <0>;
308 };
309 };
310 };
312 hsic {
313 status = "disabled";
315 lanes {
316 hsic-0 {
317 status = "disabled";
318 #phy-cells = <0>;
319 };
321 hsic-1 {
322 status = "disabled";
323 #phy-cells = <0>;
324 };
325 };
326 };
328 pcie {
329 status = "disabled";
331 lanes {
332 pcie-0 {
333 status = "disabled";
334 #phy-cells = <0>;
335 };
337 pcie-1 {
338 status = "disabled";
339 #phy-cells = <0>;
340 };
342 pcie-2 {
343 status = "disabled";
344 #phy-cells = <0>;
345 };
347 pcie-3 {
348 status = "disabled";
349 #phy-cells = <0>;
350 };
352 pcie-4 {
353 status = "disabled";
354 #phy-cells = <0>;
355 };
356 };
357 };
359 sata {
360 status = "disabled";
362 lanes {
363 sata-0 {
364 status = "disabled";
365 #phy-cells = <0>;
366 };
367 };
368 };
369 };
371 ports {
372 usb2-0 {
373 status = "disabled";
374 };
376 usb2-1 {
377 status = "disabled";
378 };
380 usb2-2 {
381 status = "disabled";
382 };
384 ulpi-0 {
385 status = "disabled";
386 };
388 hsic-0 {
389 status = "disabled";
390 };
392 hsic-1 {
393 status = "disabled";
394 };
396 usb3-0 {
397 status = "disabled";
398 };
400 usb3-1 {
401 status = "disabled";
402 };
403 };
404 };
406 Board file:
408 padctl@7009f000 {
409 status = "okay";
411 pads {
412 usb2 {
413 status = "okay";
415 lanes {
416 usb2-0 {
417 nvidia,function = "xusb";
418 status = "okay";
419 };
421 usb2-1 {
422 nvidia,function = "xusb";
423 status = "okay";
424 };
426 usb2-2 {
427 nvidia,function = "xusb";
428 status = "okay";
429 };
430 };
431 };
433 pcie {
434 status = "okay";
436 lanes {
437 pcie-0 {
438 nvidia,function = "usb3-ss";
439 status = "okay";
440 };
442 pcie-2 {
443 nvidia,function = "pcie";
444 status = "okay";
445 };
447 pcie-4 {
448 nvidia,function = "pcie";
449 status = "okay";
450 };
451 };
452 };
454 sata {
455 status = "okay";
457 lanes {
458 sata-0 {
459 nvidia,function = "sata";
460 status = "okay";
461 };
462 };
463 };
464 };
466 ports {
467 /* Micro A/B */
468 usb2-0 {
469 status = "okay";
470 mode = "otg";
471 };
473 /* Mini PCIe */
474 usb2-1 {
475 status = "okay";
476 mode = "host";
477 };
479 /* USB3 */
480 usb2-2 {
481 status = "okay";
482 mode = "host";
484 vbus-supply = <&vdd_usb3_vbus>;
485 };
487 usb3-0 {
488 nvidia,port = <2>;
489 status = "okay";
490 };
491 };
492 };
494 Tegra210:
495 ---------
497 SoC include:
499 padctl@7009f000 {
500 compatible = "nvidia,tegra210-xusb-padctl";
501 reg = <0x0 0x7009f000 0x0 0x1000>;
502 resets = <&tegra_car 142>;
503 reset-names = "padctl";
505 status = "disabled";
507 pads {
508 usb2 {
509 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
510 clock-names = "trk";
511 status = "disabled";
513 lanes {
514 usb2-0 {
515 status = "disabled";
516 #phy-cells = <0>;
517 };
519 usb2-1 {
520 status = "disabled";
521 #phy-cells = <0>;
522 };
524 usb2-2 {
525 status = "disabled";
526 #phy-cells = <0>;
527 };
529 usb2-3 {
530 status = "disabled";
531 #phy-cells = <0>;
532 };
533 };
534 };
536 hsic {
537 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
538 clock-names = "trk";
539 status = "disabled";
541 lanes {
542 hsic-0 {
543 status = "disabled";
544 #phy-cells = <0>;
545 };
547 hsic-1 {
548 status = "disabled";
549 #phy-cells = <0>;
550 };
551 };
552 };
554 pcie {
555 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
556 clock-names = "pll";
557 resets = <&tegra_car 205>;
558 reset-names = "phy";
559 status = "disabled";
561 lanes {
562 pcie-0 {
563 status = "disabled";
564 #phy-cells = <0>;
565 };
567 pcie-1 {
568 status = "disabled";
569 #phy-cells = <0>;
570 };
572 pcie-2 {
573 status = "disabled";
574 #phy-cells = <0>;
575 };
577 pcie-3 {
578 status = "disabled";
579 #phy-cells = <0>;
580 };
582 pcie-4 {
583 status = "disabled";
584 #phy-cells = <0>;
585 };
587 pcie-5 {
588 status = "disabled";
589 #phy-cells = <0>;
590 };
592 pcie-6 {
593 status = "disabled";
594 #phy-cells = <0>;
595 };
596 };
597 };
599 sata {
600 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
601 clock-names = "pll";
602 resets = <&tegra_car 204>;
603 reset-names = "phy";
604 status = "disabled";
606 lanes {
607 sata-0 {
608 status = "disabled";
609 #phy-cells = <0>;
610 };
611 };
612 };
613 };
615 ports {
616 usb2-0 {
617 status = "disabled";
618 };
620 usb2-1 {
621 status = "disabled";
622 };
624 usb2-2 {
625 status = "disabled";
626 };
628 usb2-3 {
629 status = "disabled";
630 };
632 hsic-0 {
633 status = "disabled";
634 };
636 hsic-1 {
637 status = "disabled";
638 };
640 usb3-0 {
641 status = "disabled";
642 };
644 usb3-1 {
645 status = "disabled";
646 };
648 usb3-2 {
649 status = "disabled";
650 };
652 usb3-3 {
653 status = "disabled";
654 };
655 };
656 };
658 Board file:
660 padctl@7009f000 {
661 status = "okay";
663 pads {
664 usb2 {
665 status = "okay";
667 lanes {
668 usb2-0 {
669 nvidia,function = "xusb";
670 status = "okay";
671 };
673 usb2-1 {
674 nvidia,function = "xusb";
675 status = "okay";
676 };
678 usb2-2 {
679 nvidia,function = "xusb";
680 status = "okay";
681 };
683 usb2-3 {
684 nvidia,function = "xusb";
685 status = "okay";
686 };
687 };
688 };
690 pcie {
691 status = "okay";
693 lanes {
694 pcie-0 {
695 nvidia,function = "pcie-x1";
696 status = "okay";
697 };
699 pcie-1 {
700 nvidia,function = "pcie-x4";
701 status = "okay";
702 };
704 pcie-2 {
705 nvidia,function = "pcie-x4";
706 status = "okay";
707 };
709 pcie-3 {
710 nvidia,function = "pcie-x4";
711 status = "okay";
712 };
714 pcie-4 {
715 nvidia,function = "pcie-x4";
716 status = "okay";
717 };
719 pcie-5 {
720 nvidia,function = "usb3-ss";
721 status = "okay";
722 };
724 pcie-6 {
725 nvidia,function = "usb3-ss";
726 status = "okay";
727 };
728 };
729 };
731 sata {
732 status = "okay";
734 lanes {
735 sata-0 {
736 nvidia,function = "sata";
737 status = "okay";
738 };
739 };
740 };
741 };
743 ports {
744 usb2-0 {
745 status = "okay";
746 mode = "otg";
747 };
749 usb2-1 {
750 status = "okay";
751 vbus-supply = <&vdd_5v0_rtl>;
752 mode = "host";
753 };
755 usb2-2 {
756 status = "okay";
757 vbus-supply = <&vdd_usb_vbus>;
758 mode = "host";
759 };
761 usb2-3 {
762 status = "okay";
763 mode = "host";
764 };
766 usb3-0 {
767 status = "okay";
768 nvidia,lanes = "pcie-6";
769 nvidia,port = <1>;
770 };
772 usb3-1 {
773 status = "okay";
774 nvidia,lanes = "pcie-5";
775 nvidia,port = <2>;
776 };
777 };
778 };