Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Rockchip USB2.0 phy with inno IP block
   8
   9 maintainers:
  10   - Heiko Stuebner <heiko@sntech.de>
  11
  12 properties:
  13   compatible:
  14     enum:
  15       - rockchip,px30-usb2phy
  16       - rockchip,rk3228-usb2phy
  17       - rockchip,rk3328-usb2phy
  18       - rockchip,rk3366-usb2phy
  19       - rockchip,rk3399-usb2phy
  20       - rockchip,rv1108-usb2phy
  21
  22   reg:
  23     maxItems: 1
  24
  25   clock-output-names:
  26     description:
  27       The usb 480m output clock name.
  28
  29   "#clock-cells":
  30     const: 0
  31
  32   "#phy-cells":
  33     const: 0
  34
  35   clocks:
  36     maxItems: 1
  37
  38   clock-names:
  39     const: phyclk
  40
  41   assigned-clocks:
  42     description:
  43       Phandle of the usb 480m clock.
  44
  45   assigned-clock-parents:
  46     description:
  47       Parent of the usb 480m clock.
  48       Select between usb-phy output 480m and xin24m.
  49       Refer to clk/clock-bindings.txt for generic clock consumer properties.
  50
  51   extcon:
  52     description:
  53       Phandle to the extcon device providing the cable state for the otg phy.
  54
  55   rockchip,usbgrf:
  56     $ref: /schemas/types.yaml#/definitions/phandle
  57     description:
  58       Phandle to the syscon managing the 'usb general register files'.
  59       When set the driver will request its phandle as one companion-grf
  60       for some special SoCs (e.g rv1108).
  61
  62   host-port:
  63     type: object
  64     additionalProperties: false
  65
  66     properties:
  67       "#phy-cells":
  68         const: 0
  69
  70       interrupts:
  71         description: host linestate interrupt
  72
  73       interrupt-names:
  74         const: linestate
  75
  76       phy-supply:
  77         description:
  78           Phandle to a regulator that provides power to VBUS.
  79           See ./phy-bindings.txt for details.
  80
  81     required:
  82       - "#phy-cells"
  83       - interrupts
  84       - interrupt-names
  85
  86   otg-port:
  87     type: object
  88     additionalProperties: false
  89
  90     properties:
  91       "#phy-cells":
  92         const: 0
  93
  94       interrupts:
  95         minItems: 1
  96         maxItems: 3
  97
  98       interrupt-names:
  99         oneOf:
 100           - const: linestate
 101           - const: otg-mux
 102           - items:
 103             - const: otg-bvalid
 104             - const: otg-id
 105             - const: linestate
 106
 107       phy-supply:
 108         description:
 109           Phandle to a regulator that provides power to VBUS.
 110           See ./phy-bindings.txt for details.
 111
 112     required:
 113       - "#phy-cells"
 114       - interrupts
 115       - interrupt-names
 116
 117 required:
 118   - compatible
 119   - reg
 120   - clock-output-names
 121   - "#clock-cells"
 122   - "#phy-cells"
 123   - host-port
 124   - otg-port
 125
 126 additionalProperties: false
 127
 128 examples:
 129   - |
 130     #include <dt-bindings/clock/rk3399-cru.h>
 131     #include <dt-bindings/interrupt-controller/arm-gic.h>
 132     #include <dt-bindings/interrupt-controller/irq.h>
 133     u2phy0: usb2-phy@e450 {
 134       compatible = "rockchip,rk3399-usb2phy";
 135       reg = <0xe450 0x10>;
 136       clocks = <&cru SCLK_USB2PHY0_REF>;
 137       clock-names = "phyclk";
 138       clock-output-names = "clk_usbphy0_480m";
 139       #clock-cells = <0>;
 140       #phy-cells = <0>;
 141
 142       u2phy0_host: host-port {
 143         #phy-cells = <0>;
 144         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
 145         interrupt-names = "linestate";
 146       };
 147
 148       u2phy0_otg: otg-port {
 149         #phy-cells = <0>;
 150         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
 151                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
 152                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
 153         interrupt-names = "otg-bvalid", "otg-id", "linestate";
 154       };
 155     };