Documentation/devicetree/bindings/serial/renesas,scif.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: "http://devicetree.org/schemas/serial/renesas,scif.yaml#"
   5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   6
   7 title: Renesas Serial Communication Interface with FIFO (SCIF)
   8
   9 maintainers:
  10   - Geert Uytterhoeven <geert+renesas@glider.be>
  11
  12 allOf:
  13   - $ref: serial.yaml#
  14
  15 properties:
  16   compatible:
  17     oneOf:
  18       - items:
  19           - enum:
  20               - renesas,scif-r7s72100     # RZ/A1H
  21           - const: renesas,scif           # generic SCIF compatible UART
  22
  23       - items:
  24           - enum:
  25               - renesas,scif-r7s9210      # RZ/A2
  26
  27       - items:
  28           - enum:
  29               - renesas,scif-r8a7778      # R-Car M1
  30               - renesas,scif-r8a7779      # R-Car H1
  31           - const: renesas,rcar-gen1-scif # R-Car Gen1
  32           - const: renesas,scif           # generic SCIF compatible UART
  33
  34       - items:
  35           - enum:
  36               - renesas,scif-r8a7743      # RZ/G1M
  37               - renesas,scif-r8a7744      # RZ/G1N
  38               - renesas,scif-r8a7745      # RZ/G1E
  39               - renesas,scif-r8a77470     # RZ/G1C
  40               - renesas,scif-r8a7790      # R-Car H2
  41               - renesas,scif-r8a7791      # R-Car M2-W
  42               - renesas,scif-r8a7792      # R-Car V2H
  43               - renesas,scif-r8a7793      # R-Car M2-N
  44               - renesas,scif-r8a7794      # R-Car E2
  45           - const: renesas,rcar-gen2-scif # R-Car Gen2 and RZ/G1
  46           - const: renesas,scif           # generic SCIF compatible UART
  47
  48       - items:
  49           - enum:
  50               - renesas,scif-r8a774a1     # RZ/G2M
  51               - renesas,scif-r8a774b1     # RZ/G2N
  52               - renesas,scif-r8a774c0     # RZ/G2E
  53               - renesas,scif-r8a7795      # R-Car H3
  54               - renesas,scif-r8a7796      # R-Car M3-W
  55               - renesas,scif-r8a77961     # R-Car M3-W+
  56               - renesas,scif-r8a77965     # R-Car M3-N
  57               - renesas,scif-r8a77970     # R-Car V3M
  58               - renesas,scif-r8a77980     # R-Car V3H
  59               - renesas,scif-r8a77990     # R-Car E3
  60               - renesas,scif-r8a77995     # R-Car D3
  61           - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2
  62           - const: renesas,scif           # generic SCIF compatible UART
  63
  64   reg:
  65     maxItems: 1
  66
  67   interrupts:
  68     oneOf:
  69       - items:
  70           - description: A combined interrupt
  71       - items:
  72           - description: Error interrupt
  73           - description: Receive buffer full interrupt
  74           - description: Transmit buffer empty interrupt
  75           - description: Transmit End interrupt
  76       - items:
  77           - description: Error interrupt
  78           - description: Receive buffer full interrupt
  79           - description: Transmit buffer empty interrupt
  80           - description: Break interrupt
  81           - description: Data Ready interrupt
  82           - description: Transmit End interrupt
  83
  84   interrupt-names:
  85     oneOf:
  86       - items:
  87           - const: eri
  88           - const: rxi
  89           - const: txi
  90           - const: tei
  91       - items:
  92           - const: eri
  93           - const: rxi
  94           - const: txi
  95           - const: bri
  96           - const: dri
  97           - const: tei
  98
  99   clocks:
 100     minItems: 1
 101     maxItems: 4
 102
 103   clock-names:
 104     minItems: 1
 105     maxItems: 4
 106     items:
 107       enum:
 108         - fck # UART functional clock
 109         - sck # optional external clock input
 110         - brg_int # optional internal clock source for BRG frequency divider
 111         - scif_clk # optional external clock source for BRG frequency divider
 112
 113   power-domains:
 114     maxItems: 1
 115
 116   resets:
 117     maxItems: 1
 118
 119   dmas:
 120     description:
 121       Must contain a list of pairs of references to DMA specifiers, one for
 122       transmission, and one for reception.
 123
 124   dma-names:
 125     minItems: 2
 126     maxItems: 4
 127     items:
 128       enum:
 129         - tx
 130         - rx
 131
 132 required:
 133   - compatible
 134   - reg
 135   - interrupts
 136   - clocks
 137   - clock-names
 138   - power-domains
 139
 140 if:
 141   properties:
 142     compatible:
 143       contains:
 144         enum:
 145           - renesas,rcar-gen2-scif
 146           - renesas,rcar-gen3-scif
 147 then:
 148   required:
 149     - resets
 150
 151 examples:
 152   - |
 153     #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
 154     #include <dt-bindings/interrupt-controller/arm-gic.h>
 155     #include <dt-bindings/power/r8a7791-sysc.h>
 156     aliases {
 157             serial0 = &scif0;
 158     };
 159
 160     scif0: serial@e6e60000 {
 161             compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 162                          "renesas,scif";
 163             reg = <0xe6e60000 64>;
 164             interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 165             clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
 166                      <&scif_clk>;
 167             clock-names = "fck", "brg_int", "scif_clk";
 168             dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>;
 169             dma-names = "tx", "rx", "tx", "rx";
 170             power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 171             resets = <&cpg 721>;
 172     };