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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / clk / clk-ast2600.c
blob392d01705b97bbfc0bcd49a253d40440b89f5f78
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 // Copyright IBM Corp
3 // Copyright ASPEED Technology
4
5 #define pr_fmt(fmt) "clk-ast2600: " fmt
6
7 #include <linux/mfd/syscon.h>
8 #include <linux/of_address.h>
9 #include <linux/of_device.h>
10 #include <linux/platform_device.h>
11 #include <linux/regmap.h>
12 #include <linux/slab.h>
13
14 #include <dt-bindings/clock/ast2600-clock.h>
15
16 #include "clk-aspeed.h"
17
18 #define ASPEED_G6_NUM_CLKS 71
19
20 #define ASPEED_G6_SILICON_REV 0x004
21
22 #define ASPEED_G6_RESET_CTRL 0x040
23 #define ASPEED_G6_RESET_CTRL2 0x050
24
25 #define ASPEED_G6_CLK_STOP_CTRL 0x080
26 #define ASPEED_G6_CLK_STOP_CTRL2 0x090
27
28 #define ASPEED_G6_MISC_CTRL 0x0C0
29 #define UART_DIV13_EN BIT(12)
30
31 #define ASPEED_G6_CLK_SELECTION1 0x300
32 #define ASPEED_G6_CLK_SELECTION2 0x304
33 #define ASPEED_G6_CLK_SELECTION4 0x310
34
35 #define ASPEED_HPLL_PARAM 0x200
36 #define ASPEED_APLL_PARAM 0x210
37 #define ASPEED_MPLL_PARAM 0x220
38 #define ASPEED_EPLL_PARAM 0x240
39 #define ASPEED_DPLL_PARAM 0x260
40
41 #define ASPEED_G6_STRAP1 0x500
42
43 #define ASPEED_MAC12_CLK_DLY 0x340
44 #define ASPEED_MAC34_CLK_DLY 0x350
45
46 /* Globally visible clocks */
47 static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
48
49 /* Keeps track of all clocks */
50 static struct clk_hw_onecell_data *aspeed_g6_clk_data;
51
52 static void __iomem *scu_g6_base;
53
54 /*
55 * Clocks marked with CLK_IS_CRITICAL:
56 *
57 * ref0 and ref1 are essential for the SoC to operate
58 * mpll is required if SDRAM is used
59 */
60 static const struct aspeed_gate_data aspeed_g6_gates[] = {
61 /* clk rst name parent flags */
62 [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
63 [ASPEED_CLK_GATE_ECLK] = { 1, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
64 [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
65 /* vclk parent - dclk/d1clk/hclk/mclk */
66 [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
67 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
68 /* From dpll */
69 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
70 [ASPEED_CLK_GATE_REF0CLK] = { 6, -1, "ref0clk-gate", "clkin", CLK_IS_CRITICAL },
71 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
72 /* Reserved 8 */
73 [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
74 /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
75 [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", "d1clk", 0 }, /* GFX CRT */
76 /* Reserved 11/12 */
77 [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
78 [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
79 [ASPEED_CLK_GATE_UART5CLK] = { 15, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
80 /* Reserved 16/19 */
81 [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac12", 0 }, /* MAC1 */
82 [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac12", 0 }, /* MAC2 */
83 /* Reserved 22/23 */
84 [ASPEED_CLK_GATE_RSACLK] = { 24, 4, "rsaclk-gate", NULL, 0 }, /* HAC */
85 [ASPEED_CLK_GATE_RVASCLK] = { 25, 9, "rvasclk-gate", NULL, 0 }, /* RVAS */
86 /* Reserved 26 */
87 [ASPEED_CLK_GATE_EMMCCLK] = { 27, 16, "emmcclk-gate", NULL, 0 }, /* For card clk */
88 /* Reserved 28/29/30 */
89 [ASPEED_CLK_GATE_LCLK] = { 32, 32, "lclk-gate", NULL, 0 }, /* LPC */
90 [ASPEED_CLK_GATE_ESPICLK] = { 33, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
91 [ASPEED_CLK_GATE_REF1CLK] = { 34, -1, "ref1clk-gate", "clkin", CLK_IS_CRITICAL },
92 /* Reserved 35 */
93 [ASPEED_CLK_GATE_SDCLK] = { 36, 56, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
94 [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
95 /* Reserved 38 RSA: no longer used */
96 /* Reserved 39 */
97 [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */
98 [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */
99 [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */
100 [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */
101 [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */
102 [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */
103 [ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */
104 [ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */
105 [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
106 [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
107 [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
108 [ASPEED_CLK_GATE_UART4CLK] = { 51, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
109 [ASPEED_CLK_GATE_MAC3CLK] = { 52, 52, "mac3clk-gate", "mac34", 0 }, /* MAC3 */
110 [ASPEED_CLK_GATE_MAC4CLK] = { 53, 53, "mac4clk-gate", "mac34", 0 }, /* MAC4 */
111 [ASPEED_CLK_GATE_UART6CLK] = { 54, -1, "uart6clk-gate", "uartx", 0 }, /* UART6 */
112 [ASPEED_CLK_GATE_UART7CLK] = { 55, -1, "uart7clk-gate", "uartx", 0 }, /* UART7 */
113 [ASPEED_CLK_GATE_UART8CLK] = { 56, -1, "uart8clk-gate", "uartx", 0 }, /* UART8 */
114 [ASPEED_CLK_GATE_UART9CLK] = { 57, -1, "uart9clk-gate", "uartx", 0 }, /* UART9 */
115 [ASPEED_CLK_GATE_UART10CLK] = { 58, -1, "uart10clk-gate", "uartx", 0 }, /* UART10 */
116 [ASPEED_CLK_GATE_UART11CLK] = { 59, -1, "uart11clk-gate", "uartx", 0 }, /* UART11 */
117 [ASPEED_CLK_GATE_UART12CLK] = { 60, -1, "uart12clk-gate", "uartx", 0 }, /* UART12 */
118 [ASPEED_CLK_GATE_UART13CLK] = { 61, -1, "uart13clk-gate", "uartx", 0 }, /* UART13 */
119 [ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", NULL, 0 }, /* FSI */
120 };
121
122 static const struct clk_div_table ast2600_eclk_div_table[] = {
123 { 0x0, 2 },
124 { 0x1, 2 },
125 { 0x2, 3 },
126 { 0x3, 4 },
127 { 0x4, 5 },
128 { 0x5, 6 },
129 { 0x6, 7 },
130 { 0x7, 8 },
131 { 0 }
132 };
133
134 static const struct clk_div_table ast2600_mac_div_table[] = {
135 { 0x0, 4 },
136 { 0x1, 4 },
137 { 0x2, 6 },
138 { 0x3, 8 },
139 { 0x4, 10 },
140 { 0x5, 12 },
141 { 0x6, 14 },
142 { 0x7, 16 },
143 { 0 }
144 };
145
146 static const struct clk_div_table ast2600_div_table[] = {
147 { 0x0, 4 },
148 { 0x1, 8 },
149 { 0x2, 12 },
150 { 0x3, 16 },
151 { 0x4, 20 },
152 { 0x5, 24 },
153 { 0x6, 28 },
154 { 0x7, 32 },
155 { 0 }
156 };
157
158 /* For hpll/dpll/epll/mpll */
159 static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
160 {
161 unsigned int mult, div;
162
163 if (val & BIT(24)) {
164 /* Pass through mode */
165 mult = div = 1;
166 } else {
167 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
168 u32 m = val & 0x1fff;
169 u32 n = (val >> 13) & 0x3f;
170 u32 p = (val >> 19) & 0xf;
171 mult = (m + 1) / (n + 1);
172 div = (p + 1);
173 }
174 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
175 mult, div);
176 };
177
178 static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
179 {
180 unsigned int mult, div;
181
182 if (val & BIT(20)) {
183 /* Pass through mode */
184 mult = div = 1;
185 } else {
186 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
187 u32 m = (val >> 5) & 0x3f;
188 u32 od = (val >> 4) & 0x1;
189 u32 n = val & 0xf;
190
191 mult = (2 - od) * (m + 2);
192 div = n + 1;
193 }
194 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
195 mult, div);
196 };
197
198 static u32 get_bit(u8 idx)
199 {
200 return BIT(idx % 32);
201 }
202
203 static u32 get_reset_reg(struct aspeed_clk_gate *gate)
204 {
205 if (gate->reset_idx < 32)
206 return ASPEED_G6_RESET_CTRL;
207
208 return ASPEED_G6_RESET_CTRL2;
209 }
210
211 static u32 get_clock_reg(struct aspeed_clk_gate *gate)
212 {
213 if (gate->clock_idx < 32)
214 return ASPEED_G6_CLK_STOP_CTRL;
215
216 return ASPEED_G6_CLK_STOP_CTRL2;
217 }
218
219 static int aspeed_g6_clk_is_enabled(struct clk_hw *hw)
220 {
221 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
222 u32 clk = get_bit(gate->clock_idx);
223 u32 rst = get_bit(gate->reset_idx);
224 u32 reg;
225 u32 enval;
226
227 /*
228 * If the IP is in reset, treat the clock as not enabled,
229 * this happens with some clocks such as the USB one when
230 * coming from cold reset. Without this, aspeed_clk_enable()
231 * will fail to lift the reset.
232 */
233 if (gate->reset_idx >= 0) {
234 regmap_read(gate->map, get_reset_reg(gate), &reg);
235
236 if (reg & rst)
237 return 0;
238 }
239
240 regmap_read(gate->map, get_clock_reg(gate), &reg);
241
242 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
243
244 return ((reg & clk) == enval) ? 1 : 0;
245 }
246
247 static int aspeed_g6_clk_enable(struct clk_hw *hw)
248 {
249 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
250 unsigned long flags;
251 u32 clk = get_bit(gate->clock_idx);
252 u32 rst = get_bit(gate->reset_idx);
253
254 spin_lock_irqsave(gate->lock, flags);
255
256 if (aspeed_g6_clk_is_enabled(hw)) {
257 spin_unlock_irqrestore(gate->lock, flags);
258 return 0;
259 }
260
261 if (gate->reset_idx >= 0) {
262 /* Put IP in reset */
263 regmap_write(gate->map, get_reset_reg(gate), rst);
264 /* Delay 100us */
265 udelay(100);
266 }
267
268 /* Enable clock */
269 if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
270 /* Clock is clear to enable, so use set to clear register */
271 regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk);
272 } else {
273 /* Clock is set to enable, so use write to set register */
274 regmap_write(gate->map, get_clock_reg(gate), clk);
275 }
276
277 if (gate->reset_idx >= 0) {
278 /* A delay of 10ms is specified by the ASPEED docs */
279 mdelay(10);
280 /* Take IP out of reset */
281 regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst);
282 }
283
284 spin_unlock_irqrestore(gate->lock, flags);
285
286 return 0;
287 }
288
289 static void aspeed_g6_clk_disable(struct clk_hw *hw)
290 {
291 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
292 unsigned long flags;
293 u32 clk = get_bit(gate->clock_idx);
294
295 spin_lock_irqsave(gate->lock, flags);
296
297 if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
298 regmap_write(gate->map, get_clock_reg(gate), clk);
299 } else {
300 /* Use set to clear register */
301 regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk);
302 }
303
304 spin_unlock_irqrestore(gate->lock, flags);
305 }
306
307 static const struct clk_ops aspeed_g6_clk_gate_ops = {
308 .enable = aspeed_g6_clk_enable,
309 .disable = aspeed_g6_clk_disable,
310 .is_enabled = aspeed_g6_clk_is_enabled,
311 };
312
313 static int aspeed_g6_reset_deassert(struct reset_controller_dev *rcdev,
314 unsigned long id)
315 {
316 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
317 u32 rst = get_bit(id);
318 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
319
320 /* Use set to clear register */
321 return regmap_write(ar->map, reg + 0x04, rst);
322 }
323
324 static int aspeed_g6_reset_assert(struct reset_controller_dev *rcdev,
325 unsigned long id)
326 {
327 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
328 u32 rst = get_bit(id);
329 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
330
331 return regmap_write(ar->map, reg, rst);
332 }
333
334 static int aspeed_g6_reset_status(struct reset_controller_dev *rcdev,
335 unsigned long id)
336 {
337 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
338 int ret;
339 u32 val;
340 u32 rst = get_bit(id);
341 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
342
343 ret = regmap_read(ar->map, reg, &val);
344 if (ret)
345 return ret;
346
347 return !!(val & rst);
348 }
349
350 static const struct reset_control_ops aspeed_g6_reset_ops = {
351 .assert = aspeed_g6_reset_assert,
352 .deassert = aspeed_g6_reset_deassert,
353 .status = aspeed_g6_reset_status,
354 };
355
356 static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev,
357 const char *name, const char *parent_name, unsigned long flags,
358 struct regmap *map, u8 clock_idx, u8 reset_idx,
359 u8 clk_gate_flags, spinlock_t *lock)
360 {
361 struct aspeed_clk_gate *gate;
362 struct clk_init_data init;
363 struct clk_hw *hw;
364 int ret;
365
366 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
367 if (!gate)
368 return ERR_PTR(-ENOMEM);
369
370 init.name = name;
371 init.ops = &aspeed_g6_clk_gate_ops;
372 init.flags = flags;
373 init.parent_names = parent_name ? &parent_name : NULL;
374 init.num_parents = parent_name ? 1 : 0;
375
376 gate->map = map;
377 gate->clock_idx = clock_idx;
378 gate->reset_idx = reset_idx;
379 gate->flags = clk_gate_flags;
380 gate->lock = lock;
381 gate->hw.init = &init;
382
383 hw = &gate->hw;
384 ret = clk_hw_register(dev, hw);
385 if (ret) {
386 kfree(gate);
387 hw = ERR_PTR(ret);
388 }
389
390 return hw;
391 }
392
393 static const char * const vclk_parent_names[] = {
394 "dpll",
395 "d1pll",
396 "hclk",
397 "mclk",
398 };
399
400 static const char * const d1clk_parent_names[] = {
401 "dpll",
402 "epll",
403 "usb-phy-40m",
404 "gpioc6_clkin",
405 "dp_phy_pll",
406 };
407
408 static int aspeed_g6_clk_probe(struct platform_device *pdev)
409 {
410 struct device *dev = &pdev->dev;
411 struct aspeed_reset *ar;
412 struct regmap *map;
413 struct clk_hw *hw;
414 u32 val, rate;
415 int i, ret;
416
417 map = syscon_node_to_regmap(dev->of_node);
418 if (IS_ERR(map)) {
419 dev_err(dev, "no syscon regmap\n");
420 return PTR_ERR(map);
421 }
422
423 ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
424 if (!ar)
425 return -ENOMEM;
426
427 ar->map = map;
428
429 ar->rcdev.owner = THIS_MODULE;
430 ar->rcdev.nr_resets = 64;
431 ar->rcdev.ops = &aspeed_g6_reset_ops;
432 ar->rcdev.of_node = dev->of_node;
433
434 ret = devm_reset_controller_register(dev, &ar->rcdev);
435 if (ret) {
436 dev_err(dev, "could not register reset controller\n");
437 return ret;
438 }
439
440 /* UART clock div13 setting */
441 regmap_read(map, ASPEED_G6_MISC_CTRL, &val);
442 if (val & UART_DIV13_EN)
443 rate = 24000000 / 13;
444 else
445 rate = 24000000;
446 hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
447 if (IS_ERR(hw))
448 return PTR_ERR(hw);
449 aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw;
450
451 /* UART6~13 clock div13 setting */
452 regmap_read(map, 0x80, &val);
453 if (val & BIT(31))
454 rate = 24000000 / 13;
455 else
456 rate = 24000000;
457 hw = clk_hw_register_fixed_rate(dev, "uartx", NULL, 0, rate);
458 if (IS_ERR(hw))
459 return PTR_ERR(hw);
460 aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
461
462 /* EMMC ext clock divider */
463 hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "hpll", 0,
464 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 15, 0,
465 &aspeed_g6_clk_lock);
466 if (IS_ERR(hw))
467 return PTR_ERR(hw);
468 hw = clk_hw_register_divider_table(dev, "emmc_extclk", "emmc_extclk_gate", 0,
469 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 12, 3, 0,
470 ast2600_div_table,
471 &aspeed_g6_clk_lock);
472 if (IS_ERR(hw))
473 return PTR_ERR(hw);
474 aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;
475
476 /* SD/SDIO clock divider and gate */
477 hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
478 scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0,
479 &aspeed_g6_clk_lock);
480 if (IS_ERR(hw))
481 return PTR_ERR(hw);
482 hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
483 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0,
484 ast2600_div_table,
485 &aspeed_g6_clk_lock);
486 if (IS_ERR(hw))
487 return PTR_ERR(hw);
488 aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
489
490 /* MAC1/2 RMII 50MHz RCLK */
491 hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, 50000000);
492 if (IS_ERR(hw))
493 return PTR_ERR(hw);
494
495 /* MAC1/2 AHB bus clock divider */
496 hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,
497 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
498 ast2600_mac_div_table,
499 &aspeed_g6_clk_lock);
500 if (IS_ERR(hw))
501 return PTR_ERR(hw);
502 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
503
504 /* RMII1 50MHz (RCLK) output enable */
505 hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
506 scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0,
507 &aspeed_g6_clk_lock);
508 if (IS_ERR(hw))
509 return PTR_ERR(hw);
510 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw;
511
512 /* RMII2 50MHz (RCLK) output enable */
513 hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
514 scu_g6_base + ASPEED_MAC12_CLK_DLY, 30, 0,
515 &aspeed_g6_clk_lock);
516 if (IS_ERR(hw))
517 return PTR_ERR(hw);
518 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw;
519
520 /* MAC1/2 RMII 50MHz RCLK */
521 hw = clk_hw_register_fixed_rate(dev, "mac34rclk", "hclk", 0, 50000000);
522 if (IS_ERR(hw))
523 return PTR_ERR(hw);
524
525 /* MAC3/4 AHB bus clock divider */
526 hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,
527 scu_g6_base + 0x310, 24, 3, 0,
528 ast2600_mac_div_table,
529 &aspeed_g6_clk_lock);
530 if (IS_ERR(hw))
531 return PTR_ERR(hw);
532 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
533
534 /* RMII3 50MHz (RCLK) output enable */
535 hw = clk_hw_register_gate(dev, "mac3rclk", "mac34rclk", 0,
536 scu_g6_base + ASPEED_MAC34_CLK_DLY, 29, 0,
537 &aspeed_g6_clk_lock);
538 if (IS_ERR(hw))
539 return PTR_ERR(hw);
540 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC3RCLK] = hw;
541
542 /* RMII4 50MHz (RCLK) output enable */
543 hw = clk_hw_register_gate(dev, "mac4rclk", "mac34rclk", 0,
544 scu_g6_base + ASPEED_MAC34_CLK_DLY, 30, 0,
545 &aspeed_g6_clk_lock);
546 if (IS_ERR(hw))
547 return PTR_ERR(hw);
548 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC4RCLK] = hw;
549
550 /* LPC Host (LHCLK) clock divider */
551 hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
552 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
553 ast2600_div_table,
554 &aspeed_g6_clk_lock);
555 if (IS_ERR(hw))
556 return PTR_ERR(hw);
557 aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
558
559 /* gfx d1clk : use dp clk */
560 regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10));
561 /* SoC Display clock selection */
562 hw = clk_hw_register_mux(dev, "d1clk", d1clk_parent_names,
563 ARRAY_SIZE(d1clk_parent_names), 0,
564 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 8, 3, 0,
565 &aspeed_g6_clk_lock);
566 if (IS_ERR(hw))
567 return PTR_ERR(hw);
568 aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw;
569
570 /* d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1 */
571 regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */
572
573 /* P-Bus (BCLK) clock divider */
574 hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
575 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
576 ast2600_div_table,
577 &aspeed_g6_clk_lock);
578 if (IS_ERR(hw))
579 return PTR_ERR(hw);
580 aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw;
581
582 /* Video Capture clock selection */
583 hw = clk_hw_register_mux(dev, "vclk", vclk_parent_names,
584 ARRAY_SIZE(vclk_parent_names), 0,
585 scu_g6_base + ASPEED_G6_CLK_SELECTION2, 12, 3, 0,
586 &aspeed_g6_clk_lock);
587 if (IS_ERR(hw))
588 return PTR_ERR(hw);
589 aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw;
590
591 /* Video Engine clock divider */
592 hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0,
593 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 28, 3, 0,
594 ast2600_eclk_div_table,
595 &aspeed_g6_clk_lock);
596 if (IS_ERR(hw))
597 return PTR_ERR(hw);
598 aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw;
599
600 for (i = 0; i < ARRAY_SIZE(aspeed_g6_gates); i++) {
601 const struct aspeed_gate_data *gd = &aspeed_g6_gates[i];
602 u32 gate_flags;
603
604 /*
605 * Special case: the USB port 1 clock (bit 14) is always
606 * working the opposite way from the other ones.
607 */
608 gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
609 hw = aspeed_g6_clk_hw_register_gate(dev,
610 gd->name,
611 gd->parent_name,
612 gd->flags,
613 map,
614 gd->clock_idx,
615 gd->reset_idx,
616 gate_flags,
617 &aspeed_g6_clk_lock);
618 if (IS_ERR(hw))
619 return PTR_ERR(hw);
620 aspeed_g6_clk_data->hws[i] = hw;
621 }
622
623 return 0;
624 };
625
626 static const struct of_device_id aspeed_g6_clk_dt_ids[] = {
627 { .compatible = "aspeed,ast2600-scu" },
628 { }
629 };
630
631 static struct platform_driver aspeed_g6_clk_driver = {
632 .probe = aspeed_g6_clk_probe,
633 .driver = {
634 .name = "ast2600-clk",
635 .of_match_table = aspeed_g6_clk_dt_ids,
636 .suppress_bind_attrs = true,
637 },
638 };
639 builtin_platform_driver(aspeed_g6_clk_driver);
640
641 static const u32 ast2600_a0_axi_ahb_div_table[] = {
642 2, 2, 3, 5,
643 };
644
645 static const u32 ast2600_a1_axi_ahb_div_table[] = {
646 4, 6, 2, 4,
647 };
648
649 static void __init aspeed_g6_cc(struct regmap *map)
650 {
651 struct clk_hw *hw;
652 u32 val, div, chip_id, axi_div, ahb_div;
653
654 clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
655
656 /*
657 * High-speed PLL clock derived from the crystal. This the CPU clock,
658 * and we assume that it is enabled
659 */
660 regmap_read(map, ASPEED_HPLL_PARAM, &val);
661 aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val);
662
663 regmap_read(map, ASPEED_MPLL_PARAM, &val);
664 aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val);
665
666 regmap_read(map, ASPEED_DPLL_PARAM, &val);
667 aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val);
668
669 regmap_read(map, ASPEED_EPLL_PARAM, &val);
670 aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val);
671
672 regmap_read(map, ASPEED_APLL_PARAM, &val);
673 aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val);
674
675 /* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/
676 regmap_read(map, ASPEED_G6_STRAP1, &val);
677 if (val & BIT(16))
678 axi_div = 1;
679 else
680 axi_div = 2;
681
682 regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
683 if (chip_id & BIT(16))
684 ahb_div = ast2600_a1_axi_ahb_div_table[(val >> 11) & 0x3];
685 else
686 ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
687
688 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
689 aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;
690
691 regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val);
692 val = (val >> 23) & 0x7;
693 div = 4 * (val + 1);
694 hw = clk_hw_register_fixed_factor(NULL, "apb1", "hpll", 0, 1, div);
695 aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw;
696
697 regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val);
698 val = (val >> 9) & 0x7;
699 div = 2 * (val + 1);
700 hw = clk_hw_register_fixed_factor(NULL, "apb2", "ahb", 0, 1, div);
701 aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw;
702
703 /* USB 2.0 port1 phy 40MHz clock */
704 hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000);
705 aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw;
706 };
707
708 static void __init aspeed_g6_cc_init(struct device_node *np)
709 {
710 struct regmap *map;
711 int ret;
712 int i;
713
714 scu_g6_base = of_iomap(np, 0);
715 if (!scu_g6_base)
716 return;
717
718 aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws,
719 ASPEED_G6_NUM_CLKS), GFP_KERNEL);
720 if (!aspeed_g6_clk_data)
721 return;
722
723 /*
724 * This way all clocks fetched before the platform device probes,
725 * except those we assign here for early use, will be deferred.
726 */
727 for (i = 0; i < ASPEED_G6_NUM_CLKS; i++)
728 aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
729
730 /*
731 * We check that the regmap works on this very first access,
732 * but as this is an MMIO-backed regmap, subsequent regmap
733 * access is not going to fail and we skip error checks from
734 * this point.
735 */
736 map = syscon_node_to_regmap(np);
737 if (IS_ERR(map)) {
738 pr_err("no syscon regmap\n");
739 return;
740 }
741
742 aspeed_g6_cc(map);
743 aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
744 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
745 if (ret)
746 pr_err("failed to add DT provider: %d\n", ret);
747 };
748 CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init);
Linux with added FPC-III support