drivers/clk/qcom/dispcc-sc7180.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/module.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/regmap.h>
  10
  11 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
  12
  13 #include "clk-alpha-pll.h"
  14 #include "clk-branch.h"
  15 #include "clk-rcg.h"
  16 #include "clk-regmap-divider.h"
  17 #include "common.h"
  18 #include "gdsc.h"
  19
  20 enum {
  21         P_BI_TCXO,
  22         P_CHIP_SLEEP_CLK,
  23         P_CORE_BI_PLL_TEST_SE,
  24         P_DISP_CC_PLL0_OUT_EVEN,
  25         P_DISP_CC_PLL0_OUT_MAIN,
  26         P_DP_PHY_PLL_LINK_CLK,
  27         P_DP_PHY_PLL_VCO_DIV_CLK,
  28         P_DSI0_PHY_PLL_OUT_BYTECLK,
  29         P_DSI0_PHY_PLL_OUT_DSICLK,
  30         P_GPLL0_OUT_MAIN,
  31 };
  32
  33 static const struct pll_vco fabia_vco[] = {
  34         { 249600000, 2000000000, 0 },
  35 };
  36
  37 static struct clk_alpha_pll disp_cc_pll0 = {
  38         .offset = 0x0,
  39         .vco_table = fabia_vco,
  40         .num_vco = ARRAY_SIZE(fabia_vco),
  41         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  42         .clkr = {
  43                 .hw.init = &(struct clk_init_data){
  44                         .name = "disp_cc_pll0",
  45                         .parent_data = &(const struct clk_parent_data){
  46                                 .fw_name = "bi_tcxo",
  47                         },
  48                         .num_parents = 1,
  49                         .ops = &clk_alpha_pll_fabia_ops,
  50                 },
  51         },
  52 };
  53
  54 static const struct clk_div_table post_div_table_disp_cc_pll0_out_even[] = {
  55         { 0x0, 1 },
  56         { }
  57 };
  58
  59 static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = {
  60         .offset = 0x0,
  61         .post_div_shift = 8,
  62         .post_div_table = post_div_table_disp_cc_pll0_out_even,
  63         .num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll0_out_even),
  64         .width = 4,
  65         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  66         .clkr.hw.init = &(struct clk_init_data){
  67                 .name = "disp_cc_pll0_out_even",
  68                 .parent_data = &(const struct clk_parent_data){
  69                         .hw = &disp_cc_pll0.clkr.hw,
  70                 },
  71                 .num_parents = 1,
  72                 .flags = CLK_SET_RATE_PARENT,
  73                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
  74         },
  75 };
  76
  77 static const struct parent_map disp_cc_parent_map_0[] = {
  78         { P_BI_TCXO, 0 },
  79 };
  80
  81 static const struct clk_parent_data disp_cc_parent_data_0[] = {
  82         { .fw_name = "bi_tcxo" },
  83 };
  84
  85 static const struct parent_map disp_cc_parent_map_1[] = {
  86         { P_BI_TCXO, 0 },
  87         { P_DP_PHY_PLL_LINK_CLK, 1 },
  88         { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
  89 };
  90
  91 static const struct clk_parent_data disp_cc_parent_data_1[] = {
  92         { .fw_name = "bi_tcxo" },
  93         { .fw_name = "dp_phy_pll_link_clk" },
  94         { .fw_name = "dp_phy_pll_vco_div_clk" },
  95 };
  96
  97 static const struct parent_map disp_cc_parent_map_2[] = {
  98         { P_BI_TCXO, 0 },
  99         { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
 100 };
 101
 102 static const struct clk_parent_data disp_cc_parent_data_2[] = {
 103         { .fw_name = "bi_tcxo" },
 104         { .fw_name = "dsi0_phy_pll_out_byteclk" },
 105 };
 106
 107 static const struct parent_map disp_cc_parent_map_3[] = {
 108         { P_BI_TCXO, 0 },
 109         { P_DISP_CC_PLL0_OUT_MAIN, 1 },
 110         { P_GPLL0_OUT_MAIN, 4 },
 111         { P_DISP_CC_PLL0_OUT_EVEN, 5 },
 112 };
 113
 114 static const struct clk_parent_data disp_cc_parent_data_3[] = {
 115         { .fw_name = "bi_tcxo" },
 116         { .hw = &disp_cc_pll0.clkr.hw },
 117         { .fw_name = "gcc_disp_gpll0_clk_src" },
 118         { .hw = &disp_cc_pll0_out_even.clkr.hw },
 119 };
 120
 121 static const struct parent_map disp_cc_parent_map_4[] = {
 122         { P_BI_TCXO, 0 },
 123         { P_GPLL0_OUT_MAIN, 4 },
 124 };
 125
 126 static const struct clk_parent_data disp_cc_parent_data_4[] = {
 127         { .fw_name = "bi_tcxo" },
 128         { .fw_name = "gcc_disp_gpll0_clk_src" },
 129 };
 130
 131 static const struct parent_map disp_cc_parent_map_5[] = {
 132         { P_BI_TCXO, 0 },
 133         { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
 134 };
 135
 136 static const struct clk_parent_data disp_cc_parent_data_5[] = {
 137         { .fw_name = "bi_tcxo" },
 138         { .fw_name = "dsi0_phy_pll_out_dsiclk" },
 139 };
 140
 141 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
 142         F(19200000, P_BI_TCXO, 1, 0, 0),
 143         F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 144         F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 145         { }
 146 };
 147
 148 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
 149         .cmd_rcgr = 0x22bc,
 150         .mnd_width = 0,
 151         .hid_width = 5,
 152         .parent_map = disp_cc_parent_map_4,
 153         .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
 154         .clkr.hw.init = &(struct clk_init_data){
 155                 .name = "disp_cc_mdss_ahb_clk_src",
 156                 .parent_data = disp_cc_parent_data_4,
 157                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
 158                 .flags = CLK_SET_RATE_PARENT,
 159                 .ops = &clk_rcg2_shared_ops,
 160         },
 161 };
 162
 163 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
 164         .cmd_rcgr = 0x2110,
 165         .mnd_width = 0,
 166         .hid_width = 5,
 167         .parent_map = disp_cc_parent_map_2,
 168         .clkr.hw.init = &(struct clk_init_data){
 169                 .name = "disp_cc_mdss_byte0_clk_src",
 170                 .parent_data = disp_cc_parent_data_2,
 171                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 172                 .flags = CLK_SET_RATE_PARENT,
 173                 .ops = &clk_byte2_ops,
 174         },
 175 };
 176
 177 static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
 178         F(19200000, P_BI_TCXO, 1, 0, 0),
 179         { }
 180 };
 181
 182 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
 183         .cmd_rcgr = 0x21dc,
 184         .mnd_width = 0,
 185         .hid_width = 5,
 186         .parent_map = disp_cc_parent_map_0,
 187         .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
 188         .clkr.hw.init = &(struct clk_init_data){
 189                 .name = "disp_cc_mdss_dp_aux_clk_src",
 190                 .parent_data = disp_cc_parent_data_0,
 191                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 192                 .ops = &clk_rcg2_ops,
 193         },
 194 };
 195
 196 static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
 197         .cmd_rcgr = 0x2194,
 198         .mnd_width = 0,
 199         .hid_width = 5,
 200         .parent_map = disp_cc_parent_map_1,
 201         .clkr.hw.init = &(struct clk_init_data){
 202                 .name = "disp_cc_mdss_dp_crypto_clk_src",
 203                 .parent_data = disp_cc_parent_data_1,
 204                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 205                 .flags = CLK_SET_RATE_PARENT,
 206                 .ops = &clk_byte2_ops,
 207         },
 208 };
 209
 210 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
 211         .cmd_rcgr = 0x2178,
 212         .mnd_width = 0,
 213         .hid_width = 5,
 214         .parent_map = disp_cc_parent_map_1,
 215         .clkr.hw.init = &(struct clk_init_data){
 216                 .name = "disp_cc_mdss_dp_link_clk_src",
 217                 .parent_data = disp_cc_parent_data_1,
 218                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 219                 .flags = CLK_SET_RATE_PARENT,
 220                 .ops = &clk_byte2_ops,
 221         },
 222 };
 223
 224 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
 225         .cmd_rcgr = 0x21ac,
 226         .mnd_width = 16,
 227         .hid_width = 5,
 228         .parent_map = disp_cc_parent_map_1,
 229         .clkr.hw.init = &(struct clk_init_data){
 230                 .name = "disp_cc_mdss_dp_pixel_clk_src",
 231                 .parent_data = disp_cc_parent_data_1,
 232                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 233                 .flags = CLK_SET_RATE_PARENT,
 234                 .ops = &clk_dp_ops,
 235         },
 236 };
 237
 238 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
 239         .cmd_rcgr = 0x2148,
 240         .mnd_width = 0,
 241         .hid_width = 5,
 242         .parent_map = disp_cc_parent_map_2,
 243         .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
 244         .clkr.hw.init = &(struct clk_init_data){
 245                 .name = "disp_cc_mdss_esc0_clk_src",
 246                 .parent_data = disp_cc_parent_data_2,
 247                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 248                 .ops = &clk_rcg2_ops,
 249         },
 250 };
 251
 252 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
 253         F(19200000, P_BI_TCXO, 1, 0, 0),
 254         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 255         F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 256         F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
 257         F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 258         { }
 259 };
 260
 261 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
 262         .cmd_rcgr = 0x20c8,
 263         .mnd_width = 0,
 264         .hid_width = 5,
 265         .parent_map = disp_cc_parent_map_3,
 266         .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
 267         .clkr.hw.init = &(struct clk_init_data){
 268                 .name = "disp_cc_mdss_mdp_clk_src",
 269                 .parent_data = disp_cc_parent_data_3,
 270                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
 271                 .ops = &clk_rcg2_shared_ops,
 272         },
 273 };
 274
 275 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
 276         .cmd_rcgr = 0x2098,
 277         .mnd_width = 8,
 278         .hid_width = 5,
 279         .parent_map = disp_cc_parent_map_5,
 280         .clkr.hw.init = &(struct clk_init_data){
 281                 .name = "disp_cc_mdss_pclk0_clk_src",
 282                 .parent_data = disp_cc_parent_data_5,
 283                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
 284                 .flags = CLK_SET_RATE_PARENT,
 285                 .ops = &clk_pixel_ops,
 286         },
 287 };
 288
 289 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
 290         .cmd_rcgr = 0x20e0,
 291         .mnd_width = 0,
 292         .hid_width = 5,
 293         .parent_map = disp_cc_parent_map_3,
 294         .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
 295         .clkr.hw.init = &(struct clk_init_data){
 296                 .name = "disp_cc_mdss_rot_clk_src",
 297                 .parent_data = disp_cc_parent_data_3,
 298                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
 299                 .ops = &clk_rcg2_shared_ops,
 300         },
 301 };
 302
 303 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
 304         .cmd_rcgr = 0x20f8,
 305         .mnd_width = 0,
 306         .hid_width = 5,
 307         .parent_map = disp_cc_parent_map_0,
 308         .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
 309         .clkr.hw.init = &(struct clk_init_data){
 310                 .name = "disp_cc_mdss_vsync_clk_src",
 311                 .parent_data = disp_cc_parent_data_0,
 312                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 313                 .ops = &clk_rcg2_shared_ops,
 314         },
 315 };
 316
 317 static struct clk_branch disp_cc_mdss_ahb_clk = {
 318         .halt_reg = 0x2080,
 319         .halt_check = BRANCH_HALT,
 320         .clkr = {
 321                 .enable_reg = 0x2080,
 322                 .enable_mask = BIT(0),
 323                 .hw.init = &(struct clk_init_data){
 324                         .name = "disp_cc_mdss_ahb_clk",
 325                         .parent_data = &(const struct clk_parent_data){
 326                                 .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
 327                         },
 328                         .num_parents = 1,
 329                         .flags = CLK_SET_RATE_PARENT,
 330                         .ops = &clk_branch2_ops,
 331                 },
 332         },
 333 };
 334
 335 static struct clk_branch disp_cc_mdss_byte0_clk = {
 336         .halt_reg = 0x2028,
 337         .halt_check = BRANCH_HALT,
 338         .clkr = {
 339                 .enable_reg = 0x2028,
 340                 .enable_mask = BIT(0),
 341                 .hw.init = &(struct clk_init_data){
 342                         .name = "disp_cc_mdss_byte0_clk",
 343                         .parent_data = &(const struct clk_parent_data){
 344                                 .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw,
 345                         },
 346                         .num_parents = 1,
 347                         .flags = CLK_SET_RATE_PARENT,
 348                         .ops = &clk_branch2_ops,
 349                 },
 350         },
 351 };
 352
 353 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
 354         .reg = 0x2128,
 355         .shift = 0,
 356         .width = 2,
 357         .clkr.hw.init = &(struct clk_init_data) {
 358                 .name = "disp_cc_mdss_byte0_div_clk_src",
 359                 .parent_data = &(const struct clk_parent_data){
 360                         .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw
 361                 },
 362                 .num_parents = 1,
 363                 .ops = &clk_regmap_div_ops,
 364         },
 365 };
 366
 367 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
 368         .reg = 0x2190,
 369         .shift = 0,
 370         .width = 2,
 371         .clkr.hw.init = &(struct clk_init_data) {
 372                 .name = "disp_cc_mdss_dp_link_div_clk_src",
 373                 .parent_data = &(const struct clk_parent_data){
 374                         .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw
 375                 },
 376                 .num_parents = 1,
 377                 .ops = &clk_regmap_div_ops,
 378         },
 379 };
 380
 381 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
 382         .halt_reg = 0x202c,
 383         .halt_check = BRANCH_HALT,
 384         .clkr = {
 385                 .enable_reg = 0x202c,
 386                 .enable_mask = BIT(0),
 387                 .hw.init = &(struct clk_init_data){
 388                         .name = "disp_cc_mdss_byte0_intf_clk",
 389                         .parent_data = &(const struct clk_parent_data){
 390                                 .hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
 391                         },
 392                         .num_parents = 1,
 393                         .flags = CLK_SET_RATE_PARENT,
 394                         .ops = &clk_branch2_ops,
 395                 },
 396         },
 397 };
 398
 399 static struct clk_branch disp_cc_mdss_dp_aux_clk = {
 400         .halt_reg = 0x2054,
 401         .halt_check = BRANCH_HALT,
 402         .clkr = {
 403                 .enable_reg = 0x2054,
 404                 .enable_mask = BIT(0),
 405                 .hw.init = &(struct clk_init_data){
 406                         .name = "disp_cc_mdss_dp_aux_clk",
 407                         .parent_data = &(const struct clk_parent_data){
 408                                 .hw = &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
 409                         },
 410                         .num_parents = 1,
 411                         .flags = CLK_SET_RATE_PARENT,
 412                         .ops = &clk_branch2_ops,
 413                 },
 414         },
 415 };
 416
 417 static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
 418         .halt_reg = 0x2048,
 419         .halt_check = BRANCH_HALT,
 420         .clkr = {
 421                 .enable_reg = 0x2048,
 422                 .enable_mask = BIT(0),
 423                 .hw.init = &(struct clk_init_data){
 424                         .name = "disp_cc_mdss_dp_crypto_clk",
 425                         .parent_data = &(const struct clk_parent_data){
 426                                 .hw = &disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
 427                         },
 428                         .num_parents = 1,
 429                         .flags = CLK_SET_RATE_PARENT,
 430                         .ops = &clk_branch2_ops,
 431                 },
 432         },
 433 };
 434
 435 static struct clk_branch disp_cc_mdss_dp_link_clk = {
 436         .halt_reg = 0x2040,
 437         .halt_check = BRANCH_HALT,
 438         .clkr = {
 439                 .enable_reg = 0x2040,
 440                 .enable_mask = BIT(0),
 441                 .hw.init = &(struct clk_init_data){
 442                         .name = "disp_cc_mdss_dp_link_clk",
 443                         .parent_data = &(const struct clk_parent_data){
 444                                 .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw,
 445                         },
 446                         .num_parents = 1,
 447                         .flags = CLK_SET_RATE_PARENT,
 448                         .ops = &clk_branch2_ops,
 449                 },
 450         },
 451 };
 452
 453 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
 454         .halt_reg = 0x2044,
 455         .halt_check = BRANCH_HALT,
 456         .clkr = {
 457                 .enable_reg = 0x2044,
 458                 .enable_mask = BIT(0),
 459                 .hw.init = &(struct clk_init_data){
 460                         .name = "disp_cc_mdss_dp_link_intf_clk",
 461                         .parent_data = &(const struct clk_parent_data){
 462                                 .hw = &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
 463                         },
 464                         .num_parents = 1,
 465                         .ops = &clk_branch2_ops,
 466                 },
 467         },
 468 };
 469
 470 static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
 471         .halt_reg = 0x204c,
 472         .halt_check = BRANCH_HALT,
 473         .clkr = {
 474                 .enable_reg = 0x204c,
 475                 .enable_mask = BIT(0),
 476                 .hw.init = &(struct clk_init_data){
 477                         .name = "disp_cc_mdss_dp_pixel_clk",
 478                         .parent_data = &(const struct clk_parent_data){
 479                                 .hw = &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
 480                         },
 481                         .num_parents = 1,
 482                         .flags = CLK_SET_RATE_PARENT,
 483                         .ops = &clk_branch2_ops,
 484                 },
 485         },
 486 };
 487
 488 static struct clk_branch disp_cc_mdss_esc0_clk = {
 489         .halt_reg = 0x2038,
 490         .halt_check = BRANCH_HALT,
 491         .clkr = {
 492                 .enable_reg = 0x2038,
 493                 .enable_mask = BIT(0),
 494                 .hw.init = &(struct clk_init_data){
 495                         .name = "disp_cc_mdss_esc0_clk",
 496                         .parent_data = &(const struct clk_parent_data){
 497                                 .hw = &disp_cc_mdss_esc0_clk_src.clkr.hw,
 498                         },
 499                         .num_parents = 1,
 500                         .flags = CLK_SET_RATE_PARENT,
 501                         .ops = &clk_branch2_ops,
 502                 },
 503         },
 504 };
 505
 506 static struct clk_branch disp_cc_mdss_mdp_clk = {
 507         .halt_reg = 0x200c,
 508         .halt_check = BRANCH_HALT,
 509         .clkr = {
 510                 .enable_reg = 0x200c,
 511                 .enable_mask = BIT(0),
 512                 .hw.init = &(struct clk_init_data){
 513                         .name = "disp_cc_mdss_mdp_clk",
 514                         .parent_data = &(const struct clk_parent_data){
 515                                 .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
 516                         },
 517                         .num_parents = 1,
 518                         .flags = CLK_SET_RATE_PARENT,
 519                         .ops = &clk_branch2_ops,
 520                 },
 521         },
 522 };
 523
 524 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
 525         .halt_reg = 0x201c,
 526         .halt_check = BRANCH_VOTED,
 527         .clkr = {
 528                 .enable_reg = 0x201c,
 529                 .enable_mask = BIT(0),
 530                 .hw.init = &(struct clk_init_data){
 531                         .name = "disp_cc_mdss_mdp_lut_clk",
 532                         .parent_data = &(const struct clk_parent_data){
 533                                 .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
 534                         },
 535                         .num_parents = 1,
 536                         .ops = &clk_branch2_ops,
 537                 },
 538         },
 539 };
 540
 541 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
 542         .halt_reg = 0x4004,
 543         .halt_check = BRANCH_VOTED,
 544         .clkr = {
 545                 .enable_reg = 0x4004,
 546                 .enable_mask = BIT(0),
 547                 .hw.init = &(struct clk_init_data){
 548                         .name = "disp_cc_mdss_non_gdsc_ahb_clk",
 549                         .parent_data = &(const struct clk_parent_data){
 550                                 .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
 551                         },
 552                         .num_parents = 1,
 553                         .flags = CLK_SET_RATE_PARENT,
 554                         .ops = &clk_branch2_ops,
 555                 },
 556         },
 557 };
 558
 559 static struct clk_branch disp_cc_mdss_pclk0_clk = {
 560         .halt_reg = 0x2004,
 561         .halt_check = BRANCH_HALT,
 562         .clkr = {
 563                 .enable_reg = 0x2004,
 564                 .enable_mask = BIT(0),
 565                 .hw.init = &(struct clk_init_data){
 566                         .name = "disp_cc_mdss_pclk0_clk",
 567                         .parent_data = &(const struct clk_parent_data){
 568                                 .hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw,
 569                         },
 570                         .num_parents = 1,
 571                         .flags = CLK_SET_RATE_PARENT,
 572                         .ops = &clk_branch2_ops,
 573                 },
 574         },
 575 };
 576
 577 static struct clk_branch disp_cc_mdss_rot_clk = {
 578         .halt_reg = 0x2014,
 579         .halt_check = BRANCH_HALT,
 580         .clkr = {
 581                 .enable_reg = 0x2014,
 582                 .enable_mask = BIT(0),
 583                 .hw.init = &(struct clk_init_data){
 584                         .name = "disp_cc_mdss_rot_clk",
 585                         .parent_data = &(const struct clk_parent_data){
 586                                 .hw = &disp_cc_mdss_rot_clk_src.clkr.hw,
 587                         },
 588                         .num_parents = 1,
 589                         .flags = CLK_SET_RATE_PARENT,
 590                         .ops = &clk_branch2_ops,
 591                 },
 592         },
 593 };
 594
 595 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
 596         .halt_reg = 0x4008,
 597         .halt_check = BRANCH_HALT,
 598         .clkr = {
 599                 .enable_reg = 0x4008,
 600                 .enable_mask = BIT(0),
 601                 .hw.init = &(struct clk_init_data){
 602                         .name = "disp_cc_mdss_rscc_vsync_clk",
 603                         .parent_data = &(const struct clk_parent_data){
 604                                 .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
 605                         },
 606                         .num_parents = 1,
 607                         .flags = CLK_SET_RATE_PARENT,
 608                         .ops = &clk_branch2_ops,
 609                 },
 610         },
 611 };
 612
 613 static struct clk_branch disp_cc_mdss_vsync_clk = {
 614         .halt_reg = 0x2024,
 615         .halt_check = BRANCH_HALT,
 616         .clkr = {
 617                 .enable_reg = 0x2024,
 618                 .enable_mask = BIT(0),
 619                 .hw.init = &(struct clk_init_data){
 620                         .name = "disp_cc_mdss_vsync_clk",
 621                         .parent_data = &(const struct clk_parent_data){
 622                                 .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
 623                         },
 624                         .num_parents = 1,
 625                         .flags = CLK_SET_RATE_PARENT,
 626                         .ops = &clk_branch2_ops,
 627                 },
 628         },
 629 };
 630
 631 static struct gdsc mdss_gdsc = {
 632         .gdscr = 0x3000,
 633         .pd = {
 634                 .name = "mdss_gdsc",
 635         },
 636         .pwrsts = PWRSTS_OFF_ON,
 637         .flags = HW_CTRL,
 638 };
 639
 640 static struct gdsc *disp_cc_sc7180_gdscs[] = {
 641         [MDSS_GDSC] = &mdss_gdsc,
 642 };
 643
 644 static struct clk_regmap *disp_cc_sc7180_clocks[] = {
 645         [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
 646         [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
 647         [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
 648         [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
 649         [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
 650         [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
 651         [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
 652         [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
 653         [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
 654         [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
 655         [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
 656         [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
 657         [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =
 658                                 &disp_cc_mdss_dp_link_div_clk_src.clkr,
 659         [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
 660         [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
 661         [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
 662         [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
 663         [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
 664         [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
 665         [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
 666         [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
 667         [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
 668         [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
 669         [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
 670         [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
 671         [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
 672         [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
 673         [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
 674         [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
 675         [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
 676         [DISP_CC_PLL0_OUT_EVEN] = &disp_cc_pll0_out_even.clkr,
 677 };
 678
 679 static const struct regmap_config disp_cc_sc7180_regmap_config = {
 680         .reg_bits = 32,
 681         .reg_stride = 4,
 682         .val_bits = 32,
 683         .max_register = 0x10000,
 684         .fast_io = true,
 685 };
 686
 687 static const struct qcom_cc_desc disp_cc_sc7180_desc = {
 688         .config = &disp_cc_sc7180_regmap_config,
 689         .clks = disp_cc_sc7180_clocks,
 690         .num_clks = ARRAY_SIZE(disp_cc_sc7180_clocks),
 691         .gdscs = disp_cc_sc7180_gdscs,
 692         .num_gdscs = ARRAY_SIZE(disp_cc_sc7180_gdscs),
 693 };
 694
 695 static const struct of_device_id disp_cc_sc7180_match_table[] = {
 696         { .compatible = "qcom,sc7180-dispcc" },
 697         { }
 698 };
 699 MODULE_DEVICE_TABLE(of, disp_cc_sc7180_match_table);
 700
 701 static int disp_cc_sc7180_probe(struct platform_device *pdev)
 702 {
 703         struct regmap *regmap;
 704         struct alpha_pll_config disp_cc_pll_config = {};
 705
 706         regmap = qcom_cc_map(pdev, &disp_cc_sc7180_desc);
 707         if (IS_ERR(regmap))
 708                 return PTR_ERR(regmap);
 709
 710         /* 1380MHz configuration */
 711         disp_cc_pll_config.l = 0x47;
 712         disp_cc_pll_config.alpha = 0xe000;
 713         disp_cc_pll_config.user_ctl_val = 0x00000001;
 714         disp_cc_pll_config.user_ctl_hi_val = 0x00004805;
 715
 716         clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll_config);
 717
 718         return qcom_cc_really_probe(pdev, &disp_cc_sc7180_desc, regmap);
 719 }
 720
 721 static struct platform_driver disp_cc_sc7180_driver = {
 722         .probe = disp_cc_sc7180_probe,
 723         .driver = {
 724                 .name = "sc7180-dispcc",
 725                 .of_match_table = disp_cc_sc7180_match_table,
 726         },
 727 };
 728
 729 static int __init disp_cc_sc7180_init(void)
 730 {
 731         return platform_driver_register(&disp_cc_sc7180_driver);
 732 }
 733 subsys_initcall(disp_cc_sc7180_init);
 734
 735 static void __exit disp_cc_sc7180_exit(void)
 736 {
 737         platform_driver_unregister(&disp_cc_sc7180_driver);
 738 }
 739 module_exit(disp_cc_sc7180_exit);
 740
 741 MODULE_DESCRIPTION("QTI DISP_CC SC7180 Driver");
 742 MODULE_LICENSE("GPL v2");