drivers/clk/ti/clk-7xx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * DRA7 Clock init
   4  *
   5  * Copyright (C) 2013 Texas Instruments, Inc.
   6  *
   7  * Tero Kristo (t-kristo@ti.com)
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/list.h>
  12 #include <linux/clk.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/clk/ti.h>
  15 #include <dt-bindings/clock/dra7.h>
  16
  17 #include "clock.h"
  18
  19 #define DRA7_DPLL_GMAC_DEFFREQ                          1000000000
  20 #define DRA7_DPLL_USB_DEFFREQ                           960000000
  21
  22 static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
  23         { DRA7_MPU_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
  24         { 0 },
  25 };
  26
  27 static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = {
  28         { DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },
  29         { 0 },
  30 };
  31
  32 static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = {
  33         "dpll_abe_m2x2_ck",
  34         "dpll_core_h22x2_ck",
  35         NULL,
  36 };
  37
  38 static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = {
  39         { 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
  40         { 0 },
  41 };
  42
  43 static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = {
  44         { DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP | CLKF_NO_IDLEST, "ipu1-clkctrl:0000:24" },
  45         { 0 },
  46 };
  47
  48 static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
  49         "per_abe_x1_gfclk2_div",
  50         "video1_clk2_div",
  51         "video2_clk2_div",
  52         "hdmi_clk2_div",
  53         NULL,
  54 };
  55
  56 static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
  57         "abe_24m_fclk",
  58         "abe_sys_clk_div",
  59         "func_24m_clk",
  60         "atl_clkin3_ck",
  61         "atl_clkin2_ck",
  62         "atl_clkin1_ck",
  63         "atl_clkin0_ck",
  64         "sys_clkin2",
  65         "ref_clkin0_ck",
  66         "ref_clkin1_ck",
  67         "ref_clkin2_ck",
  68         "ref_clkin3_ck",
  69         "mlb_clk",
  70         "mlbp_clk",
  71         NULL,
  72 };
  73
  74 static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
  75         { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
  76         { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
  77         { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
  78         { 0 },
  79 };
  80
  81 static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
  82         "timer_sys_clk_div",
  83         "sys_32k_ck",
  84         "sys_clkin2",
  85         "ref_clkin0_ck",
  86         "ref_clkin1_ck",
  87         "ref_clkin2_ck",
  88         "ref_clkin3_ck",
  89         "abe_giclk_div",
  90         "video1_div_clk",
  91         "video2_div_clk",
  92         "hdmi_div_clk",
  93         "clkoutmux0_clk_mux",
  94         NULL,
  95 };
  96
  97 static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
  98         { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
  99         { 0 },
 100 };
 101
 102 static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
 103         { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
 104         { 0 },
 105 };
 106
 107 static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
 108         { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
 109         { 0 },
 110 };
 111
 112 static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
 113         { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
 114         { 0 },
 115 };
 116
 117 static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
 118         "func_48m_fclk",
 119         "dpll_per_m2x2_ck",
 120         NULL,
 121 };
 122
 123 static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
 124         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 125         { 0 },
 126 };
 127
 128 static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
 129         { DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" },
 130         { DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" },
 131         { DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" },
 132         { DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" },
 133         { DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" },
 134         { DRA7_IPU_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 135         { DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" },
 136         { 0 },
 137 };
 138
 139 static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = {
 140         { DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },
 141         { 0 },
 142 };
 143
 144 static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
 145         { DRA7_RTC_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
 146         { 0 },
 147 };
 148
 149 static const char * const dra7_cam_gfclk_mux_parents[] __initconst = {
 150         "l3_iclk_div",
 151         "core_iss_main_clk",
 152         NULL,
 153 };
 154
 155 static const struct omap_clkctrl_bit_data dra7_cam_bit_data[] __initconst = {
 156         { 24, TI_CLK_MUX, dra7_cam_gfclk_mux_parents, NULL },
 157         { 0 },
 158 };
 159
 160 static const struct omap_clkctrl_reg_data dra7_cam_clkctrl_regs[] __initconst = {
 161         { DRA7_CAM_VIP1_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
 162         { DRA7_CAM_VIP2_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
 163         { DRA7_CAM_VIP3_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
 164         { 0 },
 165 };
 166
 167 static const struct omap_clkctrl_reg_data dra7_vpe_clkctrl_regs[] __initconst = {
 168         { DRA7_VPE_VPE_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h23x2_ck" },
 169         { 0 },
 170 };
 171
 172 static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
 173         { DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
 174         { DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
 175         { 0 },
 176 };
 177
 178 static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
 179         { DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
 180         { DRA7_L3MAIN1_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 181         { DRA7_L3MAIN1_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
 182         { DRA7_L3MAIN1_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 183         { DRA7_L3MAIN1_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 184         { DRA7_L3MAIN1_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
 185         { DRA7_L3MAIN1_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
 186         { 0 },
 187 };
 188
 189 static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = {
 190         { DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
 191         { 0 },
 192 };
 193
 194 static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
 195         { DRA7_DMA_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
 196         { 0 },
 197 };
 198
 199 static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
 200         { DRA7_EMIF_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
 201         { 0 },
 202 };
 203
 204 static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
 205         "sys_32k_ck",
 206         "video1_clkin_ck",
 207         "video2_clkin_ck",
 208         "hdmi_clkin_ck",
 209         NULL,
 210 };
 211
 212 static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
 213         "l3_iclk_div",
 214         "dpll_abe_m2_ck",
 215         "atl-clkctrl:0000:24",
 216         NULL,
 217 };
 218
 219 static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
 220         { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
 221         { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
 222         { 0 },
 223 };
 224
 225 static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
 226         { DRA7_ATL_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl-clkctrl:0000:26" },
 227         { 0 },
 228 };
 229
 230 static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
 231         { DRA7_L4CFG_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
 232         { DRA7_L4CFG_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
 233         { DRA7_L4CFG_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
 234         { DRA7_L4CFG_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
 235         { DRA7_L4CFG_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
 236         { DRA7_L4CFG_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
 237         { DRA7_L4CFG_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
 238         { DRA7_L4CFG_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
 239         { DRA7_L4CFG_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
 240         { DRA7_L4CFG_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
 241         { DRA7_L4CFG_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
 242         { DRA7_L4CFG_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
 243         { DRA7_L4CFG_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
 244         { DRA7_L4CFG_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
 245         { DRA7_L4CFG_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
 246         { 0 },
 247 };
 248
 249 static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
 250         { DRA7_L3INSTR_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 251         { DRA7_L3INSTR_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 252         { 0 },
 253 };
 254
 255 static const char * const dra7_dss_dss_clk_parents[] __initconst = {
 256         "dpll_per_h12x2_ck",
 257         NULL,
 258 };
 259
 260 static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
 261         "func_48m_fclk",
 262         NULL,
 263 };
 264
 265 static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
 266         "hdmi_dpll_clk_mux",
 267         NULL,
 268 };
 269
 270 static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
 271         "sys_32k_ck",
 272         NULL,
 273 };
 274
 275 static const char * const dra7_dss_video1_clk_parents[] __initconst = {
 276         "video1_dpll_clk_mux",
 277         NULL,
 278 };
 279
 280 static const char * const dra7_dss_video2_clk_parents[] __initconst = {
 281         "video2_dpll_clk_mux",
 282         NULL,
 283 };
 284
 285 static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
 286         { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
 287         { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
 288         { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
 289         { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 290         { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
 291         { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
 292         { 0 },
 293 };
 294
 295 static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
 296         { DRA7_DSS_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
 297         { DRA7_DSS_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
 298         { 0 },
 299 };
 300
 301 static const char * const dra7_gpu_core_mux_parents[] __initconst = {
 302         "dpll_core_h14x2_ck",
 303         "dpll_per_h14x2_ck",
 304         "dpll_gpu_m2_ck",
 305         NULL,
 306 };
 307
 308 static const char * const dra7_gpu_hyd_mux_parents[] __initconst = {
 309         "dpll_core_h14x2_ck",
 310         "dpll_per_h14x2_ck",
 311         "dpll_gpu_m2_ck",
 312         NULL,
 313 };
 314
 315 static const char * const dra7_gpu_sys_clk_parents[] __initconst = {
 316         "sys_clkin",
 317         NULL,
 318 };
 319
 320 static const struct omap_clkctrl_div_data dra7_gpu_sys_clk_data __initconst = {
 321         .max_div = 2,
 322 };
 323
 324 static const struct omap_clkctrl_bit_data dra7_gpu_core_bit_data[] __initconst = {
 325         { 24, TI_CLK_MUX, dra7_gpu_core_mux_parents, NULL, },
 326         { 26, TI_CLK_MUX, dra7_gpu_hyd_mux_parents, NULL, },
 327         { 0 },
 328 };
 329
 330 static const struct omap_clkctrl_reg_data dra7_gpu_clkctrl_regs[] __initconst = {
 331         { DRA7_GPU_CLKCTRL, dra7_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24", },
 332         { 0 },
 333 };
 334
 335 static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
 336         "func_128m_clk",
 337         "dpll_per_m2x2_ck",
 338         NULL,
 339 };
 340
 341 static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
 342         "l3init-clkctrl:0008:24",
 343         NULL,
 344 };
 345
 346 static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {
 347         .max_div = 4,
 348         .flags = CLK_DIVIDER_POWER_OF_TWO,
 349 };
 350
 351 static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
 352         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 353         { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
 354         { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data },
 355         { 0 },
 356 };
 357
 358 static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
 359         "l3init-clkctrl:0010:24",
 360         NULL,
 361 };
 362
 363 static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {
 364         .max_div = 4,
 365         .flags = CLK_DIVIDER_POWER_OF_TWO,
 366 };
 367
 368 static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
 369         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 370         { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
 371         { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data },
 372         { 0 },
 373 };
 374
 375 static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
 376         "l3init_960m_gfclk",
 377         NULL,
 378 };
 379
 380 static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
 381         { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
 382         { 0 },
 383 };
 384
 385 static const char * const dra7_sata_ref_clk_parents[] __initconst = {
 386         "sys_clkin1",
 387         NULL,
 388 };
 389
 390 static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
 391         { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
 392         { 0 },
 393 };
 394
 395 static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
 396         { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
 397         { 0 },
 398 };
 399
 400 static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
 401         { DRA7_L3INIT_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
 402         { DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
 403         { DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
 404         { DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
 405         { DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" },
 406         { DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
 407         { DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
 408         { DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
 409         { DRA7_L3INIT_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
 410         { 0 },
 411 };
 412
 413 static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
 414         "apll_pcie_ck",
 415         NULL,
 416 };
 417
 418 static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
 419         "optfclk_pciephy_div",
 420         NULL,
 421 };
 422
 423 static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
 424         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 425         { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
 426         { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
 427         { 0 },
 428 };
 429
 430 static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
 431         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 432         { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
 433         { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
 434         { 0 },
 435 };
 436
 437 static const struct omap_clkctrl_reg_data dra7_pcie_clkctrl_regs[] __initconst = {
 438         { DRA7_PCIE_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
 439         { DRA7_PCIE_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
 440         { 0 },
 441 };
 442
 443 static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
 444         "dpll_gmac_h11x2_ck",
 445         "rmii_clk_ck",
 446         NULL,
 447 };
 448
 449 static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
 450         "video1_clkin_ck",
 451         "video2_clkin_ck",
 452         "dpll_abe_m2_ck",
 453         "hdmi_clkin_ck",
 454         "l3_iclk_div",
 455         NULL,
 456 };
 457
 458 static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
 459         { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
 460         { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
 461         { 0 },
 462 };
 463
 464 static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = {
 465         { DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "gmac_main_clk" },
 466         { 0 },
 467 };
 468
 469 static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
 470         "timer_sys_clk_div",
 471         "sys_32k_ck",
 472         "sys_clkin2",
 473         "ref_clkin0_ck",
 474         "ref_clkin1_ck",
 475         "ref_clkin2_ck",
 476         "ref_clkin3_ck",
 477         "abe_giclk_div",
 478         "video1_div_clk",
 479         "video2_div_clk",
 480         "hdmi_div_clk",
 481         NULL,
 482 };
 483
 484 static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
 485         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 486         { 0 },
 487 };
 488
 489 static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
 490         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 491         { 0 },
 492 };
 493
 494 static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
 495         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 496         { 0 },
 497 };
 498
 499 static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
 500         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 501         { 0 },
 502 };
 503
 504 static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
 505         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 506         { 0 },
 507 };
 508
 509 static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
 510         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 511         { 0 },
 512 };
 513
 514 static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
 515         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 516         { 0 },
 517 };
 518
 519 static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
 520         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 521         { 0 },
 522 };
 523
 524 static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
 525         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 526         { 0 },
 527 };
 528
 529 static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
 530         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 531         { 0 },
 532 };
 533
 534 static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
 535         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 536         { 0 },
 537 };
 538
 539 static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
 540         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 541         { 0 },
 542 };
 543
 544 static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
 545         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 546         { 0 },
 547 };
 548
 549 static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
 550         "l4per-clkctrl:00f8:24",
 551         NULL,
 552 };
 553
 554 static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {
 555         .max_div = 4,
 556         .flags = CLK_DIVIDER_POWER_OF_TWO,
 557 };
 558
 559 static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
 560         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 561         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 562         { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data },
 563         { 0 },
 564 };
 565
 566 static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
 567         "l4per-clkctrl:0100:24",
 568         NULL,
 569 };
 570
 571 static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {
 572         .max_div = 4,
 573         .flags = CLK_DIVIDER_POWER_OF_TWO,
 574 };
 575
 576 static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
 577         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 578         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 579         { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },
 580         { 0 },
 581 };
 582
 583 static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
 584         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 585         { 0 },
 586 };
 587
 588 static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
 589         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 590         { 0 },
 591 };
 592
 593 static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
 594         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 595         { 0 },
 596 };
 597
 598 static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
 599         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 600         { 0 },
 601 };
 602
 603 static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
 604         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 605         { 0 },
 606 };
 607
 608 static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
 609         { DRA7_L4PER_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0000:24" },
 610         { DRA7_L4PER_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
 611         { DRA7_L4PER_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
 612         { DRA7_L4PER_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
 613         { DRA7_L4PER_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
 614         { DRA7_L4PER_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
 615         { DRA7_L4PER_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
 616         { DRA7_L4PER_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
 617         { DRA7_L4PER_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
 618         { DRA7_L4PER_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
 619         { DRA7_L4PER_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
 620         { DRA7_L4PER_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
 621         { DRA7_L4PER_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
 622         { DRA7_L4PER_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 623         { DRA7_L4PER_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 624         { DRA7_L4PER_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 625         { DRA7_L4PER_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
 626         { DRA7_L4PER_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
 627         { DRA7_L4PER_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 628         { DRA7_L4PER_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 629         { DRA7_L4PER_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 630         { DRA7_L4PER_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
 631         { DRA7_L4PER_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
 632         { DRA7_L4PER_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
 633         { DRA7_L4PER_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:00f8:25" },
 634         { DRA7_L4PER_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0100:25" },
 635         { DRA7_L4PER_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0118:24" },
 636         { DRA7_L4PER_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0120:24" },
 637         { DRA7_L4PER_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0128:24" },
 638         { DRA7_L4PER_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0130:24" },
 639         { DRA7_L4PER_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0148:24" },
 640         { 0 },
 641 };
 642
 643 static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst = {
 644         { DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 645         { DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 646         { DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 647         { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },
 648         { DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
 649         { 0 },
 650 };
 651
 652 static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
 653         "func_128m_clk",
 654         "dpll_per_h13x2_ck",
 655         NULL,
 656 };
 657
 658 static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
 659         "l4per2-clkctrl:012c:24",
 660         NULL,
 661 };
 662
 663 static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
 664         .max_div = 4,
 665         .flags = CLK_DIVIDER_POWER_OF_TWO,
 666 };
 667
 668 static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
 669         { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
 670         { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
 671         { 0 },
 672 };
 673
 674 static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
 675         { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
 676         { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
 677         { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
 678         { 0 },
 679 };
 680
 681 static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
 682         { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
 683         { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
 684         { 0 },
 685 };
 686
 687 static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
 688         { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
 689         { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
 690         { 0 },
 691 };
 692
 693 static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
 694         { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
 695         { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
 696         { 0 },
 697 };
 698
 699 static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
 700         { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
 701         { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
 702         { 0 },
 703 };
 704
 705 static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
 706         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 707         { 0 },
 708 };
 709
 710 static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
 711         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 712         { 0 },
 713 };
 714
 715 static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
 716         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 717         { 0 },
 718 };
 719
 720 static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
 721         { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
 722         { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
 723         { 0 },
 724 };
 725
 726 static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
 727         { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
 728         { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
 729         { 0 },
 730 };
 731
 732 static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst = {
 733         { DRA7_L4PER2_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div" },
 734         { DRA7_L4PER2_PRUSS1_CLKCTRL, NULL, CLKF_SW_SUP, "" },
 735         { DRA7_L4PER2_PRUSS2_CLKCTRL, NULL, CLKF_SW_SUP, "" },
 736         { DRA7_L4PER2_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
 737         { DRA7_L4PER2_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
 738         { DRA7_L4PER2_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
 739         { DRA7_L4PER2_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:012c:25" },
 740         { DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },
 741         { DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },
 742         { DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },
 743         { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:22" },
 744         { DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },
 745         { DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" },
 746         { DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" },
 747         { DRA7_L4PER2_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01dc:24" },
 748         { DRA7_L4PER2_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1" },
 749         { DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01f8:22" },
 750         { DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01fc:22" },
 751         { 0 },
 752 };
 753
 754 static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
 755         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 756         { 0 },
 757 };
 758
 759 static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
 760         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 761         { 0 },
 762 };
 763
 764 static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
 765         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 766         { 0 },
 767 };
 768
 769 static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
 770         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 771         { 0 },
 772 };
 773
 774 static const struct omap_clkctrl_reg_data dra7_l4per3_clkctrl_regs[] __initconst = {
 775         { DRA7_L4PER3_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div" },
 776         { DRA7_L4PER3_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00b4:24" },
 777         { DRA7_L4PER3_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00bc:24" },
 778         { DRA7_L4PER3_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00c4:24" },
 779         { DRA7_L4PER3_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:011c:24" },
 780         { 0 },
 781 };
 782
 783 static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
 784         { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
 785         { 0 },
 786 };
 787
 788 static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
 789         { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
 790         { 0 },
 791 };
 792
 793 static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
 794         { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
 795         { 0 },
 796 };
 797
 798 static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
 799         "sys_clkin1",
 800         "sys_clkin2",
 801         NULL,
 802 };
 803
 804 static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
 805         { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
 806         { 0 },
 807 };
 808
 809 static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
 810         { DRA7_WKUPAON_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
 811         { DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
 812         { DRA7_WKUPAON_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
 813         { DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
 814         { DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },
 815         { DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
 816         { DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" },
 817         { DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" },
 818         { DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk" },
 819         { 0 },
 820 };
 821
 822 const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
 823         { 0x4a005320, dra7_mpu_clkctrl_regs },
 824         { 0x4a005420, dra7_dsp1_clkctrl_regs },
 825         { 0x4a005520, dra7_ipu1_clkctrl_regs },
 826         { 0x4a005550, dra7_ipu_clkctrl_regs },
 827         { 0x4a005620, dra7_dsp2_clkctrl_regs },
 828         { 0x4a005720, dra7_rtc_clkctrl_regs },
 829         { 0x4a005760, dra7_vpe_clkctrl_regs },
 830         { 0x4a008620, dra7_coreaon_clkctrl_regs },
 831         { 0x4a008720, dra7_l3main1_clkctrl_regs },
 832         { 0x4a008920, dra7_ipu2_clkctrl_regs },
 833         { 0x4a008a20, dra7_dma_clkctrl_regs },
 834         { 0x4a008b20, dra7_emif_clkctrl_regs },
 835         { 0x4a008c00, dra7_atl_clkctrl_regs },
 836         { 0x4a008d20, dra7_l4cfg_clkctrl_regs },
 837         { 0x4a008e20, dra7_l3instr_clkctrl_regs },
 838         { 0x4a009020, dra7_cam_clkctrl_regs },
 839         { 0x4a009120, dra7_dss_clkctrl_regs },
 840         { 0x4a009220, dra7_gpu_clkctrl_regs },
 841         { 0x4a009320, dra7_l3init_clkctrl_regs },
 842         { 0x4a0093b0, dra7_pcie_clkctrl_regs },
 843         { 0x4a0093d0, dra7_gmac_clkctrl_regs },
 844         { 0x4a009728, dra7_l4per_clkctrl_regs },
 845         { 0x4a0098a0, dra7_l4sec_clkctrl_regs },
 846         { 0x4a00970c, dra7_l4per2_clkctrl_regs },
 847         { 0x4a009714, dra7_l4per3_clkctrl_regs },
 848         { 0x4ae07820, dra7_wkupaon_clkctrl_regs },
 849         { 0 },
 850 };
 851
 852 static struct ti_dt_clk dra7xx_clks[] = {
 853         DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
 854         DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
 855         DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
 856         DT_CLK(NULL, "atl_dpll_clk_mux", "atl-clkctrl:0000:24"),
 857         DT_CLK(NULL, "atl_gfclk_mux", "atl-clkctrl:0000:26"),
 858         DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon-clkctrl:0068:24"),
 859         DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
 860         DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
 861         DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
 862         DT_CLK(NULL, "dss_hdmi_clk", "dss-clkctrl:0000:10"),
 863         DT_CLK(NULL, "dss_video1_clk", "dss-clkctrl:0000:12"),
 864         DT_CLK(NULL, "dss_video2_clk", "dss-clkctrl:0000:13"),
 865         DT_CLK(NULL, "gmac_rft_clk_mux", "gmac-clkctrl:0000:25"),
 866         DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
 867         DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0038:8"),
 868         DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0040:8"),
 869         DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0048:8"),
 870         DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0050:8"),
 871         DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0058:8"),
 872         DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00e8:8"),
 873         DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f0:8"),
 874         DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1-clkctrl:0000:24"),
 875         DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu-clkctrl:0000:28"),
 876         DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu-clkctrl:0000:24"),
 877         DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu-clkctrl:0000:22"),
 878         DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per2-clkctrl:0154:28"),
 879         DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per2-clkctrl:0154:24"),
 880         DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per2-clkctrl:0154:22"),
 881         DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per2-clkctrl:015c:24"),
 882         DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per2-clkctrl:015c:22"),
 883         DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per2-clkctrl:018c:24"),
 884         DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per2-clkctrl:018c:22"),
 885         DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per2-clkctrl:016c:24"),
 886         DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per2-clkctrl:016c:22"),
 887         DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per2-clkctrl:01f8:24"),
 888         DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
 889         DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
 890         DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
 891         DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"),
 892         DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:22"),
 893         DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
 894         DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
 895         DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
 896         DT_CLK(NULL, "mmc2_clk32k", "l3init-clkctrl:0010:8"),
 897         DT_CLK(NULL, "mmc2_fclk_div", "l3init-clkctrl:0010:25"),
 898         DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
 899         DT_CLK(NULL, "mmc3_clk32k", "l4per-clkctrl:00f8:8"),
 900         DT_CLK(NULL, "mmc3_gfclk_div", "l4per-clkctrl:00f8:25"),
 901         DT_CLK(NULL, "mmc3_gfclk_mux", "l4per-clkctrl:00f8:24"),
 902         DT_CLK(NULL, "mmc4_clk32k", "l4per-clkctrl:0100:8"),
 903         DT_CLK(NULL, "mmc4_gfclk_div", "l4per-clkctrl:0100:25"),
 904         DT_CLK(NULL, "mmc4_gfclk_mux", "l4per-clkctrl:0100:24"),
 905         DT_CLK(NULL, "optfclk_pciephy1_32khz", "pcie-clkctrl:0000:8"),
 906         DT_CLK(NULL, "optfclk_pciephy1_clk", "pcie-clkctrl:0000:9"),
 907         DT_CLK(NULL, "optfclk_pciephy1_div_clk", "pcie-clkctrl:0000:10"),
 908         DT_CLK(NULL, "optfclk_pciephy2_32khz", "pcie-clkctrl:0008:8"),
 909         DT_CLK(NULL, "optfclk_pciephy2_clk", "pcie-clkctrl:0008:9"),
 910         DT_CLK(NULL, "optfclk_pciephy2_div_clk", "pcie-clkctrl:0008:10"),
 911         DT_CLK(NULL, "qspi_gfclk_div", "l4per2-clkctrl:012c:25"),
 912         DT_CLK(NULL, "qspi_gfclk_mux", "l4per2-clkctrl:012c:24"),
 913         DT_CLK(NULL, "rmii_50mhz_clk_mux", "gmac-clkctrl:0000:24"),
 914         DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
 915         DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0000:24"),
 916         DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0008:24"),
 917         DT_CLK(NULL, "timer13_gfclk_mux", "l4per3-clkctrl:00b4:24"),
 918         DT_CLK(NULL, "timer14_gfclk_mux", "l4per3-clkctrl:00bc:24"),
 919         DT_CLK(NULL, "timer15_gfclk_mux", "l4per3-clkctrl:00c4:24"),
 920         DT_CLK(NULL, "timer16_gfclk_mux", "l4per3-clkctrl:011c:24"),
 921         DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
 922         DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0010:24"),
 923         DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0018:24"),
 924         DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0020:24"),
 925         DT_CLK(NULL, "timer5_gfclk_mux", "ipu-clkctrl:0008:24"),
 926         DT_CLK(NULL, "timer6_gfclk_mux", "ipu-clkctrl:0010:24"),
 927         DT_CLK(NULL, "timer7_gfclk_mux", "ipu-clkctrl:0018:24"),
 928         DT_CLK(NULL, "timer8_gfclk_mux", "ipu-clkctrl:0020:24"),
 929         DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0028:24"),
 930         DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon-clkctrl:0060:24"),
 931         DT_CLK(NULL, "uart1_gfclk_mux", "l4per-clkctrl:0118:24"),
 932         DT_CLK(NULL, "uart2_gfclk_mux", "l4per-clkctrl:0120:24"),
 933         DT_CLK(NULL, "uart3_gfclk_mux", "l4per-clkctrl:0128:24"),
 934         DT_CLK(NULL, "uart4_gfclk_mux", "l4per-clkctrl:0130:24"),
 935         DT_CLK(NULL, "uart5_gfclk_mux", "l4per-clkctrl:0148:24"),
 936         DT_CLK(NULL, "uart6_gfclk_mux", "ipu-clkctrl:0030:24"),
 937         DT_CLK(NULL, "uart7_gfclk_mux", "l4per2-clkctrl:01c4:24"),
 938         DT_CLK(NULL, "uart8_gfclk_mux", "l4per2-clkctrl:01d4:24"),
 939         DT_CLK(NULL, "uart9_gfclk_mux", "l4per2-clkctrl:01dc:24"),
 940         DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init-clkctrl:00d0:8"),
 941         DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init-clkctrl:0020:8"),
 942         { .node_name = NULL },
 943 };
 944
 945 int __init dra7xx_dt_clk_init(void)
 946 {
 947         int rc;
 948         struct clk *dpll_ck, *hdcp_ck;
 949
 950         if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
 951                 ti_dt_clocks_register(dra7xx_compat_clks);
 952         else
 953                 ti_dt_clocks_register(dra7xx_clks);
 954
 955         omap2_clk_disable_autoidle_all();
 956
 957         ti_clk_add_aliases();
 958
 959         dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
 960         rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
 961         if (rc)
 962                 pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
 963
 964         dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
 965         rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
 966         if (rc)
 967                 pr_err("%s: failed to configure USB DPLL!\n", __func__);
 968
 969         dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
 970         rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
 971         if (rc)
 972                 pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
 973
 974         hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
 975         rc = clk_prepare_enable(hdcp_ck);
 976         if (rc)
 977                 pr_err("%s: failed to set dss_deshdcp_clk\n", __func__);
 978
 979         return rc;
 980 }