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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / crypto / inside-secure / safexcel.h
blob94016c505abb87e25cd5ddb765f64f3115237b89
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) 2017 Marvell
4 *
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
6 */
7
8 #ifndef __SAFEXCEL_H__
9 #define __SAFEXCEL_H__
10
11 #include <crypto/aead.h>
12 #include <crypto/algapi.h>
13 #include <crypto/internal/hash.h>
14 #include <crypto/sha.h>
15 #include <crypto/skcipher.h>
16
17 #define EIP197_HIA_VERSION_BE 0xca35
18 #define EIP197_HIA_VERSION_LE 0x35ca
19 #define EIP97_VERSION_LE 0x9e61
20 #define EIP196_VERSION_LE 0x3bc4
21 #define EIP197_VERSION_LE 0x3ac5
22 #define EIP96_VERSION_LE 0x9f60
23 #define EIP201_VERSION_LE 0x36c9
24 #define EIP206_VERSION_LE 0x31ce
25 #define EIP197_REG_LO16(reg) (reg & 0xffff)
26 #define EIP197_REG_HI16(reg) ((reg >> 16) & 0xffff)
27 #define EIP197_VERSION_MASK(reg) ((reg >> 16) & 0xfff)
28 #define EIP197_VERSION_SWAP(reg) (((reg & 0xf0) << 4) | \
29 ((reg >> 4) & 0xf0) | \
30 ((reg >> 12) & 0xf))
31
32 /* EIP197 HIA OPTIONS ENCODING */
33 #define EIP197_HIA_OPT_HAS_PE_ARB BIT(29)
34
35 /* EIP206 OPTIONS ENCODING */
36 #define EIP206_OPT_ICE_TYPE(n) ((n>>8)&3)
37
38 /* EIP197 OPTIONS ENCODING */
39 #define EIP197_OPT_HAS_TRC BIT(31)
40
41 /* Static configuration */
42 #define EIP197_DEFAULT_RING_SIZE 400
43 #define EIP197_EMB_TOKENS 4 /* Pad CD to 16 dwords */
44 #define EIP197_MAX_TOKENS 16
45 #define EIP197_MAX_RINGS 4
46 #define EIP197_FETCH_DEPTH 2
47 #define EIP197_MAX_BATCH_SZ 64
48 #define EIP197_MAX_RING_AIC 14
49
50 #define EIP197_GFP_FLAGS(base) ((base).flags & CRYPTO_TFM_REQ_MAY_SLEEP ? \
51 GFP_KERNEL : GFP_ATOMIC)
52
53 /* Custom on-stack requests (for invalidation) */
54 #define EIP197_SKCIPHER_REQ_SIZE sizeof(struct skcipher_request) + \
55 sizeof(struct safexcel_cipher_req)
56 #define EIP197_AHASH_REQ_SIZE sizeof(struct ahash_request) + \
57 sizeof(struct safexcel_ahash_req)
58 #define EIP197_AEAD_REQ_SIZE sizeof(struct aead_request) + \
59 sizeof(struct safexcel_cipher_req)
60 #define EIP197_REQUEST_ON_STACK(name, type, size) \
61 char __##name##_desc[size] CRYPTO_MINALIGN_ATTR; \
62 struct type##_request *name = (void *)__##name##_desc
63
64 /* Xilinx dev board base offsets */
65 #define EIP197_XLX_GPIO_BASE 0x200000
66 #define EIP197_XLX_IRQ_BLOCK_ID_ADDR 0x2000
67 #define EIP197_XLX_IRQ_BLOCK_ID_VALUE 0x1fc2
68 #define EIP197_XLX_USER_INT_ENB_MSK 0x2004
69 #define EIP197_XLX_USER_INT_ENB_SET 0x2008
70 #define EIP197_XLX_USER_INT_ENB_CLEAR 0x200c
71 #define EIP197_XLX_USER_INT_BLOCK 0x2040
72 #define EIP197_XLX_USER_INT_PEND 0x2048
73 #define EIP197_XLX_USER_VECT_LUT0_ADDR 0x2080
74 #define EIP197_XLX_USER_VECT_LUT0_IDENT 0x03020100
75 #define EIP197_XLX_USER_VECT_LUT1_ADDR 0x2084
76 #define EIP197_XLX_USER_VECT_LUT1_IDENT 0x07060504
77 #define EIP197_XLX_USER_VECT_LUT2_ADDR 0x2088
78 #define EIP197_XLX_USER_VECT_LUT2_IDENT 0x0b0a0908
79 #define EIP197_XLX_USER_VECT_LUT3_ADDR 0x208c
80 #define EIP197_XLX_USER_VECT_LUT3_IDENT 0x0f0e0d0c
81
82 /* Helper defines for probe function */
83 #define EIP197_IRQ_NUMBER(i, is_pci) (i + is_pci)
84
85 /* Register base offsets */
86 #define EIP197_HIA_AIC(priv) ((priv)->base + (priv)->offsets.hia_aic)
87 #define EIP197_HIA_AIC_G(priv) ((priv)->base + (priv)->offsets.hia_aic_g)
88 #define EIP197_HIA_AIC_R(priv) ((priv)->base + (priv)->offsets.hia_aic_r)
89 #define EIP197_HIA_AIC_xDR(priv) ((priv)->base + (priv)->offsets.hia_aic_xdr)
90 #define EIP197_HIA_DFE(priv) ((priv)->base + (priv)->offsets.hia_dfe)
91 #define EIP197_HIA_DFE_THR(priv) ((priv)->base + (priv)->offsets.hia_dfe_thr)
92 #define EIP197_HIA_DSE(priv) ((priv)->base + (priv)->offsets.hia_dse)
93 #define EIP197_HIA_DSE_THR(priv) ((priv)->base + (priv)->offsets.hia_dse_thr)
94 #define EIP197_HIA_GEN_CFG(priv) ((priv)->base + (priv)->offsets.hia_gen_cfg)
95 #define EIP197_PE(priv) ((priv)->base + (priv)->offsets.pe)
96 #define EIP197_GLOBAL(priv) ((priv)->base + (priv)->offsets.global)
97
98 /* EIP197 base offsets */
99 #define EIP197_HIA_AIC_BASE 0x90000
100 #define EIP197_HIA_AIC_G_BASE 0x90000
101 #define EIP197_HIA_AIC_R_BASE 0x90800
102 #define EIP197_HIA_AIC_xDR_BASE 0x80000
103 #define EIP197_HIA_DFE_BASE 0x8c000
104 #define EIP197_HIA_DFE_THR_BASE 0x8c040
105 #define EIP197_HIA_DSE_BASE 0x8d000
106 #define EIP197_HIA_DSE_THR_BASE 0x8d040
107 #define EIP197_HIA_GEN_CFG_BASE 0xf0000
108 #define EIP197_PE_BASE 0xa0000
109 #define EIP197_GLOBAL_BASE 0xf0000
110
111 /* EIP97 base offsets */
112 #define EIP97_HIA_AIC_BASE 0x0
113 #define EIP97_HIA_AIC_G_BASE 0x0
114 #define EIP97_HIA_AIC_R_BASE 0x0
115 #define EIP97_HIA_AIC_xDR_BASE 0x0
116 #define EIP97_HIA_DFE_BASE 0xf000
117 #define EIP97_HIA_DFE_THR_BASE 0xf200
118 #define EIP97_HIA_DSE_BASE 0xf400
119 #define EIP97_HIA_DSE_THR_BASE 0xf600
120 #define EIP97_HIA_GEN_CFG_BASE 0x10000
121 #define EIP97_PE_BASE 0x10000
122 #define EIP97_GLOBAL_BASE 0x10000
123
124 /* CDR/RDR register offsets */
125 #define EIP197_HIA_xDR_OFF(priv, r) (EIP197_HIA_AIC_xDR(priv) + (r) * 0x1000)
126 #define EIP197_HIA_CDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r))
127 #define EIP197_HIA_RDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r) + 0x800)
128 #define EIP197_HIA_xDR_RING_BASE_ADDR_LO 0x0000
129 #define EIP197_HIA_xDR_RING_BASE_ADDR_HI 0x0004
130 #define EIP197_HIA_xDR_RING_SIZE 0x0018
131 #define EIP197_HIA_xDR_DESC_SIZE 0x001c
132 #define EIP197_HIA_xDR_CFG 0x0020
133 #define EIP197_HIA_xDR_DMA_CFG 0x0024
134 #define EIP197_HIA_xDR_THRESH 0x0028
135 #define EIP197_HIA_xDR_PREP_COUNT 0x002c
136 #define EIP197_HIA_xDR_PROC_COUNT 0x0030
137 #define EIP197_HIA_xDR_PREP_PNTR 0x0034
138 #define EIP197_HIA_xDR_PROC_PNTR 0x0038
139 #define EIP197_HIA_xDR_STAT 0x003c
140
141 /* register offsets */
142 #define EIP197_HIA_DFE_CFG(n) (0x0000 + (128 * (n)))
143 #define EIP197_HIA_DFE_THR_CTRL(n) (0x0000 + (128 * (n)))
144 #define EIP197_HIA_DFE_THR_STAT(n) (0x0004 + (128 * (n)))
145 #define EIP197_HIA_DSE_CFG(n) (0x0000 + (128 * (n)))
146 #define EIP197_HIA_DSE_THR_CTRL(n) (0x0000 + (128 * (n)))
147 #define EIP197_HIA_DSE_THR_STAT(n) (0x0004 + (128 * (n)))
148 #define EIP197_HIA_RA_PE_CTRL(n) (0x0010 + (8 * (n)))
149 #define EIP197_HIA_RA_PE_STAT 0x0014
150 #define EIP197_HIA_AIC_R_OFF(r) ((r) * 0x1000)
151 #define EIP197_HIA_AIC_R_ENABLE_CTRL(r) (0xe008 - EIP197_HIA_AIC_R_OFF(r))
152 #define EIP197_HIA_AIC_R_ENABLED_STAT(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r))
153 #define EIP197_HIA_AIC_R_ACK(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r))
154 #define EIP197_HIA_AIC_R_ENABLE_CLR(r) (0xe014 - EIP197_HIA_AIC_R_OFF(r))
155 #define EIP197_HIA_AIC_R_VERSION(r) (0xe01c - EIP197_HIA_AIC_R_OFF(r))
156 #define EIP197_HIA_AIC_G_ENABLE_CTRL 0xf808
157 #define EIP197_HIA_AIC_G_ENABLED_STAT 0xf810
158 #define EIP197_HIA_AIC_G_ACK 0xf810
159 #define EIP197_HIA_MST_CTRL 0xfff4
160 #define EIP197_HIA_OPTIONS 0xfff8
161 #define EIP197_HIA_VERSION 0xfffc
162 #define EIP197_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n)))
163 #define EIP197_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n)))
164 #define EIP197_PE_ICE_SCRATCH_RAM(n) (0x0800 + (0x2000 * (n)))
165 #define EIP197_PE_ICE_PUE_CTRL(n) (0x0c80 + (0x2000 * (n)))
166 #define EIP197_PE_ICE_PUTF_CTRL(n) (0x0d00 + (0x2000 * (n)))
167 #define EIP197_PE_ICE_SCRATCH_CTRL(n) (0x0d04 + (0x2000 * (n)))
168 #define EIP197_PE_ICE_FPP_CTRL(n) (0x0d80 + (0x2000 * (n)))
169 #define EIP197_PE_ICE_PPTF_CTRL(n) (0x0e00 + (0x2000 * (n)))
170 #define EIP197_PE_ICE_RAM_CTRL(n) (0x0ff0 + (0x2000 * (n)))
171 #define EIP197_PE_EIP96_TOKEN_CTRL(n) (0x1000 + (0x2000 * (n)))
172 #define EIP197_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n)))
173 #define EIP197_PE_EIP96_CONTEXT_CTRL(n) (0x1008 + (0x2000 * (n)))
174 #define EIP197_PE_EIP96_CONTEXT_STAT(n) (0x100c + (0x2000 * (n)))
175 #define EIP197_PE_EIP96_TOKEN_CTRL2(n) (0x102c + (0x2000 * (n)))
176 #define EIP197_PE_EIP96_FUNCTION2_EN(n) (0x1030 + (0x2000 * (n)))
177 #define EIP197_PE_EIP96_OPTIONS(n) (0x13f8 + (0x2000 * (n)))
178 #define EIP197_PE_EIP96_VERSION(n) (0x13fc + (0x2000 * (n)))
179 #define EIP197_PE_OUT_DBUF_THRES(n) (0x1c00 + (0x2000 * (n)))
180 #define EIP197_PE_OUT_TBUF_THRES(n) (0x1d00 + (0x2000 * (n)))
181 #define EIP197_PE_OPTIONS(n) (0x1ff8 + (0x2000 * (n)))
182 #define EIP197_PE_VERSION(n) (0x1ffc + (0x2000 * (n)))
183 #define EIP197_MST_CTRL 0xfff4
184 #define EIP197_OPTIONS 0xfff8
185 #define EIP197_VERSION 0xfffc
186
187 /* EIP197-specific registers, no indirection */
188 #define EIP197_CLASSIFICATION_RAMS 0xe0000
189 #define EIP197_TRC_CTRL 0xf0800
190 #define EIP197_TRC_LASTRES 0xf0804
191 #define EIP197_TRC_REGINDEX 0xf0808
192 #define EIP197_TRC_PARAMS 0xf0820
193 #define EIP197_TRC_FREECHAIN 0xf0824
194 #define EIP197_TRC_PARAMS2 0xf0828
195 #define EIP197_TRC_ECCCTRL 0xf0830
196 #define EIP197_TRC_ECCSTAT 0xf0834
197 #define EIP197_TRC_ECCADMINSTAT 0xf0838
198 #define EIP197_TRC_ECCDATASTAT 0xf083c
199 #define EIP197_TRC_ECCDATA 0xf0840
200 #define EIP197_STRC_CONFIG 0xf43f0
201 #define EIP197_FLUE_CACHEBASE_LO(n) (0xf6000 + (32 * (n)))
202 #define EIP197_FLUE_CACHEBASE_HI(n) (0xf6004 + (32 * (n)))
203 #define EIP197_FLUE_CONFIG(n) (0xf6010 + (32 * (n)))
204 #define EIP197_FLUE_OFFSETS 0xf6808
205 #define EIP197_FLUE_ARC4_OFFSET 0xf680c
206 #define EIP197_FLUE_IFC_LUT(n) (0xf6820 + (4 * (n)))
207 #define EIP197_CS_RAM_CTRL 0xf7ff0
208
209 /* EIP197_HIA_xDR_DESC_SIZE */
210 #define EIP197_xDR_DESC_MODE_64BIT BIT(31)
211 #define EIP197_CDR_DESC_MODE_ADCP BIT(30)
212
213 /* EIP197_HIA_xDR_DMA_CFG */
214 #define EIP197_HIA_xDR_WR_RES_BUF BIT(22)
215 #define EIP197_HIA_xDR_WR_CTRL_BUF BIT(23)
216 #define EIP197_HIA_xDR_WR_OWN_BUF BIT(24)
217 #define EIP197_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 25)
218 #define EIP197_HIA_xDR_CFG_RD_CACHE(n) (((n) & 0x7) << 29)
219
220 /* EIP197_HIA_CDR_THRESH */
221 #define EIP197_HIA_CDR_THRESH_PROC_PKT(n) (n)
222 #define EIP197_HIA_CDR_THRESH_PROC_MODE BIT(22)
223 #define EIP197_HIA_CDR_THRESH_PKT_MODE BIT(23)
224 #define EIP197_HIA_CDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */
225
226 /* EIP197_HIA_RDR_THRESH */
227 #define EIP197_HIA_RDR_THRESH_PROC_PKT(n) (n)
228 #define EIP197_HIA_RDR_THRESH_PKT_MODE BIT(23)
229 #define EIP197_HIA_RDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */
230
231 /* EIP197_HIA_xDR_PREP_COUNT */
232 #define EIP197_xDR_PREP_CLR_COUNT BIT(31)
233
234 /* EIP197_HIA_xDR_PROC_COUNT */
235 #define EIP197_xDR_PROC_xD_PKT_OFFSET 24
236 #define EIP197_xDR_PROC_xD_PKT_MASK GENMASK(6, 0)
237 #define EIP197_xDR_PROC_xD_PKT(n) ((n) << 24)
238 #define EIP197_xDR_PROC_CLR_COUNT BIT(31)
239
240 /* EIP197_HIA_xDR_STAT */
241 #define EIP197_xDR_DMA_ERR BIT(0)
242 #define EIP197_xDR_PREP_CMD_THRES BIT(1)
243 #define EIP197_xDR_ERR BIT(2)
244 #define EIP197_xDR_THRESH BIT(4)
245 #define EIP197_xDR_TIMEOUT BIT(5)
246
247 #define EIP197_HIA_RA_PE_CTRL_RESET BIT(31)
248 #define EIP197_HIA_RA_PE_CTRL_EN BIT(30)
249
250 /* EIP197_HIA_OPTIONS */
251 #define EIP197_N_RINGS_OFFSET 0
252 #define EIP197_N_RINGS_MASK GENMASK(3, 0)
253 #define EIP197_N_PES_OFFSET 4
254 #define EIP197_N_PES_MASK GENMASK(4, 0)
255 #define EIP97_N_PES_MASK GENMASK(2, 0)
256 #define EIP197_HWDATAW_OFFSET 25
257 #define EIP197_HWDATAW_MASK GENMASK(3, 0)
258 #define EIP97_HWDATAW_MASK GENMASK(2, 0)
259 #define EIP197_CFSIZE_OFFSET 9
260 #define EIP197_CFSIZE_ADJUST 4
261 #define EIP97_CFSIZE_OFFSET 8
262 #define EIP197_CFSIZE_MASK GENMASK(2, 0)
263 #define EIP97_CFSIZE_MASK GENMASK(3, 0)
264 #define EIP197_RFSIZE_OFFSET 12
265 #define EIP197_RFSIZE_ADJUST 4
266 #define EIP97_RFSIZE_OFFSET 12
267 #define EIP197_RFSIZE_MASK GENMASK(2, 0)
268 #define EIP97_RFSIZE_MASK GENMASK(3, 0)
269
270 /* EIP197_HIA_AIC_R_ENABLE_CTRL */
271 #define EIP197_CDR_IRQ(n) BIT((n) * 2)
272 #define EIP197_RDR_IRQ(n) BIT((n) * 2 + 1)
273
274 /* EIP197_HIA_DFE/DSE_CFG */
275 #define EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(n) ((n) << 0)
276 #define EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(n) (((n) & 0x7) << 4)
277 #define EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(n) ((n) << 8)
278 #define EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE GENMASK(15, 14)
279 #define EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(n) ((n) << 16)
280 #define EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20)
281 #define EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(n) ((n) << 24)
282 #define EIP197_HIA_DFE_CFG_DIS_DEBUG GENMASK(31, 29)
283 #define EIP197_HIA_DSE_CFG_EN_SINGLE_WR BIT(29)
284 #define EIP197_HIA_DSE_CFG_DIS_DEBUG GENMASK(31, 30)
285
286 /* EIP197_HIA_DFE/DSE_THR_CTRL */
287 #define EIP197_DxE_THR_CTRL_EN BIT(30)
288 #define EIP197_DxE_THR_CTRL_RESET_PE BIT(31)
289
290 /* EIP197_PE_ICE_PUE/FPP_CTRL */
291 #define EIP197_PE_ICE_UENG_START_OFFSET(n) ((n) << 16)
292 #define EIP197_PE_ICE_UENG_INIT_ALIGN_MASK 0x7ff0
293 #define EIP197_PE_ICE_UENG_DEBUG_RESET BIT(3)
294
295 /* EIP197_HIA_AIC_G_ENABLED_STAT */
296 #define EIP197_G_IRQ_DFE(n) BIT((n) << 1)
297 #define EIP197_G_IRQ_DSE(n) BIT(((n) << 1) + 1)
298 #define EIP197_G_IRQ_RING BIT(16)
299 #define EIP197_G_IRQ_PE(n) BIT((n) + 20)
300
301 /* EIP197_HIA_MST_CTRL */
302 #define RD_CACHE_3BITS 0x5
303 #define WR_CACHE_3BITS 0x3
304 #define RD_CACHE_4BITS (RD_CACHE_3BITS << 1 | BIT(0))
305 #define WR_CACHE_4BITS (WR_CACHE_3BITS << 1 | BIT(0))
306 #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0)
307 #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4)
308 #define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20)
309 #define EIP197_MST_CTRL_BYTE_SWAP BIT(24)
310 #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25)
311 #define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24)
312
313 /* EIP197_PE_IN_DBUF/TBUF_THRES */
314 #define EIP197_PE_IN_xBUF_THRES_MIN(n) ((n) << 8)
315 #define EIP197_PE_IN_xBUF_THRES_MAX(n) ((n) << 12)
316
317 /* EIP197_PE_OUT_DBUF_THRES */
318 #define EIP197_PE_OUT_DBUF_THRES_MIN(n) ((n) << 0)
319 #define EIP197_PE_OUT_DBUF_THRES_MAX(n) ((n) << 4)
320
321 /* EIP197_PE_ICE_SCRATCH_CTRL */
322 #define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER BIT(2)
323 #define EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN BIT(3)
324 #define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS BIT(24)
325 #define EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS BIT(25)
326
327 /* EIP197_PE_ICE_SCRATCH_RAM */
328 #define EIP197_NUM_OF_SCRATCH_BLOCKS 32
329
330 /* EIP197_PE_ICE_PUE/FPP_CTRL */
331 #define EIP197_PE_ICE_x_CTRL_SW_RESET BIT(0)
332 #define EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR BIT(14)
333 #define EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR BIT(15)
334
335 /* EIP197_PE_ICE_RAM_CTRL */
336 #define EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN BIT(0)
337 #define EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN BIT(1)
338
339 /* EIP197_PE_EIP96_TOKEN_CTRL */
340 #define EIP197_PE_EIP96_TOKEN_CTRL_CTX_UPDATES BIT(16)
341 #define EIP197_PE_EIP96_TOKEN_CTRL_NO_TOKEN_WAIT BIT(17)
342 #define EIP197_PE_EIP96_TOKEN_CTRL_ENABLE_TIMEOUT BIT(22)
343
344 /* EIP197_PE_EIP96_FUNCTION_EN */
345 #define EIP197_FUNCTION_ALL 0xffffffff
346
347 /* EIP197_PE_EIP96_CONTEXT_CTRL */
348 #define EIP197_CONTEXT_SIZE(n) (n)
349 #define EIP197_ADDRESS_MODE BIT(8)
350 #define EIP197_CONTROL_MODE BIT(9)
351
352 /* EIP197_PE_EIP96_TOKEN_CTRL2 */
353 #define EIP197_PE_EIP96_TOKEN_CTRL2_CTX_DONE BIT(3)
354
355 /* EIP197_STRC_CONFIG */
356 #define EIP197_STRC_CONFIG_INIT BIT(31)
357 #define EIP197_STRC_CONFIG_LARGE_REC(s) (s<<8)
358 #define EIP197_STRC_CONFIG_SMALL_REC(s) (s<<0)
359
360 /* EIP197_FLUE_CONFIG */
361 #define EIP197_FLUE_CONFIG_MAGIC 0xc7000004
362
363 /* Context Control */
364 struct safexcel_context_record {
365 __le32 control0;
366 __le32 control1;
367
368 __le32 data[40];
369 } __packed;
370
371 /* control0 */
372 #define CONTEXT_CONTROL_TYPE_NULL_OUT 0x0
373 #define CONTEXT_CONTROL_TYPE_NULL_IN 0x1
374 #define CONTEXT_CONTROL_TYPE_HASH_OUT 0x2
375 #define CONTEXT_CONTROL_TYPE_HASH_IN 0x3
376 #define CONTEXT_CONTROL_TYPE_CRYPTO_OUT 0x4
377 #define CONTEXT_CONTROL_TYPE_CRYPTO_IN 0x5
378 #define CONTEXT_CONTROL_TYPE_ENCRYPT_HASH_OUT 0x6
379 #define CONTEXT_CONTROL_TYPE_DECRYPT_HASH_IN 0x7
380 #define CONTEXT_CONTROL_TYPE_HASH_ENCRYPT_OUT 0xe
381 #define CONTEXT_CONTROL_TYPE_HASH_DECRYPT_IN 0xf
382 #define CONTEXT_CONTROL_RESTART_HASH BIT(4)
383 #define CONTEXT_CONTROL_NO_FINISH_HASH BIT(5)
384 #define CONTEXT_CONTROL_SIZE(n) ((n) << 8)
385 #define CONTEXT_CONTROL_KEY_EN BIT(16)
386 #define CONTEXT_CONTROL_CRYPTO_ALG_DES (0x0 << 17)
387 #define CONTEXT_CONTROL_CRYPTO_ALG_3DES (0x2 << 17)
388 #define CONTEXT_CONTROL_CRYPTO_ALG_AES128 (0x5 << 17)
389 #define CONTEXT_CONTROL_CRYPTO_ALG_AES192 (0x6 << 17)
390 #define CONTEXT_CONTROL_CRYPTO_ALG_AES256 (0x7 << 17)
391 #define CONTEXT_CONTROL_CRYPTO_ALG_CHACHA20 (0x8 << 17)
392 #define CONTEXT_CONTROL_CRYPTO_ALG_SM4 (0xd << 17)
393 #define CONTEXT_CONTROL_DIGEST_INITIAL (0x0 << 21)
394 #define CONTEXT_CONTROL_DIGEST_PRECOMPUTED (0x1 << 21)
395 #define CONTEXT_CONTROL_DIGEST_XCM (0x2 << 21)
396 #define CONTEXT_CONTROL_DIGEST_HMAC (0x3 << 21)
397 #define CONTEXT_CONTROL_CRYPTO_ALG_MD5 (0x0 << 23)
398 #define CONTEXT_CONTROL_CRYPTO_ALG_CRC32 (0x0 << 23)
399 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA1 (0x2 << 23)
400 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA224 (0x4 << 23)
401 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA256 (0x3 << 23)
402 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA384 (0x6 << 23)
403 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA512 (0x5 << 23)
404 #define CONTEXT_CONTROL_CRYPTO_ALG_GHASH (0x4 << 23)
405 #define CONTEXT_CONTROL_CRYPTO_ALG_XCBC128 (0x1 << 23)
406 #define CONTEXT_CONTROL_CRYPTO_ALG_XCBC192 (0x2 << 23)
407 #define CONTEXT_CONTROL_CRYPTO_ALG_XCBC256 (0x3 << 23)
408 #define CONTEXT_CONTROL_CRYPTO_ALG_SM3 (0x7 << 23)
409 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_256 (0xb << 23)
410 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_224 (0xc << 23)
411 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_512 (0xd << 23)
412 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_384 (0xe << 23)
413 #define CONTEXT_CONTROL_CRYPTO_ALG_POLY1305 (0xf << 23)
414 #define CONTEXT_CONTROL_INV_FR (0x5 << 24)
415 #define CONTEXT_CONTROL_INV_TR (0x6 << 24)
416
417 /* control1 */
418 #define CONTEXT_CONTROL_CRYPTO_MODE_ECB (0 << 0)
419 #define CONTEXT_CONTROL_CRYPTO_MODE_CBC (1 << 0)
420 #define CONTEXT_CONTROL_CHACHA20_MODE_256_32 (2 << 0)
421 #define CONTEXT_CONTROL_CRYPTO_MODE_OFB (4 << 0)
422 #define CONTEXT_CONTROL_CRYPTO_MODE_CFB (5 << 0)
423 #define CONTEXT_CONTROL_CRYPTO_MODE_CTR_LOAD (6 << 0)
424 #define CONTEXT_CONTROL_CRYPTO_MODE_XTS (7 << 0)
425 #define CONTEXT_CONTROL_CRYPTO_MODE_XCM ((6 << 0) | BIT(17))
426 #define CONTEXT_CONTROL_CHACHA20_MODE_CALC_OTK (12 << 0)
427 #define CONTEXT_CONTROL_IV0 BIT(5)
428 #define CONTEXT_CONTROL_IV1 BIT(6)
429 #define CONTEXT_CONTROL_IV2 BIT(7)
430 #define CONTEXT_CONTROL_IV3 BIT(8)
431 #define CONTEXT_CONTROL_DIGEST_CNT BIT(9)
432 #define CONTEXT_CONTROL_COUNTER_MODE BIT(10)
433 #define CONTEXT_CONTROL_CRYPTO_STORE BIT(12)
434 #define CONTEXT_CONTROL_HASH_STORE BIT(19)
435
436 #define EIP197_XCM_MODE_GCM 1
437 #define EIP197_XCM_MODE_CCM 2
438
439 #define EIP197_AEAD_TYPE_IPSEC_ESP 2
440 #define EIP197_AEAD_TYPE_IPSEC_ESP_GMAC 3
441 #define EIP197_AEAD_IPSEC_IV_SIZE 8
442 #define EIP197_AEAD_IPSEC_NONCE_SIZE 4
443 #define EIP197_AEAD_IPSEC_COUNTER_SIZE 4
444 #define EIP197_AEAD_IPSEC_CCM_NONCE_SIZE 3
445
446 /* The hash counter given to the engine in the context has a granularity of
447 * 64 bits.
448 */
449 #define EIP197_COUNTER_BLOCK_SIZE 64
450
451 /* EIP197_CS_RAM_CTRL */
452 #define EIP197_TRC_ENABLE_0 BIT(4)
453 #define EIP197_TRC_ENABLE_1 BIT(5)
454 #define EIP197_TRC_ENABLE_2 BIT(6)
455 #define EIP197_TRC_ENABLE_MASK GENMASK(6, 4)
456 #define EIP197_CS_BANKSEL_MASK GENMASK(14, 12)
457 #define EIP197_CS_BANKSEL_OFS 12
458
459 /* EIP197_TRC_PARAMS */
460 #define EIP197_TRC_PARAMS_SW_RESET BIT(0)
461 #define EIP197_TRC_PARAMS_DATA_ACCESS BIT(2)
462 #define EIP197_TRC_PARAMS_HTABLE_SZ(x) ((x) << 4)
463 #define EIP197_TRC_PARAMS_BLK_TIMER_SPEED(x) ((x) << 10)
464 #define EIP197_TRC_PARAMS_RC_SZ_LARGE(n) ((n) << 18)
465
466 /* EIP197_TRC_FREECHAIN */
467 #define EIP197_TRC_FREECHAIN_HEAD_PTR(p) (p)
468 #define EIP197_TRC_FREECHAIN_TAIL_PTR(p) ((p) << 16)
469
470 /* EIP197_TRC_PARAMS2 */
471 #define EIP197_TRC_PARAMS2_HTABLE_PTR(p) (p)
472 #define EIP197_TRC_PARAMS2_RC_SZ_SMALL(n) ((n) << 18)
473
474 /* Cache helpers */
475 #define EIP197_MIN_DSIZE 1024
476 #define EIP197_MIN_ASIZE 8
477 #define EIP197_CS_TRC_REC_WC 64
478 #define EIP197_CS_RC_SIZE (4 * sizeof(u32))
479 #define EIP197_CS_RC_NEXT(x) (x)
480 #define EIP197_CS_RC_PREV(x) ((x) << 10)
481 #define EIP197_RC_NULL 0x3ff
482
483 /* Result data */
484 struct result_data_desc {
485 u32 packet_length:17;
486 u32 error_code:15;
487
488 u8 bypass_length:4;
489 u8 e15:1;
490 u16 rsvd0;
491 u8 hash_bytes:1;
492 u8 hash_length:6;
493 u8 generic_bytes:1;
494 u8 checksum:1;
495 u8 next_header:1;
496 u8 length:1;
497
498 u16 application_id;
499 u16 rsvd1;
500
501 u32 rsvd2[5];
502 } __packed;
503
504
505 /* Basic Result Descriptor format */
506 struct safexcel_result_desc {
507 u32 particle_size:17;
508 u8 rsvd0:3;
509 u8 descriptor_overflow:1;
510 u8 buffer_overflow:1;
511 u8 last_seg:1;
512 u8 first_seg:1;
513 u16 result_size:8;
514
515 u32 rsvd1;
516
517 u32 data_lo;
518 u32 data_hi;
519 } __packed;
520
521 /*
522 * The EIP(1)97 only needs to fetch the descriptor part of
523 * the result descriptor, not the result token part!
524 */
525 #define EIP197_RD64_FETCH_SIZE (sizeof(struct safexcel_result_desc) /\
526 sizeof(u32))
527 #define EIP197_RD64_RESULT_SIZE (sizeof(struct result_data_desc) /\
528 sizeof(u32))
529
530 struct safexcel_token {
531 u32 packet_length:17;
532 u8 stat:2;
533 u16 instructions:9;
534 u8 opcode:4;
535 } __packed;
536
537 #define EIP197_TOKEN_HASH_RESULT_VERIFY BIT(16)
538
539 #define EIP197_TOKEN_CTX_OFFSET(x) (x)
540 #define EIP197_TOKEN_DIRECTION_EXTERNAL BIT(11)
541 #define EIP197_TOKEN_EXEC_IF_SUCCESSFUL (0x1 << 12)
542
543 #define EIP197_TOKEN_STAT_LAST_HASH BIT(0)
544 #define EIP197_TOKEN_STAT_LAST_PACKET BIT(1)
545 #define EIP197_TOKEN_OPCODE_DIRECTION 0x0
546 #define EIP197_TOKEN_OPCODE_INSERT 0x2
547 #define EIP197_TOKEN_OPCODE_NOOP EIP197_TOKEN_OPCODE_INSERT
548 #define EIP197_TOKEN_OPCODE_RETRIEVE 0x4
549 #define EIP197_TOKEN_OPCODE_INSERT_REMRES 0xa
550 #define EIP197_TOKEN_OPCODE_VERIFY 0xd
551 #define EIP197_TOKEN_OPCODE_CTX_ACCESS 0xe
552 #define EIP197_TOKEN_OPCODE_BYPASS GENMASK(3, 0)
553
554 static inline void eip197_noop_token(struct safexcel_token *token)
555 {
556 token->opcode = EIP197_TOKEN_OPCODE_NOOP;
557 token->packet_length = BIT(2);
558 token->stat = 0;
559 token->instructions = 0;
560 }
561
562 /* Instructions */
563 #define EIP197_TOKEN_INS_INSERT_HASH_DIGEST 0x1c
564 #define EIP197_TOKEN_INS_ORIGIN_IV0 0x14
565 #define EIP197_TOKEN_INS_ORIGIN_TOKEN 0x1b
566 #define EIP197_TOKEN_INS_ORIGIN_LEN(x) ((x) << 5)
567 #define EIP197_TOKEN_INS_TYPE_OUTPUT BIT(5)
568 #define EIP197_TOKEN_INS_TYPE_HASH BIT(6)
569 #define EIP197_TOKEN_INS_TYPE_CRYPTO BIT(7)
570 #define EIP197_TOKEN_INS_LAST BIT(8)
571
572 /* Processing Engine Control Data */
573 struct safexcel_control_data_desc {
574 u32 packet_length:17;
575 u16 options:13;
576 u8 type:2;
577
578 u16 application_id;
579 u16 rsvd;
580
581 u32 context_lo;
582 u32 context_hi;
583
584 u32 control0;
585 u32 control1;
586
587 u32 token[EIP197_EMB_TOKENS];
588 } __packed;
589
590 #define EIP197_OPTION_MAGIC_VALUE BIT(0)
591 #define EIP197_OPTION_64BIT_CTX BIT(1)
592 #define EIP197_OPTION_RC_AUTO (0x2 << 3)
593 #define EIP197_OPTION_CTX_CTRL_IN_CMD BIT(8)
594 #define EIP197_OPTION_2_TOKEN_IV_CMD GENMASK(11, 10)
595 #define EIP197_OPTION_4_TOKEN_IV_CMD GENMASK(11, 9)
596
597 #define EIP197_TYPE_BCLA 0x0
598 #define EIP197_TYPE_EXTENDED 0x3
599 #define EIP197_CONTEXT_SMALL 0x2
600 #define EIP197_CONTEXT_SIZE_MASK 0x3
601
602 /* Basic Command Descriptor format */
603 struct safexcel_command_desc {
604 u32 particle_size:17;
605 u8 rsvd0:5;
606 u8 last_seg:1;
607 u8 first_seg:1;
608 u8 additional_cdata_size:8;
609
610 u32 rsvd1;
611
612 u32 data_lo;
613 u32 data_hi;
614
615 u32 atok_lo;
616 u32 atok_hi;
617
618 struct safexcel_control_data_desc control_data;
619 } __packed;
620
621 #define EIP197_CD64_FETCH_SIZE (sizeof(struct safexcel_command_desc) /\
622 sizeof(u32))
623
624 /*
625 * Internal structures & functions
626 */
627
628 #define EIP197_FW_TERMINAL_NOPS 2
629 #define EIP197_FW_START_POLLCNT 16
630 #define EIP197_FW_PUE_READY 0x14
631 #define EIP197_FW_FPP_READY 0x18
632
633 enum eip197_fw {
634 FW_IFPP = 0,
635 FW_IPUE,
636 FW_NB
637 };
638
639 struct safexcel_desc_ring {
640 void *base;
641 void *shbase;
642 void *base_end;
643 void *shbase_end;
644 dma_addr_t base_dma;
645 dma_addr_t shbase_dma;
646
647 /* write and read pointers */
648 void *write;
649 void *shwrite;
650 void *read;
651
652 /* descriptor element offset */
653 unsigned int offset;
654 unsigned int shoffset;
655 };
656
657 enum safexcel_alg_type {
658 SAFEXCEL_ALG_TYPE_SKCIPHER,
659 SAFEXCEL_ALG_TYPE_AEAD,
660 SAFEXCEL_ALG_TYPE_AHASH,
661 };
662
663 struct safexcel_config {
664 u32 pes;
665 u32 rings;
666
667 u32 cd_size;
668 u32 cd_offset;
669 u32 cdsh_offset;
670
671 u32 rd_size;
672 u32 rd_offset;
673 u32 res_offset;
674 };
675
676 struct safexcel_work_data {
677 struct work_struct work;
678 struct safexcel_crypto_priv *priv;
679 int ring;
680 };
681
682 struct safexcel_ring {
683 spinlock_t lock;
684
685 struct workqueue_struct *workqueue;
686 struct safexcel_work_data work_data;
687
688 /* command/result rings */
689 struct safexcel_desc_ring cdr;
690 struct safexcel_desc_ring rdr;
691
692 /* result ring crypto API request */
693 struct crypto_async_request **rdr_req;
694
695 /* queue */
696 struct crypto_queue queue;
697 spinlock_t queue_lock;
698
699 /* Number of requests in the engine. */
700 int requests;
701
702 /* The ring is currently handling at least one request */
703 bool busy;
704
705 /* Store for current requests when bailing out of the dequeueing
706 * function when no enough resources are available.
707 */
708 struct crypto_async_request *req;
709 struct crypto_async_request *backlog;
710 };
711
712 /* EIP integration context flags */
713 enum safexcel_eip_version {
714 /* Platform (EIP integration context) specifier */
715 EIP97IES_MRVL,
716 EIP197B_MRVL,
717 EIP197D_MRVL,
718 EIP197_DEVBRD
719 };
720
721 /* Priority we use for advertising our algorithms */
722 #define SAFEXCEL_CRA_PRIORITY 300
723
724 /* SM3 digest result for zero length message */
725 #define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \
726 "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \
727 "\x22\xBE\xC8\xC7\x28\xFE\xFB\x74" \
728 "\x7E\xD0\x35\xEB\x50\x82\xAA\x2B"
729
730 /* EIP algorithm presence flags */
731 enum safexcel_eip_algorithms {
732 SAFEXCEL_ALG_BC0 = BIT(5),
733 SAFEXCEL_ALG_SM4 = BIT(6),
734 SAFEXCEL_ALG_SM3 = BIT(7),
735 SAFEXCEL_ALG_CHACHA20 = BIT(8),
736 SAFEXCEL_ALG_POLY1305 = BIT(9),
737 SAFEXCEL_SEQMASK_256 = BIT(10),
738 SAFEXCEL_SEQMASK_384 = BIT(11),
739 SAFEXCEL_ALG_AES = BIT(12),
740 SAFEXCEL_ALG_AES_XFB = BIT(13),
741 SAFEXCEL_ALG_DES = BIT(15),
742 SAFEXCEL_ALG_DES_XFB = BIT(16),
743 SAFEXCEL_ALG_ARC4 = BIT(18),
744 SAFEXCEL_ALG_AES_XTS = BIT(20),
745 SAFEXCEL_ALG_WIRELESS = BIT(21),
746 SAFEXCEL_ALG_MD5 = BIT(22),
747 SAFEXCEL_ALG_SHA1 = BIT(23),
748 SAFEXCEL_ALG_SHA2_256 = BIT(25),
749 SAFEXCEL_ALG_SHA2_512 = BIT(26),
750 SAFEXCEL_ALG_XCBC_MAC = BIT(27),
751 SAFEXCEL_ALG_CBC_MAC_ALL = BIT(29),
752 SAFEXCEL_ALG_GHASH = BIT(30),
753 SAFEXCEL_ALG_SHA3 = BIT(31),
754 };
755
756 struct safexcel_register_offsets {
757 u32 hia_aic;
758 u32 hia_aic_g;
759 u32 hia_aic_r;
760 u32 hia_aic_xdr;
761 u32 hia_dfe;
762 u32 hia_dfe_thr;
763 u32 hia_dse;
764 u32 hia_dse_thr;
765 u32 hia_gen_cfg;
766 u32 pe;
767 u32 global;
768 };
769
770 enum safexcel_flags {
771 EIP197_TRC_CACHE = BIT(0),
772 SAFEXCEL_HW_EIP197 = BIT(1),
773 EIP197_PE_ARB = BIT(2),
774 EIP197_ICE = BIT(3),
775 EIP197_SIMPLE_TRC = BIT(4),
776 };
777
778 struct safexcel_hwconfig {
779 enum safexcel_eip_algorithms algo_flags;
780 int hwver;
781 int hiaver;
782 int ppver;
783 int pever;
784 int hwdataw;
785 int hwcfsize;
786 int hwrfsize;
787 int hwnumpes;
788 int hwnumrings;
789 int hwnumraic;
790 };
791
792 struct safexcel_crypto_priv {
793 void __iomem *base;
794 struct device *dev;
795 struct clk *clk;
796 struct clk *reg_clk;
797 struct safexcel_config config;
798
799 enum safexcel_eip_version version;
800 struct safexcel_register_offsets offsets;
801 struct safexcel_hwconfig hwconfig;
802 u32 flags;
803
804 /* context DMA pool */
805 struct dma_pool *context_pool;
806
807 atomic_t ring_used;
808
809 struct safexcel_ring *ring;
810 };
811
812 struct safexcel_context {
813 int (*send)(struct crypto_async_request *req, int ring,
814 int *commands, int *results);
815 int (*handle_result)(struct safexcel_crypto_priv *priv, int ring,
816 struct crypto_async_request *req, bool *complete,
817 int *ret);
818 struct safexcel_context_record *ctxr;
819 dma_addr_t ctxr_dma;
820
821 int ring;
822 bool needs_inv;
823 bool exit_inv;
824 };
825
826 #define HASH_CACHE_SIZE SHA512_BLOCK_SIZE
827
828 struct safexcel_ahash_export_state {
829 u64 len;
830 u64 processed;
831
832 u32 digest;
833
834 u32 state[SHA512_DIGEST_SIZE / sizeof(u32)];
835 u8 cache[HASH_CACHE_SIZE];
836 };
837
838 /*
839 * Template structure to describe the algorithms in order to register them.
840 * It also has the purpose to contain our private structure and is actually
841 * the only way I know in this framework to avoid having global pointers...
842 */
843 struct safexcel_alg_template {
844 struct safexcel_crypto_priv *priv;
845 enum safexcel_alg_type type;
846 enum safexcel_eip_algorithms algo_mask;
847 union {
848 struct skcipher_alg skcipher;
849 struct aead_alg aead;
850 struct ahash_alg ahash;
851 } alg;
852 };
853
854 struct safexcel_inv_result {
855 struct completion completion;
856 int error;
857 };
858
859 void safexcel_dequeue(struct safexcel_crypto_priv *priv, int ring);
860 int safexcel_rdesc_check_errors(struct safexcel_crypto_priv *priv,
861 void *rdp);
862 void safexcel_complete(struct safexcel_crypto_priv *priv, int ring);
863 int safexcel_invalidate_cache(struct crypto_async_request *async,
864 struct safexcel_crypto_priv *priv,
865 dma_addr_t ctxr_dma, int ring);
866 int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv,
867 struct safexcel_desc_ring *cdr,
868 struct safexcel_desc_ring *rdr);
869 int safexcel_select_ring(struct safexcel_crypto_priv *priv);
870 void *safexcel_ring_next_rptr(struct safexcel_crypto_priv *priv,
871 struct safexcel_desc_ring *ring);
872 void *safexcel_ring_first_rptr(struct safexcel_crypto_priv *priv, int ring);
873 void safexcel_ring_rollback_wptr(struct safexcel_crypto_priv *priv,
874 struct safexcel_desc_ring *ring);
875 struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *priv,
876 int ring_id,
877 bool first, bool last,
878 dma_addr_t data, u32 len,
879 u32 full_data_len,
880 dma_addr_t context,
881 struct safexcel_token **atoken);
882 struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv,
883 int ring_id,
884 bool first, bool last,
885 dma_addr_t data, u32 len);
886 int safexcel_ring_first_rdr_index(struct safexcel_crypto_priv *priv,
887 int ring);
888 int safexcel_ring_rdr_rdesc_index(struct safexcel_crypto_priv *priv,
889 int ring,
890 struct safexcel_result_desc *rdesc);
891 void safexcel_rdr_req_set(struct safexcel_crypto_priv *priv,
892 int ring,
893 struct safexcel_result_desc *rdesc,
894 struct crypto_async_request *req);
895 inline struct crypto_async_request *
896 safexcel_rdr_req_get(struct safexcel_crypto_priv *priv, int ring);
897 void safexcel_inv_complete(struct crypto_async_request *req, int error);
898 int safexcel_hmac_setkey(const char *alg, const u8 *key, unsigned int keylen,
899 void *istate, void *ostate);
900
901 /* available algorithms */
902 extern struct safexcel_alg_template safexcel_alg_ecb_des;
903 extern struct safexcel_alg_template safexcel_alg_cbc_des;
904 extern struct safexcel_alg_template safexcel_alg_ecb_des3_ede;
905 extern struct safexcel_alg_template safexcel_alg_cbc_des3_ede;
906 extern struct safexcel_alg_template safexcel_alg_ecb_aes;
907 extern struct safexcel_alg_template safexcel_alg_cbc_aes;
908 extern struct safexcel_alg_template safexcel_alg_cfb_aes;
909 extern struct safexcel_alg_template safexcel_alg_ofb_aes;
910 extern struct safexcel_alg_template safexcel_alg_ctr_aes;
911 extern struct safexcel_alg_template safexcel_alg_md5;
912 extern struct safexcel_alg_template safexcel_alg_sha1;
913 extern struct safexcel_alg_template safexcel_alg_sha224;
914 extern struct safexcel_alg_template safexcel_alg_sha256;
915 extern struct safexcel_alg_template safexcel_alg_sha384;
916 extern struct safexcel_alg_template safexcel_alg_sha512;
917 extern struct safexcel_alg_template safexcel_alg_hmac_md5;
918 extern struct safexcel_alg_template safexcel_alg_hmac_sha1;
919 extern struct safexcel_alg_template safexcel_alg_hmac_sha224;
920 extern struct safexcel_alg_template safexcel_alg_hmac_sha256;
921 extern struct safexcel_alg_template safexcel_alg_hmac_sha384;
922 extern struct safexcel_alg_template safexcel_alg_hmac_sha512;
923 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_aes;
924 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_aes;
925 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_aes;
926 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_aes;
927 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_aes;
928 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_des3_ede;
929 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_ctr_aes;
930 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_ctr_aes;
931 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_ctr_aes;
932 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_ctr_aes;
933 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_ctr_aes;
934 extern struct safexcel_alg_template safexcel_alg_xts_aes;
935 extern struct safexcel_alg_template safexcel_alg_gcm;
936 extern struct safexcel_alg_template safexcel_alg_ccm;
937 extern struct safexcel_alg_template safexcel_alg_crc32;
938 extern struct safexcel_alg_template safexcel_alg_cbcmac;
939 extern struct safexcel_alg_template safexcel_alg_xcbcmac;
940 extern struct safexcel_alg_template safexcel_alg_cmac;
941 extern struct safexcel_alg_template safexcel_alg_chacha20;
942 extern struct safexcel_alg_template safexcel_alg_chachapoly;
943 extern struct safexcel_alg_template safexcel_alg_chachapoly_esp;
944 extern struct safexcel_alg_template safexcel_alg_sm3;
945 extern struct safexcel_alg_template safexcel_alg_hmac_sm3;
946 extern struct safexcel_alg_template safexcel_alg_ecb_sm4;
947 extern struct safexcel_alg_template safexcel_alg_cbc_sm4;
948 extern struct safexcel_alg_template safexcel_alg_ofb_sm4;
949 extern struct safexcel_alg_template safexcel_alg_cfb_sm4;
950 extern struct safexcel_alg_template safexcel_alg_ctr_sm4;
951 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_sm4;
952 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sm3_cbc_sm4;
953 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_ctr_sm4;
954 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sm3_ctr_sm4;
955 extern struct safexcel_alg_template safexcel_alg_sha3_224;
956 extern struct safexcel_alg_template safexcel_alg_sha3_256;
957 extern struct safexcel_alg_template safexcel_alg_sha3_384;
958 extern struct safexcel_alg_template safexcel_alg_sha3_512;
959 extern struct safexcel_alg_template safexcel_alg_hmac_sha3_224;
960 extern struct safexcel_alg_template safexcel_alg_hmac_sha3_256;
961 extern struct safexcel_alg_template safexcel_alg_hmac_sha3_384;
962 extern struct safexcel_alg_template safexcel_alg_hmac_sha3_512;
963 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_des;
964 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_des3_ede;
965 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_des3_ede;
966 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_des3_ede;
967 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_des3_ede;
968 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_des;
969 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_des;
970 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_des;
971 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_des;
972 extern struct safexcel_alg_template safexcel_alg_rfc4106_gcm;
973 extern struct safexcel_alg_template safexcel_alg_rfc4543_gcm;
974 extern struct safexcel_alg_template safexcel_alg_rfc4309_ccm;
975
976 #endif
Linux with added FPC-III support