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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-qcom-geni.c
blob18d1e4fd4cf345db8bc7cb69770cb11a00433d37
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
3
4 #include <linux/acpi.h>
5 #include <linux/clk.h>
6 #include <linux/dma-mapping.h>
7 #include <linux/err.h>
8 #include <linux/i2c.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/qcom-geni-se.h>
16 #include <linux/spinlock.h>
17
18 #define SE_I2C_TX_TRANS_LEN 0x26c
19 #define SE_I2C_RX_TRANS_LEN 0x270
20 #define SE_I2C_SCL_COUNTERS 0x278
21
22 #define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
23 M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
24 #define SE_I2C_ABORT BIT(1)
25
26 /* M_CMD OP codes for I2C */
27 #define I2C_WRITE 0x1
28 #define I2C_READ 0x2
29 #define I2C_WRITE_READ 0x3
30 #define I2C_ADDR_ONLY 0x4
31 #define I2C_BUS_CLEAR 0x6
32 #define I2C_STOP_ON_BUS 0x7
33 /* M_CMD params for I2C */
34 #define PRE_CMD_DELAY BIT(0)
35 #define TIMESTAMP_BEFORE BIT(1)
36 #define STOP_STRETCH BIT(2)
37 #define TIMESTAMP_AFTER BIT(3)
38 #define POST_COMMAND_DELAY BIT(4)
39 #define IGNORE_ADD_NACK BIT(6)
40 #define READ_FINISHED_WITH_ACK BIT(7)
41 #define BYPASS_ADDR_PHASE BIT(8)
42 #define SLV_ADDR_MSK GENMASK(15, 9)
43 #define SLV_ADDR_SHFT 9
44 /* I2C SCL COUNTER fields */
45 #define HIGH_COUNTER_MSK GENMASK(29, 20)
46 #define HIGH_COUNTER_SHFT 20
47 #define LOW_COUNTER_MSK GENMASK(19, 10)
48 #define LOW_COUNTER_SHFT 10
49 #define CYCLE_COUNTER_MSK GENMASK(9, 0)
50
51 enum geni_i2c_err_code {
52 GP_IRQ0,
53 NACK,
54 GP_IRQ2,
55 BUS_PROTO,
56 ARB_LOST,
57 GP_IRQ5,
58 GENI_OVERRUN,
59 GENI_ILLEGAL_CMD,
60 GENI_ABORT_DONE,
61 GENI_TIMEOUT,
62 };
63
64 #define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \
65 << 5)
66
67 #define I2C_AUTO_SUSPEND_DELAY 250
68 #define KHZ(freq) (1000 * freq)
69 #define PACKING_BYTES_PW 4
70
71 #define ABORT_TIMEOUT HZ
72 #define XFER_TIMEOUT HZ
73 #define RST_TIMEOUT HZ
74
75 struct geni_i2c_dev {
76 struct geni_se se;
77 u32 tx_wm;
78 int irq;
79 int err;
80 struct i2c_adapter adap;
81 struct completion done;
82 struct i2c_msg *cur;
83 int cur_wr;
84 int cur_rd;
85 spinlock_t lock;
86 u32 clk_freq_out;
87 const struct geni_i2c_clk_fld *clk_fld;
88 int suspended;
89 };
90
91 struct geni_i2c_err_log {
92 int err;
93 const char *msg;
94 };
95
96 static const struct geni_i2c_err_log gi2c_log[] = {
97 [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"},
98 [NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"},
99 [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"},
100 [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unepxected start/stop"},
101 [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"},
102 [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"},
103 [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"},
104 [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"},
105 [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"},
106 [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"},
107 };
108
109 struct geni_i2c_clk_fld {
110 u32 clk_freq_out;
111 u8 clk_div;
112 u8 t_high_cnt;
113 u8 t_low_cnt;
114 u8 t_cycle_cnt;
115 };
116
117 /*
118 * Hardware uses the underlying formula to calculate time periods of
119 * SCL clock cycle. Firmware uses some additional cycles excluded from the
120 * below formula and it is confirmed that the time periods are within
121 * specification limits.
122 *
123 * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock
124 * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock
125 * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock
126 * clk_freq_out = t / t_cycle
127 * source_clock = 19.2 MHz
128 */
129 static const struct geni_i2c_clk_fld geni_i2c_clk_map[] = {
130 {KHZ(100), 7, 10, 11, 26},
131 {KHZ(400), 2, 5, 12, 24},
132 {KHZ(1000), 1, 3, 9, 18},
133 };
134
135 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
136 {
137 int i;
138 const struct geni_i2c_clk_fld *itr = geni_i2c_clk_map;
139
140 for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) {
141 if (itr->clk_freq_out == gi2c->clk_freq_out) {
142 gi2c->clk_fld = itr;
143 return 0;
144 }
145 }
146 return -EINVAL;
147 }
148
149 static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
150 {
151 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
152 u32 val;
153
154 writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL);
155
156 val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN;
157 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG);
158
159 val = itr->t_high_cnt << HIGH_COUNTER_SHFT;
160 val |= itr->t_low_cnt << LOW_COUNTER_SHFT;
161 val |= itr->t_cycle_cnt;
162 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
163 }
164
165 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
166 {
167 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
168 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
169 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);
170 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS);
171 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN);
172 u32 rx_st, tx_st;
173
174 if (dma) {
175 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
176 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
177 } else {
178 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS);
179 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS);
180 }
181 dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n",
182 dma, tx_st, rx_st, m_stat);
183 dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n",
184 m_cmd, geni_s, geni_ios);
185 }
186
187 static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err)
188 {
189 if (!gi2c->err)
190 gi2c->err = gi2c_log[err].err;
191 if (gi2c->cur)
192 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n",
193 gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags);
194
195 if (err != NACK && err != GENI_ABORT_DONE) {
196 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
197 geni_i2c_err_misc(gi2c);
198 }
199 }
200
201 static irqreturn_t geni_i2c_irq(int irq, void *dev)
202 {
203 struct geni_i2c_dev *gi2c = dev;
204 void __iomem *base = gi2c->se.base;
205 int j, p;
206 u32 m_stat;
207 u32 rx_st;
208 u32 dm_tx_st;
209 u32 dm_rx_st;
210 u32 dma;
211 u32 val;
212 struct i2c_msg *cur;
213 unsigned long flags;
214
215 spin_lock_irqsave(&gi2c->lock, flags);
216 m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS);
217 rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS);
218 dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT);
219 dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT);
220 dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
221 cur = gi2c->cur;
222
223 if (!cur ||
224 m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) ||
225 dm_rx_st & (DM_I2C_CB_ERR)) {
226 if (m_stat & M_GP_IRQ_1_EN)
227 geni_i2c_err(gi2c, NACK);
228 if (m_stat & M_GP_IRQ_3_EN)
229 geni_i2c_err(gi2c, BUS_PROTO);
230 if (m_stat & M_GP_IRQ_4_EN)
231 geni_i2c_err(gi2c, ARB_LOST);
232 if (m_stat & M_CMD_OVERRUN_EN)
233 geni_i2c_err(gi2c, GENI_OVERRUN);
234 if (m_stat & M_ILLEGAL_CMD_EN)
235 geni_i2c_err(gi2c, GENI_ILLEGAL_CMD);
236 if (m_stat & M_CMD_ABORT_EN)
237 geni_i2c_err(gi2c, GENI_ABORT_DONE);
238 if (m_stat & M_GP_IRQ_0_EN)
239 geni_i2c_err(gi2c, GP_IRQ0);
240
241 /* Disable the TX Watermark interrupt to stop TX */
242 if (!dma)
243 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
244 } else if (dma) {
245 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n",
246 dm_tx_st, dm_rx_st);
247 } else if (cur->flags & I2C_M_RD &&
248 m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) {
249 u32 rxcnt = rx_st & RX_FIFO_WC_MSK;
250
251 for (j = 0; j < rxcnt; j++) {
252 p = 0;
253 val = readl_relaxed(base + SE_GENI_RX_FIFOn);
254 while (gi2c->cur_rd < cur->len && p < sizeof(val)) {
255 cur->buf[gi2c->cur_rd++] = val & 0xff;
256 val >>= 8;
257 p++;
258 }
259 if (gi2c->cur_rd == cur->len)
260 break;
261 }
262 } else if (!(cur->flags & I2C_M_RD) &&
263 m_stat & M_TX_FIFO_WATERMARK_EN) {
264 for (j = 0; j < gi2c->tx_wm; j++) {
265 u32 temp;
266
267 val = 0;
268 p = 0;
269 while (gi2c->cur_wr < cur->len && p < sizeof(val)) {
270 temp = cur->buf[gi2c->cur_wr++];
271 val |= temp << (p * 8);
272 p++;
273 }
274 writel_relaxed(val, base + SE_GENI_TX_FIFOn);
275 /* TX Complete, Disable the TX Watermark interrupt */
276 if (gi2c->cur_wr == cur->len) {
277 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
278 break;
279 }
280 }
281 }
282
283 if (m_stat)
284 writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR);
285
286 if (dma && dm_tx_st)
287 writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR);
288 if (dma && dm_rx_st)
289 writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR);
290
291 /* if this is err with done-bit not set, handle that through timeout. */
292 if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN ||
293 dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE ||
294 dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE)
295 complete(&gi2c->done);
296
297 spin_unlock_irqrestore(&gi2c->lock, flags);
298
299 return IRQ_HANDLED;
300 }
301
302 static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c)
303 {
304 u32 val;
305 unsigned long time_left = ABORT_TIMEOUT;
306 unsigned long flags;
307
308 spin_lock_irqsave(&gi2c->lock, flags);
309 geni_i2c_err(gi2c, GENI_TIMEOUT);
310 gi2c->cur = NULL;
311 geni_se_abort_m_cmd(&gi2c->se);
312 spin_unlock_irqrestore(&gi2c->lock, flags);
313 do {
314 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
315 val = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
316 } while (!(val & M_CMD_ABORT_EN) && time_left);
317
318 if (!(val & M_CMD_ABORT_EN))
319 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n");
320 }
321
322 static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c)
323 {
324 u32 val;
325 unsigned long time_left = RST_TIMEOUT;
326
327 writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST);
328 do {
329 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
330 val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
331 } while (!(val & RX_RESET_DONE) && time_left);
332
333 if (!(val & RX_RESET_DONE))
334 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n");
335 }
336
337 static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c)
338 {
339 u32 val;
340 unsigned long time_left = RST_TIMEOUT;
341
342 writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST);
343 do {
344 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
345 val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
346 } while (!(val & TX_RESET_DONE) && time_left);
347
348 if (!(val & TX_RESET_DONE))
349 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n");
350 }
351
352 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
353 u32 m_param)
354 {
355 dma_addr_t rx_dma;
356 unsigned long time_left;
357 void *dma_buf = NULL;
358 struct geni_se *se = &gi2c->se;
359 size_t len = msg->len;
360
361 if (!of_machine_is_compatible("lenovo,yoga-c630"))
362 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
363
364 if (dma_buf)
365 geni_se_select_mode(se, GENI_SE_DMA);
366 else
367 geni_se_select_mode(se, GENI_SE_FIFO);
368
369 writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN);
370 geni_se_setup_m_cmd(se, I2C_READ, m_param);
371
372 if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) {
373 geni_se_select_mode(se, GENI_SE_FIFO);
374 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
375 dma_buf = NULL;
376 }
377
378 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
379 if (!time_left)
380 geni_i2c_abort_xfer(gi2c);
381
382 gi2c->cur_rd = 0;
383 if (dma_buf) {
384 if (gi2c->err)
385 geni_i2c_rx_fsm_rst(gi2c);
386 geni_se_rx_dma_unprep(se, rx_dma, len);
387 i2c_put_dma_safe_msg_buf(dma_buf, msg, !gi2c->err);
388 }
389
390 return gi2c->err;
391 }
392
393 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
394 u32 m_param)
395 {
396 dma_addr_t tx_dma;
397 unsigned long time_left;
398 void *dma_buf = NULL;
399 struct geni_se *se = &gi2c->se;
400 size_t len = msg->len;
401
402 if (!of_machine_is_compatible("lenovo,yoga-c630"))
403 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
404
405 if (dma_buf)
406 geni_se_select_mode(se, GENI_SE_DMA);
407 else
408 geni_se_select_mode(se, GENI_SE_FIFO);
409
410 writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN);
411 geni_se_setup_m_cmd(se, I2C_WRITE, m_param);
412
413 if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) {
414 geni_se_select_mode(se, GENI_SE_FIFO);
415 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
416 dma_buf = NULL;
417 }
418
419 if (!dma_buf) /* Get FIFO IRQ */
420 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG);
421
422 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
423 if (!time_left)
424 geni_i2c_abort_xfer(gi2c);
425
426 gi2c->cur_wr = 0;
427 if (dma_buf) {
428 if (gi2c->err)
429 geni_i2c_tx_fsm_rst(gi2c);
430 geni_se_tx_dma_unprep(se, tx_dma, len);
431 i2c_put_dma_safe_msg_buf(dma_buf, msg, !gi2c->err);
432 }
433
434 return gi2c->err;
435 }
436
437 static int geni_i2c_xfer(struct i2c_adapter *adap,
438 struct i2c_msg msgs[],
439 int num)
440 {
441 struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap);
442 int i, ret;
443
444 gi2c->err = 0;
445 reinit_completion(&gi2c->done);
446 ret = pm_runtime_get_sync(gi2c->se.dev);
447 if (ret < 0) {
448 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret);
449 pm_runtime_put_noidle(gi2c->se.dev);
450 /* Set device in suspended since resume failed */
451 pm_runtime_set_suspended(gi2c->se.dev);
452 return ret;
453 }
454
455 qcom_geni_i2c_conf(gi2c);
456 for (i = 0; i < num; i++) {
457 u32 m_param = i < (num - 1) ? STOP_STRETCH : 0;
458
459 m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK);
460
461 gi2c->cur = &msgs[i];
462 if (msgs[i].flags & I2C_M_RD)
463 ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param);
464 else
465 ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param);
466
467 if (ret)
468 break;
469 }
470 if (ret == 0)
471 ret = num;
472
473 pm_runtime_mark_last_busy(gi2c->se.dev);
474 pm_runtime_put_autosuspend(gi2c->se.dev);
475 gi2c->cur = NULL;
476 gi2c->err = 0;
477 return ret;
478 }
479
480 static u32 geni_i2c_func(struct i2c_adapter *adap)
481 {
482 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
483 }
484
485 static const struct i2c_algorithm geni_i2c_algo = {
486 .master_xfer = geni_i2c_xfer,
487 .functionality = geni_i2c_func,
488 };
489
490 #ifdef CONFIG_ACPI
491 static const struct acpi_device_id geni_i2c_acpi_match[] = {
492 { "QCOM0220"},
493 { },
494 };
495 MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match);
496 #endif
497
498 static int geni_i2c_probe(struct platform_device *pdev)
499 {
500 struct geni_i2c_dev *gi2c;
501 struct resource *res;
502 u32 proto, tx_depth;
503 int ret;
504 struct device *dev = &pdev->dev;
505
506 gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL);
507 if (!gi2c)
508 return -ENOMEM;
509
510 gi2c->se.dev = dev;
511 gi2c->se.wrapper = dev_get_drvdata(dev->parent);
512 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
513 gi2c->se.base = devm_ioremap_resource(dev, res);
514 if (IS_ERR(gi2c->se.base))
515 return PTR_ERR(gi2c->se.base);
516
517 gi2c->se.clk = devm_clk_get(dev, "se");
518 if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev))
519 return PTR_ERR(gi2c->se.clk);
520
521 ret = device_property_read_u32(dev, "clock-frequency",
522 &gi2c->clk_freq_out);
523 if (ret) {
524 dev_info(dev, "Bus frequency not specified, default to 100kHz.\n");
525 gi2c->clk_freq_out = KHZ(100);
526 }
527
528 if (has_acpi_companion(dev))
529 ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev));
530
531 gi2c->irq = platform_get_irq(pdev, 0);
532 if (gi2c->irq < 0)
533 return gi2c->irq;
534
535 ret = geni_i2c_clk_map_idx(gi2c);
536 if (ret) {
537 dev_err(dev, "Invalid clk frequency %d Hz: %d\n",
538 gi2c->clk_freq_out, ret);
539 return ret;
540 }
541
542 gi2c->adap.algo = &geni_i2c_algo;
543 init_completion(&gi2c->done);
544 spin_lock_init(&gi2c->lock);
545 platform_set_drvdata(pdev, gi2c);
546 ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, 0,
547 dev_name(dev), gi2c);
548 if (ret) {
549 dev_err(dev, "Request_irq failed:%d: err:%d\n",
550 gi2c->irq, ret);
551 return ret;
552 }
553 /* Disable the interrupt so that the system can enter low-power mode */
554 disable_irq(gi2c->irq);
555 i2c_set_adapdata(&gi2c->adap, gi2c);
556 gi2c->adap.dev.parent = dev;
557 gi2c->adap.dev.of_node = dev->of_node;
558 strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
559
560 ret = geni_se_resources_on(&gi2c->se);
561 if (ret) {
562 dev_err(dev, "Error turning on resources %d\n", ret);
563 return ret;
564 }
565 proto = geni_se_read_proto(&gi2c->se);
566 tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);
567 if (proto != GENI_SE_I2C) {
568 dev_err(dev, "Invalid proto %d\n", proto);
569 geni_se_resources_off(&gi2c->se);
570 return -ENXIO;
571 }
572 gi2c->tx_wm = tx_depth - 1;
573 geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth);
574 geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, PACKING_BYTES_PW,
575 true, true, true);
576 ret = geni_se_resources_off(&gi2c->se);
577 if (ret) {
578 dev_err(dev, "Error turning off resources %d\n", ret);
579 return ret;
580 }
581
582 dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
583
584 gi2c->suspended = 1;
585 pm_runtime_set_suspended(gi2c->se.dev);
586 pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY);
587 pm_runtime_use_autosuspend(gi2c->se.dev);
588 pm_runtime_enable(gi2c->se.dev);
589
590 ret = i2c_add_adapter(&gi2c->adap);
591 if (ret) {
592 dev_err(dev, "Error adding i2c adapter %d\n", ret);
593 pm_runtime_disable(gi2c->se.dev);
594 return ret;
595 }
596
597 dev_dbg(dev, "Geni-I2C adaptor successfully added\n");
598
599 return 0;
600 }
601
602 static int geni_i2c_remove(struct platform_device *pdev)
603 {
604 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
605
606 i2c_del_adapter(&gi2c->adap);
607 pm_runtime_disable(gi2c->se.dev);
608 return 0;
609 }
610
611 static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
612 {
613 int ret;
614 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
615
616 disable_irq(gi2c->irq);
617 ret = geni_se_resources_off(&gi2c->se);
618 if (ret) {
619 enable_irq(gi2c->irq);
620 return ret;
621
622 } else {
623 gi2c->suspended = 1;
624 }
625
626 return 0;
627 }
628
629 static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
630 {
631 int ret;
632 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
633
634 ret = geni_se_resources_on(&gi2c->se);
635 if (ret)
636 return ret;
637
638 enable_irq(gi2c->irq);
639 gi2c->suspended = 0;
640 return 0;
641 }
642
643 static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev)
644 {
645 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
646
647 if (!gi2c->suspended) {
648 geni_i2c_runtime_suspend(dev);
649 pm_runtime_disable(dev);
650 pm_runtime_set_suspended(dev);
651 pm_runtime_enable(dev);
652 }
653 return 0;
654 }
655
656 static const struct dev_pm_ops geni_i2c_pm_ops = {
657 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, NULL)
658 SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume,
659 NULL)
660 };
661
662 static const struct of_device_id geni_i2c_dt_match[] = {
663 { .compatible = "qcom,geni-i2c" },
664 {}
665 };
666 MODULE_DEVICE_TABLE(of, geni_i2c_dt_match);
667
668 static struct platform_driver geni_i2c_driver = {
669 .probe = geni_i2c_probe,
670 .remove = geni_i2c_remove,
671 .driver = {
672 .name = "geni_i2c",
673 .pm = &geni_i2c_pm_ops,
674 .of_match_table = geni_i2c_dt_match,
675 .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match),
676 },
677 };
678
679 module_platform_driver(geni_i2c_driver);
680
681 MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores");
682 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support