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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-tegra.c
blob4c4d17ddc96b964125f89b49c13dd1f44f8bc457
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * drivers/i2c/busses/i2c-tegra.c
4 *
5 * Copyright (C) 2010 Google, Inc.
6 * Author: Colin Cross <ccross@android.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/err.h>
14 #include <linux/i2c.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/iopoll.h>
19 #include <linux/irq.h>
20 #include <linux/kernel.h>
21 #include <linux/ktime.h>
22 #include <linux/module.h>
23 #include <linux/of_device.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/reset.h>
28
29 #define BYTES_PER_FIFO_WORD 4
30
31 #define I2C_CNFG 0x000
32 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
33 #define I2C_CNFG_PACKET_MODE_EN BIT(10)
34 #define I2C_CNFG_NEW_MASTER_FSM BIT(11)
35 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17)
36 #define I2C_STATUS 0x01C
37 #define I2C_SL_CNFG 0x020
38 #define I2C_SL_CNFG_NACK BIT(1)
39 #define I2C_SL_CNFG_NEWSL BIT(2)
40 #define I2C_SL_ADDR1 0x02c
41 #define I2C_SL_ADDR2 0x030
42 #define I2C_TX_FIFO 0x050
43 #define I2C_RX_FIFO 0x054
44 #define I2C_PACKET_TRANSFER_STATUS 0x058
45 #define I2C_FIFO_CONTROL 0x05c
46 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1)
47 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0)
48 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
49 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
50 #define I2C_FIFO_STATUS 0x060
51 #define I2C_FIFO_STATUS_TX_MASK 0xF0
52 #define I2C_FIFO_STATUS_TX_SHIFT 4
53 #define I2C_FIFO_STATUS_RX_MASK 0x0F
54 #define I2C_FIFO_STATUS_RX_SHIFT 0
55 #define I2C_INT_MASK 0x064
56 #define I2C_INT_STATUS 0x068
57 #define I2C_INT_BUS_CLR_DONE BIT(11)
58 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7)
59 #define I2C_INT_NO_ACK BIT(3)
60 #define I2C_INT_ARBITRATION_LOST BIT(2)
61 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1)
62 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0)
63 #define I2C_CLK_DIVISOR 0x06c
64 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16
65
66 #define DVC_CTRL_REG1 0x000
67 #define DVC_CTRL_REG1_INTR_EN BIT(10)
68 #define DVC_CTRL_REG3 0x008
69 #define DVC_CTRL_REG3_SW_PROG BIT(26)
70 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30)
71 #define DVC_STATUS 0x00c
72 #define DVC_STATUS_I2C_DONE_INTR BIT(30)
73
74 #define I2C_ERR_NONE 0x00
75 #define I2C_ERR_NO_ACK BIT(0)
76 #define I2C_ERR_ARBITRATION_LOST BIT(1)
77 #define I2C_ERR_UNKNOWN_INTERRUPT BIT(2)
78 #define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3)
79
80 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
81 #define PACKET_HEADER0_PACKET_ID_SHIFT 16
82 #define PACKET_HEADER0_CONT_ID_SHIFT 12
83 #define PACKET_HEADER0_PROTOCOL_I2C BIT(4)
84
85 #define I2C_HEADER_CONT_ON_NAK BIT(21)
86 #define I2C_HEADER_READ BIT(19)
87 #define I2C_HEADER_10BIT_ADDR BIT(18)
88 #define I2C_HEADER_IE_ENABLE BIT(17)
89 #define I2C_HEADER_REPEAT_START BIT(16)
90 #define I2C_HEADER_CONTINUE_XFER BIT(15)
91 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
92
93 #define I2C_BUS_CLEAR_CNFG 0x084
94 #define I2C_BC_SCLK_THRESHOLD 9
95 #define I2C_BC_SCLK_THRESHOLD_SHIFT 16
96 #define I2C_BC_STOP_COND BIT(2)
97 #define I2C_BC_TERMINATE BIT(1)
98 #define I2C_BC_ENABLE BIT(0)
99 #define I2C_BUS_CLEAR_STATUS 0x088
100 #define I2C_BC_STATUS BIT(0)
101
102 #define I2C_CONFIG_LOAD 0x08C
103 #define I2C_MSTR_CONFIG_LOAD BIT(0)
104
105 #define I2C_CLKEN_OVERRIDE 0x090
106 #define I2C_MST_CORE_CLKEN_OVR BIT(0)
107
108 #define I2C_CONFIG_LOAD_TIMEOUT 1000000
109
110 #define I2C_MST_FIFO_CONTROL 0x0b4
111 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0)
112 #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1)
113 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
114 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
115
116 #define I2C_MST_FIFO_STATUS 0x0b8
117 #define I2C_MST_FIFO_STATUS_RX_MASK 0xff
118 #define I2C_MST_FIFO_STATUS_RX_SHIFT 0
119 #define I2C_MST_FIFO_STATUS_TX_MASK 0xff0000
120 #define I2C_MST_FIFO_STATUS_TX_SHIFT 16
121
122 #define I2C_INTERFACE_TIMING_0 0x94
123 #define I2C_THIGH_SHIFT 8
124 #define I2C_INTERFACE_TIMING_1 0x98
125
126 /* Packet header size in bytes */
127 #define I2C_PACKET_HEADER_SIZE 12
128
129 /*
130 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to
131 * avoid DMA overhead, otherwise external APB DMA controller will be used.
132 * Note that the actual MAX PIO length is 20 bytes because 32 bytes include
133 * I2C_PACKET_HEADER_SIZE.
134 */
135 #define I2C_PIO_MODE_PREFERRED_LEN 32
136
137 /*
138 * msg_end_type: The bus control which need to be send at end of transfer.
139 * @MSG_END_STOP: Send stop pulse at end of transfer.
140 * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
141 * @MSG_END_CONTINUE: The following on message is coming and so do not send
142 * stop or repeat start.
143 */
144 enum msg_end_type {
145 MSG_END_STOP,
146 MSG_END_REPEAT_START,
147 MSG_END_CONTINUE,
148 };
149
150 /**
151 * struct tegra_i2c_hw_feature : Different HW support on Tegra
152 * @has_continue_xfer_support: Continue transfer supports.
153 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
154 * complete interrupt per packet basis.
155 * @has_single_clk_source: The I2C controller has single clock source. Tegra30
156 * and earlier SoCs have two clock sources i.e. div-clk and
157 * fast-clk.
158 * @has_config_load_reg: Has the config load register to load the new
159 * configuration.
160 * @clk_divisor_hs_mode: Clock divisor in HS mode.
161 * @clk_divisor_std_mode: Clock divisor in standard mode. It is
162 * applicable if there is no fast clock source i.e. single clock
163 * source.
164 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
165 * applicable if there is no fast clock source i.e. single clock
166 * source.
167 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
168 * applicable if there is no fast clock source (i.e. single
169 * clock source).
170 * @has_multi_master_mode: The I2C controller supports running in single-master
171 * or multi-master mode.
172 * @has_slcg_override_reg: The I2C controller supports a register that
173 * overrides the second level clock gating.
174 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
175 * provides additional features and allows for longer messages to
176 * be transferred in one go.
177 * @quirks: i2c adapter quirks for limiting write/read transfer size and not
178 * allowing 0 length transfers.
179 * @supports_bus_clear: Bus Clear support to recover from bus hang during
180 * SDA stuck low from device for some unknown reasons.
181 * @has_apb_dma: Support of APBDMA on corresponding Tegra chip.
182 * @tlow_std_mode: Low period of the clock in standard mode.
183 * @thigh_std_mode: High period of the clock in standard mode.
184 * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes.
185 * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes.
186 * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions
187 * in standard mode.
188 * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop
189 * conditions in fast/fast-plus modes.
190 * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions
191 * in HS mode.
192 * @has_interface_timing_reg: Has interface timing register to program the tuned
193 * timing settings.
194 */
195 struct tegra_i2c_hw_feature {
196 bool has_continue_xfer_support;
197 bool has_per_pkt_xfer_complete_irq;
198 bool has_single_clk_source;
199 bool has_config_load_reg;
200 int clk_divisor_hs_mode;
201 int clk_divisor_std_mode;
202 int clk_divisor_fast_mode;
203 u16 clk_divisor_fast_plus_mode;
204 bool has_multi_master_mode;
205 bool has_slcg_override_reg;
206 bool has_mst_fifo;
207 const struct i2c_adapter_quirks *quirks;
208 bool supports_bus_clear;
209 bool has_apb_dma;
210 u8 tlow_std_mode;
211 u8 thigh_std_mode;
212 u8 tlow_fast_fastplus_mode;
213 u8 thigh_fast_fastplus_mode;
214 u32 setup_hold_time_std_mode;
215 u32 setup_hold_time_fast_fast_plus_mode;
216 u32 setup_hold_time_hs_mode;
217 bool has_interface_timing_reg;
218 };
219
220 /**
221 * struct tegra_i2c_dev - per device I2C context
222 * @dev: device reference for power management
223 * @hw: Tegra I2C HW feature
224 * @adapter: core I2C layer adapter information
225 * @div_clk: clock reference for div clock of I2C controller
226 * @fast_clk: clock reference for fast clock of I2C controller
227 * @rst: reset control for the I2C controller
228 * @base: ioremapped registers cookie
229 * @base_phys: physical base address of the I2C controller
230 * @cont_id: I2C controller ID, used for packet header
231 * @irq: IRQ number of transfer complete interrupt
232 * @is_dvc: identifies the DVC I2C controller, has a different register layout
233 * @msg_complete: transfer completion notifier
234 * @msg_err: error code for completed message
235 * @msg_buf: pointer to current message data
236 * @msg_buf_remaining: size of unsent data in the message buffer
237 * @msg_read: identifies read transfers
238 * @bus_clk_rate: current I2C bus clock rate
239 * @clk_divisor_non_hs_mode: clock divider for non-high-speed modes
240 * @is_multimaster_mode: track if I2C controller is in multi-master mode
241 * @tx_dma_chan: DMA transmit channel
242 * @rx_dma_chan: DMA receive channel
243 * @dma_phys: handle to DMA resources
244 * @dma_buf: pointer to allocated DMA buffer
245 * @dma_buf_size: DMA buffer size
246 * @is_curr_dma_xfer: indicates active DMA transfer
247 * @dma_complete: DMA completion notifier
248 * @is_curr_atomic_xfer: indicates active atomic transfer
249 */
250 struct tegra_i2c_dev {
251 struct device *dev;
252 const struct tegra_i2c_hw_feature *hw;
253 struct i2c_adapter adapter;
254 struct clk *div_clk;
255 struct clk *fast_clk;
256 struct reset_control *rst;
257 void __iomem *base;
258 phys_addr_t base_phys;
259 int cont_id;
260 int irq;
261 int is_dvc;
262 struct completion msg_complete;
263 int msg_err;
264 u8 *msg_buf;
265 size_t msg_buf_remaining;
266 int msg_read;
267 u32 bus_clk_rate;
268 u16 clk_divisor_non_hs_mode;
269 bool is_multimaster_mode;
270 struct dma_chan *tx_dma_chan;
271 struct dma_chan *rx_dma_chan;
272 dma_addr_t dma_phys;
273 u32 *dma_buf;
274 unsigned int dma_buf_size;
275 bool is_curr_dma_xfer;
276 struct completion dma_complete;
277 bool is_curr_atomic_xfer;
278 };
279
280 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
281 unsigned long reg)
282 {
283 writel_relaxed(val, i2c_dev->base + reg);
284 }
285
286 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
287 {
288 return readl_relaxed(i2c_dev->base + reg);
289 }
290
291 /*
292 * i2c_writel and i2c_readl will offset the register if necessary to talk
293 * to the I2C block inside the DVC block
294 */
295 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
296 unsigned long reg)
297 {
298 if (i2c_dev->is_dvc)
299 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
300 return reg;
301 }
302
303 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
304 unsigned long reg)
305 {
306 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
307
308 /* Read back register to make sure that register writes completed */
309 if (reg != I2C_TX_FIFO)
310 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
311 }
312
313 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
314 {
315 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
316 }
317
318 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
319 unsigned long reg, int len)
320 {
321 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
322 }
323
324 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
325 unsigned long reg, int len)
326 {
327 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
328 }
329
330 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
331 {
332 u32 int_mask;
333
334 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
335 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
336 }
337
338 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
339 {
340 u32 int_mask;
341
342 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
343 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
344 }
345
346 static void tegra_i2c_dma_complete(void *args)
347 {
348 struct tegra_i2c_dev *i2c_dev = args;
349
350 complete(&i2c_dev->dma_complete);
351 }
352
353 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len)
354 {
355 struct dma_async_tx_descriptor *dma_desc;
356 enum dma_transfer_direction dir;
357 struct dma_chan *chan;
358
359 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len);
360 reinit_completion(&i2c_dev->dma_complete);
361 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
362 chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan;
363 dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys,
364 len, dir, DMA_PREP_INTERRUPT |
365 DMA_CTRL_ACK);
366 if (!dma_desc) {
367 dev_err(i2c_dev->dev, "failed to get DMA descriptor\n");
368 return -EINVAL;
369 }
370
371 dma_desc->callback = tegra_i2c_dma_complete;
372 dma_desc->callback_param = i2c_dev;
373 dmaengine_submit(dma_desc);
374 dma_async_issue_pending(chan);
375 return 0;
376 }
377
378 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
379 {
380 if (i2c_dev->dma_buf) {
381 dma_free_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
382 i2c_dev->dma_buf, i2c_dev->dma_phys);
383 i2c_dev->dma_buf = NULL;
384 }
385
386 if (i2c_dev->tx_dma_chan) {
387 dma_release_channel(i2c_dev->tx_dma_chan);
388 i2c_dev->tx_dma_chan = NULL;
389 }
390
391 if (i2c_dev->rx_dma_chan) {
392 dma_release_channel(i2c_dev->rx_dma_chan);
393 i2c_dev->rx_dma_chan = NULL;
394 }
395 }
396
397 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
398 {
399 struct dma_chan *chan;
400 u32 *dma_buf;
401 dma_addr_t dma_phys;
402 int err;
403
404 if (!i2c_dev->hw->has_apb_dma)
405 return 0;
406
407 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) {
408 dev_dbg(i2c_dev->dev, "Support for APB DMA not enabled!\n");
409 return 0;
410 }
411
412 chan = dma_request_chan(i2c_dev->dev, "rx");
413 if (IS_ERR(chan)) {
414 err = PTR_ERR(chan);
415 goto err_out;
416 }
417
418 i2c_dev->rx_dma_chan = chan;
419
420 chan = dma_request_chan(i2c_dev->dev, "tx");
421 if (IS_ERR(chan)) {
422 err = PTR_ERR(chan);
423 goto err_out;
424 }
425
426 i2c_dev->tx_dma_chan = chan;
427
428 dma_buf = dma_alloc_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
429 &dma_phys, GFP_KERNEL | __GFP_NOWARN);
430 if (!dma_buf) {
431 dev_err(i2c_dev->dev, "failed to allocate the DMA buffer\n");
432 err = -ENOMEM;
433 goto err_out;
434 }
435
436 i2c_dev->dma_buf = dma_buf;
437 i2c_dev->dma_phys = dma_phys;
438 return 0;
439
440 err_out:
441 tegra_i2c_release_dma(i2c_dev);
442 if (err != -EPROBE_DEFER) {
443 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err);
444 dev_err(i2c_dev->dev, "falling back to PIO\n");
445 return 0;
446 }
447
448 return err;
449 }
450
451 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
452 {
453 unsigned long timeout = jiffies + HZ;
454 unsigned int offset;
455 u32 mask, val;
456
457 if (i2c_dev->hw->has_mst_fifo) {
458 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
459 I2C_MST_FIFO_CONTROL_RX_FLUSH;
460 offset = I2C_MST_FIFO_CONTROL;
461 } else {
462 mask = I2C_FIFO_CONTROL_TX_FLUSH |
463 I2C_FIFO_CONTROL_RX_FLUSH;
464 offset = I2C_FIFO_CONTROL;
465 }
466
467 val = i2c_readl(i2c_dev, offset);
468 val |= mask;
469 i2c_writel(i2c_dev, val, offset);
470
471 while (i2c_readl(i2c_dev, offset) & mask) {
472 if (time_after(jiffies, timeout)) {
473 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
474 return -ETIMEDOUT;
475 }
476 usleep_range(1000, 2000);
477 }
478 return 0;
479 }
480
481 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
482 {
483 u32 val;
484 int rx_fifo_avail;
485 u8 *buf = i2c_dev->msg_buf;
486 size_t buf_remaining = i2c_dev->msg_buf_remaining;
487 int words_to_transfer;
488
489 /*
490 * Catch overflow due to message fully sent
491 * before the check for RX FIFO availability.
492 */
493 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining)))
494 return -EINVAL;
495
496 if (i2c_dev->hw->has_mst_fifo) {
497 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
498 rx_fifo_avail = (val & I2C_MST_FIFO_STATUS_RX_MASK) >>
499 I2C_MST_FIFO_STATUS_RX_SHIFT;
500 } else {
501 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
502 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
503 I2C_FIFO_STATUS_RX_SHIFT;
504 }
505
506 /* Rounds down to not include partial word at the end of buf */
507 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
508 if (words_to_transfer > rx_fifo_avail)
509 words_to_transfer = rx_fifo_avail;
510
511 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
512
513 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
514 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
515 rx_fifo_avail -= words_to_transfer;
516
517 /*
518 * If there is a partial word at the end of buf, handle it manually to
519 * prevent overwriting past the end of buf
520 */
521 if (rx_fifo_avail > 0 && buf_remaining > 0) {
522 /*
523 * buf_remaining > 3 check not needed as rx_fifo_avail == 0
524 * when (words_to_transfer was > rx_fifo_avail) earlier
525 * in this function.
526 */
527 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
528 val = cpu_to_le32(val);
529 memcpy(buf, &val, buf_remaining);
530 buf_remaining = 0;
531 rx_fifo_avail--;
532 }
533
534 /* RX FIFO must be drained, otherwise it's an Overflow case. */
535 if (WARN_ON_ONCE(rx_fifo_avail))
536 return -EINVAL;
537
538 i2c_dev->msg_buf_remaining = buf_remaining;
539 i2c_dev->msg_buf = buf;
540
541 return 0;
542 }
543
544 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
545 {
546 u32 val;
547 int tx_fifo_avail;
548 u8 *buf = i2c_dev->msg_buf;
549 size_t buf_remaining = i2c_dev->msg_buf_remaining;
550 int words_to_transfer;
551
552 if (i2c_dev->hw->has_mst_fifo) {
553 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
554 tx_fifo_avail = (val & I2C_MST_FIFO_STATUS_TX_MASK) >>
555 I2C_MST_FIFO_STATUS_TX_SHIFT;
556 } else {
557 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
558 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
559 I2C_FIFO_STATUS_TX_SHIFT;
560 }
561
562 /* Rounds down to not include partial word at the end of buf */
563 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
564
565 /* It's very common to have < 4 bytes, so optimize that case. */
566 if (words_to_transfer) {
567 if (words_to_transfer > tx_fifo_avail)
568 words_to_transfer = tx_fifo_avail;
569
570 /*
571 * Update state before writing to FIFO. If this casues us
572 * to finish writing all bytes (AKA buf_remaining goes to 0) we
573 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
574 * not maskable). We need to make sure that the isr sees
575 * buf_remaining as 0 and doesn't call us back re-entrantly.
576 */
577 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
578 tx_fifo_avail -= words_to_transfer;
579 i2c_dev->msg_buf_remaining = buf_remaining;
580 i2c_dev->msg_buf = buf +
581 words_to_transfer * BYTES_PER_FIFO_WORD;
582 barrier();
583
584 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
585
586 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
587 }
588
589 /*
590 * If there is a partial word at the end of buf, handle it manually to
591 * prevent reading past the end of buf, which could cross a page
592 * boundary and fault.
593 */
594 if (tx_fifo_avail > 0 && buf_remaining > 0) {
595 /*
596 * buf_remaining > 3 check not needed as tx_fifo_avail == 0
597 * when (words_to_transfer was > tx_fifo_avail) earlier
598 * in this function for non-zero words_to_transfer.
599 */
600 memcpy(&val, buf, buf_remaining);
601 val = le32_to_cpu(val);
602
603 /* Again update before writing to FIFO to make sure isr sees. */
604 i2c_dev->msg_buf_remaining = 0;
605 i2c_dev->msg_buf = NULL;
606 barrier();
607
608 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
609 }
610
611 return 0;
612 }
613
614 /*
615 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
616 * block. This block is identical to the rest of the I2C blocks, except that
617 * it only supports master mode, it has registers moved around, and it needs
618 * some extra init to get it into I2C mode. The register moves are handled
619 * by i2c_readl and i2c_writel
620 */
621 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
622 {
623 u32 val;
624
625 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
626 val |= DVC_CTRL_REG3_SW_PROG;
627 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
628 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
629
630 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
631 val |= DVC_CTRL_REG1_INTR_EN;
632 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
633 }
634
635 static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev)
636 {
637 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
638 int ret;
639
640 ret = pinctrl_pm_select_default_state(i2c_dev->dev);
641 if (ret)
642 return ret;
643
644 if (!i2c_dev->hw->has_single_clk_source) {
645 ret = clk_enable(i2c_dev->fast_clk);
646 if (ret < 0) {
647 dev_err(i2c_dev->dev,
648 "Enabling fast clk failed, err %d\n", ret);
649 return ret;
650 }
651 }
652
653 ret = clk_enable(i2c_dev->div_clk);
654 if (ret < 0) {
655 dev_err(i2c_dev->dev,
656 "Enabling div clk failed, err %d\n", ret);
657 clk_disable(i2c_dev->fast_clk);
658 return ret;
659 }
660
661 return 0;
662 }
663
664 static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev)
665 {
666 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
667
668 clk_disable(i2c_dev->div_clk);
669 if (!i2c_dev->hw->has_single_clk_source)
670 clk_disable(i2c_dev->fast_clk);
671
672 return pinctrl_pm_select_idle_state(i2c_dev->dev);
673 }
674
675 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
676 {
677 unsigned long reg_offset;
678 void __iomem *addr;
679 u32 val;
680 int err;
681
682 if (i2c_dev->hw->has_config_load_reg) {
683 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD);
684 addr = i2c_dev->base + reg_offset;
685 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
686
687 if (i2c_dev->is_curr_atomic_xfer)
688 err = readl_relaxed_poll_timeout_atomic(
689 addr, val, val == 0, 1000,
690 I2C_CONFIG_LOAD_TIMEOUT);
691 else
692 err = readl_relaxed_poll_timeout(
693 addr, val, val == 0, 1000,
694 I2C_CONFIG_LOAD_TIMEOUT);
695
696 if (err) {
697 dev_warn(i2c_dev->dev,
698 "timeout waiting for config load\n");
699 return err;
700 }
701 }
702
703 return 0;
704 }
705
706 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit)
707 {
708 u32 val;
709 int err;
710 u32 clk_divisor, clk_multiplier;
711 u32 tsu_thd;
712 u8 tlow, thigh;
713
714 reset_control_assert(i2c_dev->rst);
715 udelay(2);
716 reset_control_deassert(i2c_dev->rst);
717
718 if (i2c_dev->is_dvc)
719 tegra_dvc_init(i2c_dev);
720
721 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
722 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
723
724 if (i2c_dev->hw->has_multi_master_mode)
725 val |= I2C_CNFG_MULTI_MASTER_MODE;
726
727 i2c_writel(i2c_dev, val, I2C_CNFG);
728 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
729
730 /* Make sure clock divisor programmed correctly */
731 clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
732 clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<
733 I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
734 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
735
736 if (i2c_dev->bus_clk_rate > I2C_MAX_STANDARD_MODE_FREQ &&
737 i2c_dev->bus_clk_rate <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
738 tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
739 thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
740 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
741 } else {
742 tlow = i2c_dev->hw->tlow_std_mode;
743 thigh = i2c_dev->hw->thigh_std_mode;
744 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
745 }
746
747 if (i2c_dev->hw->has_interface_timing_reg) {
748 val = (thigh << I2C_THIGH_SHIFT) | tlow;
749 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
750 }
751
752 /*
753 * configure setup and hold times only when tsu_thd is non-zero.
754 * otherwise, preserve the chip default values
755 */
756 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
757 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
758
759 if (!clk_reinit) {
760 clk_multiplier = (tlow + thigh + 2);
761 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
762 err = clk_set_rate(i2c_dev->div_clk,
763 i2c_dev->bus_clk_rate * clk_multiplier);
764 if (err) {
765 dev_err(i2c_dev->dev,
766 "failed changing clock rate: %d\n", err);
767 return err;
768 }
769 }
770
771 if (!i2c_dev->is_dvc) {
772 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
773
774 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
775 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
776 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
777 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
778 }
779
780 err = tegra_i2c_flush_fifos(i2c_dev);
781 if (err)
782 return err;
783
784 if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
785 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
786
787 err = tegra_i2c_wait_for_config_load(i2c_dev);
788 if (err)
789 return err;
790
791 return 0;
792 }
793
794 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
795 {
796 u32 cnfg;
797
798 /*
799 * NACK interrupt is generated before the I2C controller generates
800 * the STOP condition on the bus. So wait for 2 clock periods
801 * before disabling the controller so that the STOP condition has
802 * been delivered properly.
803 */
804 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
805
806 cnfg = i2c_readl(i2c_dev, I2C_CNFG);
807 if (cnfg & I2C_CNFG_PACKET_MODE_EN)
808 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
809
810 return tegra_i2c_wait_for_config_load(i2c_dev);
811 }
812
813 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
814 {
815 u32 status;
816 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
817 struct tegra_i2c_dev *i2c_dev = dev_id;
818
819 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
820
821 if (status == 0) {
822 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
823 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
824 i2c_readl(i2c_dev, I2C_STATUS),
825 i2c_readl(i2c_dev, I2C_CNFG));
826 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
827 goto err;
828 }
829
830 if (unlikely(status & status_err)) {
831 tegra_i2c_disable_packet_mode(i2c_dev);
832 if (status & I2C_INT_NO_ACK)
833 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
834 if (status & I2C_INT_ARBITRATION_LOST)
835 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
836 goto err;
837 }
838
839 /*
840 * I2C transfer is terminated during the bus clear so skip
841 * processing the other interrupts.
842 */
843 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE))
844 goto err;
845
846 if (!i2c_dev->is_curr_dma_xfer) {
847 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
848 if (tegra_i2c_empty_rx_fifo(i2c_dev)) {
849 /*
850 * Overflow error condition: message fully sent,
851 * with no XFER_COMPLETE interrupt but hardware
852 * asks to transfer more.
853 */
854 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW;
855 goto err;
856 }
857 }
858
859 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
860 if (i2c_dev->msg_buf_remaining)
861 tegra_i2c_fill_tx_fifo(i2c_dev);
862 else
863 tegra_i2c_mask_irq(i2c_dev,
864 I2C_INT_TX_FIFO_DATA_REQ);
865 }
866 }
867
868 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
869 if (i2c_dev->is_dvc)
870 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
871
872 /*
873 * During message read XFER_COMPLETE interrupt is triggered prior to
874 * DMA completion and during message write XFER_COMPLETE interrupt is
875 * triggered after DMA completion.
876 * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer.
877 * so forcing msg_buf_remaining to 0 in DMA mode.
878 */
879 if (status & I2C_INT_PACKET_XFER_COMPLETE) {
880 if (i2c_dev->is_curr_dma_xfer)
881 i2c_dev->msg_buf_remaining = 0;
882 /*
883 * Underflow error condition: XFER_COMPLETE before message
884 * fully sent.
885 */
886 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) {
887 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
888 goto err;
889 }
890 complete(&i2c_dev->msg_complete);
891 }
892 goto done;
893 err:
894 /* An error occurred, mask all interrupts */
895 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
896 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
897 I2C_INT_RX_FIFO_DATA_REQ);
898 if (i2c_dev->hw->supports_bus_clear)
899 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
900 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
901 if (i2c_dev->is_dvc)
902 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
903
904 if (i2c_dev->is_curr_dma_xfer) {
905 if (i2c_dev->msg_read)
906 dmaengine_terminate_async(i2c_dev->rx_dma_chan);
907 else
908 dmaengine_terminate_async(i2c_dev->tx_dma_chan);
909
910 complete(&i2c_dev->dma_complete);
911 }
912
913 complete(&i2c_dev->msg_complete);
914 done:
915 return IRQ_HANDLED;
916 }
917
918 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev,
919 size_t len)
920 {
921 u32 val, reg;
922 u8 dma_burst;
923 struct dma_slave_config slv_config = {0};
924 struct dma_chan *chan;
925 int ret;
926 unsigned long reg_offset;
927
928 if (i2c_dev->hw->has_mst_fifo)
929 reg = I2C_MST_FIFO_CONTROL;
930 else
931 reg = I2C_FIFO_CONTROL;
932
933 if (i2c_dev->is_curr_dma_xfer) {
934 if (len & 0xF)
935 dma_burst = 1;
936 else if (len & 0x10)
937 dma_burst = 4;
938 else
939 dma_burst = 8;
940
941 if (i2c_dev->msg_read) {
942 chan = i2c_dev->rx_dma_chan;
943 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO);
944 slv_config.src_addr = i2c_dev->base_phys + reg_offset;
945 slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
946 slv_config.src_maxburst = dma_burst;
947
948 if (i2c_dev->hw->has_mst_fifo)
949 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst);
950 else
951 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst);
952 } else {
953 chan = i2c_dev->tx_dma_chan;
954 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);
955 slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
956 slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
957 slv_config.dst_maxburst = dma_burst;
958
959 if (i2c_dev->hw->has_mst_fifo)
960 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst);
961 else
962 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst);
963 }
964
965 slv_config.device_fc = true;
966 ret = dmaengine_slave_config(chan, &slv_config);
967 if (ret < 0) {
968 dev_err(i2c_dev->dev, "DMA slave config failed: %d\n",
969 ret);
970 dev_err(i2c_dev->dev, "falling back to PIO\n");
971 tegra_i2c_release_dma(i2c_dev);
972 i2c_dev->is_curr_dma_xfer = false;
973 } else {
974 goto out;
975 }
976 }
977
978 if (i2c_dev->hw->has_mst_fifo)
979 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
980 I2C_MST_FIFO_CONTROL_RX_TRIG(1);
981 else
982 val = I2C_FIFO_CONTROL_TX_TRIG(8) |
983 I2C_FIFO_CONTROL_RX_TRIG(1);
984 out:
985 i2c_writel(i2c_dev, val, reg);
986 }
987
988 static unsigned long
989 tegra_i2c_poll_completion_timeout(struct tegra_i2c_dev *i2c_dev,
990 struct completion *complete,
991 unsigned int timeout_ms)
992 {
993 ktime_t ktime = ktime_get();
994 ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms);
995
996 do {
997 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
998
999 if (status) {
1000 tegra_i2c_isr(i2c_dev->irq, i2c_dev);
1001
1002 if (completion_done(complete)) {
1003 s64 delta = ktime_ms_delta(ktimeout, ktime);
1004
1005 return msecs_to_jiffies(delta) ?: 1;
1006 }
1007 }
1008
1009 ktime = ktime_get();
1010
1011 } while (ktime_before(ktime, ktimeout));
1012
1013 return 0;
1014 }
1015
1016 static unsigned long
1017 tegra_i2c_wait_completion_timeout(struct tegra_i2c_dev *i2c_dev,
1018 struct completion *complete,
1019 unsigned int timeout_ms)
1020 {
1021 unsigned long ret;
1022
1023 if (i2c_dev->is_curr_atomic_xfer) {
1024 ret = tegra_i2c_poll_completion_timeout(i2c_dev, complete,
1025 timeout_ms);
1026 } else {
1027 enable_irq(i2c_dev->irq);
1028 ret = wait_for_completion_timeout(complete,
1029 msecs_to_jiffies(timeout_ms));
1030 disable_irq(i2c_dev->irq);
1031
1032 /*
1033 * There is a chance that completion may happen after IRQ
1034 * synchronization, which is done by disable_irq().
1035 */
1036 if (ret == 0 && completion_done(complete)) {
1037 dev_warn(i2c_dev->dev,
1038 "completion done after timeout\n");
1039 ret = 1;
1040 }
1041 }
1042
1043 return ret;
1044 }
1045
1046 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap)
1047 {
1048 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1049 int err;
1050 unsigned long time_left;
1051 u32 reg;
1052
1053 reinit_completion(&i2c_dev->msg_complete);
1054 reg = (I2C_BC_SCLK_THRESHOLD << I2C_BC_SCLK_THRESHOLD_SHIFT) |
1055 I2C_BC_STOP_COND | I2C_BC_TERMINATE;
1056 i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG);
1057 if (i2c_dev->hw->has_config_load_reg) {
1058 err = tegra_i2c_wait_for_config_load(i2c_dev);
1059 if (err)
1060 return err;
1061 }
1062
1063 reg |= I2C_BC_ENABLE;
1064 i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG);
1065 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1066
1067 time_left = tegra_i2c_wait_completion_timeout(
1068 i2c_dev, &i2c_dev->msg_complete, 50);
1069 if (time_left == 0) {
1070 dev_err(i2c_dev->dev, "timed out for bus clear\n");
1071 return -ETIMEDOUT;
1072 }
1073
1074 reg = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS);
1075 if (!(reg & I2C_BC_STATUS)) {
1076 dev_err(i2c_dev->dev,
1077 "un-recovered arbitration lost\n");
1078 return -EIO;
1079 }
1080
1081 return -EAGAIN;
1082 }
1083
1084 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
1085 struct i2c_msg *msg,
1086 enum msg_end_type end_state)
1087 {
1088 u32 packet_header;
1089 u32 int_mask;
1090 unsigned long time_left;
1091 size_t xfer_size;
1092 u32 *buffer = NULL;
1093 int err = 0;
1094 bool dma;
1095 u16 xfer_time = 100;
1096
1097 tegra_i2c_flush_fifos(i2c_dev);
1098
1099 i2c_dev->msg_buf = msg->buf;
1100 i2c_dev->msg_buf_remaining = msg->len;
1101 i2c_dev->msg_err = I2C_ERR_NONE;
1102 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
1103 reinit_completion(&i2c_dev->msg_complete);
1104
1105 if (i2c_dev->msg_read)
1106 xfer_size = msg->len;
1107 else
1108 xfer_size = msg->len + I2C_PACKET_HEADER_SIZE;
1109
1110 xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD);
1111 i2c_dev->is_curr_dma_xfer = (xfer_size > I2C_PIO_MODE_PREFERRED_LEN) &&
1112 i2c_dev->dma_buf &&
1113 !i2c_dev->is_curr_atomic_xfer;
1114 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size);
1115 dma = i2c_dev->is_curr_dma_xfer;
1116 /*
1117 * Transfer time in mSec = Total bits / transfer rate
1118 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits
1119 */
1120 xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC,
1121 i2c_dev->bus_clk_rate);
1122
1123 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
1124 tegra_i2c_unmask_irq(i2c_dev, int_mask);
1125 if (dma) {
1126 if (i2c_dev->msg_read) {
1127 dma_sync_single_for_device(i2c_dev->dev,
1128 i2c_dev->dma_phys,
1129 xfer_size,
1130 DMA_FROM_DEVICE);
1131 err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1132 if (err < 0) {
1133 dev_err(i2c_dev->dev,
1134 "starting RX DMA failed, err %d\n",
1135 err);
1136 return err;
1137 }
1138
1139 } else {
1140 dma_sync_single_for_cpu(i2c_dev->dev,
1141 i2c_dev->dma_phys,
1142 xfer_size,
1143 DMA_TO_DEVICE);
1144 buffer = i2c_dev->dma_buf;
1145 }
1146 }
1147
1148 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
1149 PACKET_HEADER0_PROTOCOL_I2C |
1150 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
1151 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
1152 if (dma && !i2c_dev->msg_read)
1153 *buffer++ = packet_header;
1154 else
1155 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1156
1157 packet_header = msg->len - 1;
1158 if (dma && !i2c_dev->msg_read)
1159 *buffer++ = packet_header;
1160 else
1161 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1162
1163 packet_header = I2C_HEADER_IE_ENABLE;
1164 if (end_state == MSG_END_CONTINUE)
1165 packet_header |= I2C_HEADER_CONTINUE_XFER;
1166 else if (end_state == MSG_END_REPEAT_START)
1167 packet_header |= I2C_HEADER_REPEAT_START;
1168 if (msg->flags & I2C_M_TEN) {
1169 packet_header |= msg->addr;
1170 packet_header |= I2C_HEADER_10BIT_ADDR;
1171 } else {
1172 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
1173 }
1174 if (msg->flags & I2C_M_IGNORE_NAK)
1175 packet_header |= I2C_HEADER_CONT_ON_NAK;
1176 if (msg->flags & I2C_M_RD)
1177 packet_header |= I2C_HEADER_READ;
1178 if (dma && !i2c_dev->msg_read)
1179 *buffer++ = packet_header;
1180 else
1181 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1182
1183 if (!i2c_dev->msg_read) {
1184 if (dma) {
1185 memcpy(buffer, msg->buf, msg->len);
1186 dma_sync_single_for_device(i2c_dev->dev,
1187 i2c_dev->dma_phys,
1188 xfer_size,
1189 DMA_TO_DEVICE);
1190 err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1191 if (err < 0) {
1192 dev_err(i2c_dev->dev,
1193 "starting TX DMA failed, err %d\n",
1194 err);
1195 return err;
1196 }
1197 } else {
1198 tegra_i2c_fill_tx_fifo(i2c_dev);
1199 }
1200 }
1201
1202 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
1203 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
1204 if (!dma) {
1205 if (msg->flags & I2C_M_RD)
1206 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
1207 else if (i2c_dev->msg_buf_remaining)
1208 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
1209 }
1210
1211 tegra_i2c_unmask_irq(i2c_dev, int_mask);
1212 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
1213 i2c_readl(i2c_dev, I2C_INT_MASK));
1214
1215 if (dma) {
1216 time_left = tegra_i2c_wait_completion_timeout(
1217 i2c_dev, &i2c_dev->dma_complete, xfer_time);
1218
1219 dmaengine_terminate_sync(i2c_dev->msg_read ?
1220 i2c_dev->rx_dma_chan :
1221 i2c_dev->tx_dma_chan);
1222
1223 if (!time_left && !completion_done(&i2c_dev->dma_complete)) {
1224 dev_err(i2c_dev->dev, "DMA transfer timeout\n");
1225 tegra_i2c_init(i2c_dev, true);
1226 return -ETIMEDOUT;
1227 }
1228
1229 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) {
1230 dma_sync_single_for_cpu(i2c_dev->dev,
1231 i2c_dev->dma_phys,
1232 xfer_size,
1233 DMA_FROM_DEVICE);
1234 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf,
1235 msg->len);
1236 }
1237 }
1238
1239 time_left = tegra_i2c_wait_completion_timeout(
1240 i2c_dev, &i2c_dev->msg_complete, xfer_time);
1241
1242 tegra_i2c_mask_irq(i2c_dev, int_mask);
1243
1244 if (time_left == 0) {
1245 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
1246 tegra_i2c_init(i2c_dev, true);
1247 return -ETIMEDOUT;
1248 }
1249
1250 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
1251 time_left, completion_done(&i2c_dev->msg_complete),
1252 i2c_dev->msg_err);
1253
1254 i2c_dev->is_curr_dma_xfer = false;
1255 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
1256 return 0;
1257
1258 tegra_i2c_init(i2c_dev, true);
1259 /* start recovery upon arbitration loss in single master mode */
1260 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
1261 if (!i2c_dev->is_multimaster_mode)
1262 return i2c_recover_bus(&i2c_dev->adapter);
1263 return -EAGAIN;
1264 }
1265
1266 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
1267 if (msg->flags & I2C_M_IGNORE_NAK)
1268 return 0;
1269 return -EREMOTEIO;
1270 }
1271
1272 return -EIO;
1273 }
1274
1275 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
1276 int num)
1277 {
1278 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1279 int i;
1280 int ret;
1281
1282 ret = pm_runtime_get_sync(i2c_dev->dev);
1283 if (ret < 0) {
1284 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
1285 return ret;
1286 }
1287
1288 for (i = 0; i < num; i++) {
1289 enum msg_end_type end_type = MSG_END_STOP;
1290
1291 if (i < (num - 1)) {
1292 if (msgs[i + 1].flags & I2C_M_NOSTART)
1293 end_type = MSG_END_CONTINUE;
1294 else
1295 end_type = MSG_END_REPEAT_START;
1296 }
1297 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
1298 if (ret)
1299 break;
1300 }
1301
1302 pm_runtime_put(i2c_dev->dev);
1303
1304 return ret ?: i;
1305 }
1306
1307 static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap,
1308 struct i2c_msg msgs[], int num)
1309 {
1310 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1311 int ret;
1312
1313 i2c_dev->is_curr_atomic_xfer = true;
1314 ret = tegra_i2c_xfer(adap, msgs, num);
1315 i2c_dev->is_curr_atomic_xfer = false;
1316
1317 return ret;
1318 }
1319
1320 static u32 tegra_i2c_func(struct i2c_adapter *adap)
1321 {
1322 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1323 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
1324 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
1325
1326 if (i2c_dev->hw->has_continue_xfer_support)
1327 ret |= I2C_FUNC_NOSTART;
1328 return ret;
1329 }
1330
1331 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
1332 {
1333 struct device_node *np = i2c_dev->dev->of_node;
1334 int ret;
1335 bool multi_mode;
1336
1337 ret = of_property_read_u32(np, "clock-frequency",
1338 &i2c_dev->bus_clk_rate);
1339 if (ret)
1340 i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; /* default clock rate */
1341
1342 multi_mode = of_property_read_bool(np, "multi-master");
1343 i2c_dev->is_multimaster_mode = multi_mode;
1344 }
1345
1346 static const struct i2c_algorithm tegra_i2c_algo = {
1347 .master_xfer = tegra_i2c_xfer,
1348 .master_xfer_atomic = tegra_i2c_xfer_atomic,
1349 .functionality = tegra_i2c_func,
1350 };
1351
1352 /* payload size is only 12 bit */
1353 static const struct i2c_adapter_quirks tegra_i2c_quirks = {
1354 .flags = I2C_AQ_NO_ZERO_LEN,
1355 .max_read_len = SZ_4K,
1356 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
1357 };
1358
1359 static const struct i2c_adapter_quirks tegra194_i2c_quirks = {
1360 .flags = I2C_AQ_NO_ZERO_LEN,
1361 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
1362 };
1363
1364 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = {
1365 .recover_bus = tegra_i2c_issue_bus_clear,
1366 };
1367
1368 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
1369 .has_continue_xfer_support = false,
1370 .has_per_pkt_xfer_complete_irq = false,
1371 .has_single_clk_source = false,
1372 .clk_divisor_hs_mode = 3,
1373 .clk_divisor_std_mode = 0,
1374 .clk_divisor_fast_mode = 0,
1375 .clk_divisor_fast_plus_mode = 0,
1376 .has_config_load_reg = false,
1377 .has_multi_master_mode = false,
1378 .has_slcg_override_reg = false,
1379 .has_mst_fifo = false,
1380 .quirks = &tegra_i2c_quirks,
1381 .supports_bus_clear = false,
1382 .has_apb_dma = true,
1383 .tlow_std_mode = 0x4,
1384 .thigh_std_mode = 0x2,
1385 .tlow_fast_fastplus_mode = 0x4,
1386 .thigh_fast_fastplus_mode = 0x2,
1387 .setup_hold_time_std_mode = 0x0,
1388 .setup_hold_time_fast_fast_plus_mode = 0x0,
1389 .setup_hold_time_hs_mode = 0x0,
1390 .has_interface_timing_reg = false,
1391 };
1392
1393 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
1394 .has_continue_xfer_support = true,
1395 .has_per_pkt_xfer_complete_irq = false,
1396 .has_single_clk_source = false,
1397 .clk_divisor_hs_mode = 3,
1398 .clk_divisor_std_mode = 0,
1399 .clk_divisor_fast_mode = 0,
1400 .clk_divisor_fast_plus_mode = 0,
1401 .has_config_load_reg = false,
1402 .has_multi_master_mode = false,
1403 .has_slcg_override_reg = false,
1404 .has_mst_fifo = false,
1405 .quirks = &tegra_i2c_quirks,
1406 .supports_bus_clear = false,
1407 .has_apb_dma = true,
1408 .tlow_std_mode = 0x4,
1409 .thigh_std_mode = 0x2,
1410 .tlow_fast_fastplus_mode = 0x4,
1411 .thigh_fast_fastplus_mode = 0x2,
1412 .setup_hold_time_std_mode = 0x0,
1413 .setup_hold_time_fast_fast_plus_mode = 0x0,
1414 .setup_hold_time_hs_mode = 0x0,
1415 .has_interface_timing_reg = false,
1416 };
1417
1418 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
1419 .has_continue_xfer_support = true,
1420 .has_per_pkt_xfer_complete_irq = true,
1421 .has_single_clk_source = true,
1422 .clk_divisor_hs_mode = 1,
1423 .clk_divisor_std_mode = 0x19,
1424 .clk_divisor_fast_mode = 0x19,
1425 .clk_divisor_fast_plus_mode = 0x10,
1426 .has_config_load_reg = false,
1427 .has_multi_master_mode = false,
1428 .has_slcg_override_reg = false,
1429 .has_mst_fifo = false,
1430 .quirks = &tegra_i2c_quirks,
1431 .supports_bus_clear = true,
1432 .has_apb_dma = true,
1433 .tlow_std_mode = 0x4,
1434 .thigh_std_mode = 0x2,
1435 .tlow_fast_fastplus_mode = 0x4,
1436 .thigh_fast_fastplus_mode = 0x2,
1437 .setup_hold_time_std_mode = 0x0,
1438 .setup_hold_time_fast_fast_plus_mode = 0x0,
1439 .setup_hold_time_hs_mode = 0x0,
1440 .has_interface_timing_reg = false,
1441 };
1442
1443 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
1444 .has_continue_xfer_support = true,
1445 .has_per_pkt_xfer_complete_irq = true,
1446 .has_single_clk_source = true,
1447 .clk_divisor_hs_mode = 1,
1448 .clk_divisor_std_mode = 0x19,
1449 .clk_divisor_fast_mode = 0x19,
1450 .clk_divisor_fast_plus_mode = 0x10,
1451 .has_config_load_reg = true,
1452 .has_multi_master_mode = false,
1453 .has_slcg_override_reg = true,
1454 .has_mst_fifo = false,
1455 .quirks = &tegra_i2c_quirks,
1456 .supports_bus_clear = true,
1457 .has_apb_dma = true,
1458 .tlow_std_mode = 0x4,
1459 .thigh_std_mode = 0x2,
1460 .tlow_fast_fastplus_mode = 0x4,
1461 .thigh_fast_fastplus_mode = 0x2,
1462 .setup_hold_time_std_mode = 0x0,
1463 .setup_hold_time_fast_fast_plus_mode = 0x0,
1464 .setup_hold_time_hs_mode = 0x0,
1465 .has_interface_timing_reg = true,
1466 };
1467
1468 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
1469 .has_continue_xfer_support = true,
1470 .has_per_pkt_xfer_complete_irq = true,
1471 .has_single_clk_source = true,
1472 .clk_divisor_hs_mode = 1,
1473 .clk_divisor_std_mode = 0x19,
1474 .clk_divisor_fast_mode = 0x19,
1475 .clk_divisor_fast_plus_mode = 0x10,
1476 .has_config_load_reg = true,
1477 .has_multi_master_mode = false,
1478 .has_slcg_override_reg = true,
1479 .has_mst_fifo = false,
1480 .quirks = &tegra_i2c_quirks,
1481 .supports_bus_clear = true,
1482 .has_apb_dma = true,
1483 .tlow_std_mode = 0x4,
1484 .thigh_std_mode = 0x2,
1485 .tlow_fast_fastplus_mode = 0x4,
1486 .thigh_fast_fastplus_mode = 0x2,
1487 .setup_hold_time_std_mode = 0,
1488 .setup_hold_time_fast_fast_plus_mode = 0,
1489 .setup_hold_time_hs_mode = 0,
1490 .has_interface_timing_reg = true,
1491 };
1492
1493 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
1494 .has_continue_xfer_support = true,
1495 .has_per_pkt_xfer_complete_irq = true,
1496 .has_single_clk_source = true,
1497 .clk_divisor_hs_mode = 1,
1498 .clk_divisor_std_mode = 0x16,
1499 .clk_divisor_fast_mode = 0x19,
1500 .clk_divisor_fast_plus_mode = 0x10,
1501 .has_config_load_reg = true,
1502 .has_multi_master_mode = false,
1503 .has_slcg_override_reg = true,
1504 .has_mst_fifo = false,
1505 .quirks = &tegra_i2c_quirks,
1506 .supports_bus_clear = true,
1507 .has_apb_dma = false,
1508 .tlow_std_mode = 0x4,
1509 .thigh_std_mode = 0x3,
1510 .tlow_fast_fastplus_mode = 0x4,
1511 .thigh_fast_fastplus_mode = 0x2,
1512 .setup_hold_time_std_mode = 0,
1513 .setup_hold_time_fast_fast_plus_mode = 0,
1514 .setup_hold_time_hs_mode = 0,
1515 .has_interface_timing_reg = true,
1516 };
1517
1518 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
1519 .has_continue_xfer_support = true,
1520 .has_per_pkt_xfer_complete_irq = true,
1521 .has_single_clk_source = true,
1522 .clk_divisor_hs_mode = 1,
1523 .clk_divisor_std_mode = 0x4f,
1524 .clk_divisor_fast_mode = 0x3c,
1525 .clk_divisor_fast_plus_mode = 0x16,
1526 .has_config_load_reg = true,
1527 .has_multi_master_mode = true,
1528 .has_slcg_override_reg = true,
1529 .has_mst_fifo = true,
1530 .quirks = &tegra194_i2c_quirks,
1531 .supports_bus_clear = true,
1532 .has_apb_dma = false,
1533 .tlow_std_mode = 0x8,
1534 .thigh_std_mode = 0x7,
1535 .tlow_fast_fastplus_mode = 0x2,
1536 .thigh_fast_fastplus_mode = 0x2,
1537 .setup_hold_time_std_mode = 0x08080808,
1538 .setup_hold_time_fast_fast_plus_mode = 0x02020202,
1539 .setup_hold_time_hs_mode = 0x090909,
1540 .has_interface_timing_reg = true,
1541 };
1542
1543 /* Match table for of_platform binding */
1544 static const struct of_device_id tegra_i2c_of_match[] = {
1545 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
1546 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
1547 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
1548 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
1549 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
1550 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
1551 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
1552 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
1553 {},
1554 };
1555 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
1556
1557 static int tegra_i2c_probe(struct platform_device *pdev)
1558 {
1559 struct tegra_i2c_dev *i2c_dev;
1560 struct resource *res;
1561 struct clk *div_clk;
1562 struct clk *fast_clk;
1563 void __iomem *base;
1564 phys_addr_t base_phys;
1565 int irq;
1566 int ret;
1567
1568 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1569 base_phys = res->start;
1570 base = devm_ioremap_resource(&pdev->dev, res);
1571 if (IS_ERR(base))
1572 return PTR_ERR(base);
1573
1574 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1575 if (!res) {
1576 dev_err(&pdev->dev, "no irq resource\n");
1577 return -EINVAL;
1578 }
1579 irq = res->start;
1580
1581 div_clk = devm_clk_get(&pdev->dev, "div-clk");
1582 if (IS_ERR(div_clk)) {
1583 if (PTR_ERR(div_clk) != -EPROBE_DEFER)
1584 dev_err(&pdev->dev, "missing controller clock\n");
1585
1586 return PTR_ERR(div_clk);
1587 }
1588
1589 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1590 if (!i2c_dev)
1591 return -ENOMEM;
1592
1593 i2c_dev->base = base;
1594 i2c_dev->base_phys = base_phys;
1595 i2c_dev->div_clk = div_clk;
1596 i2c_dev->adapter.algo = &tegra_i2c_algo;
1597 i2c_dev->adapter.retries = 1;
1598 i2c_dev->adapter.timeout = 6 * HZ;
1599 i2c_dev->irq = irq;
1600 i2c_dev->cont_id = pdev->id;
1601 i2c_dev->dev = &pdev->dev;
1602
1603 i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c");
1604 if (IS_ERR(i2c_dev->rst)) {
1605 dev_err(&pdev->dev, "missing controller reset\n");
1606 return PTR_ERR(i2c_dev->rst);
1607 }
1608
1609 tegra_i2c_parse_dt(i2c_dev);
1610
1611 i2c_dev->hw = of_device_get_match_data(&pdev->dev);
1612 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
1613 "nvidia,tegra20-i2c-dvc");
1614 i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
1615 i2c_dev->dma_buf_size = i2c_dev->adapter.quirks->max_write_len +
1616 I2C_PACKET_HEADER_SIZE;
1617 init_completion(&i2c_dev->msg_complete);
1618 init_completion(&i2c_dev->dma_complete);
1619
1620 if (!i2c_dev->hw->has_single_clk_source) {
1621 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
1622 if (IS_ERR(fast_clk)) {
1623 dev_err(&pdev->dev, "missing fast clock\n");
1624 return PTR_ERR(fast_clk);
1625 }
1626 i2c_dev->fast_clk = fast_clk;
1627 }
1628
1629 platform_set_drvdata(pdev, i2c_dev);
1630
1631 if (!i2c_dev->hw->has_single_clk_source) {
1632 ret = clk_prepare(i2c_dev->fast_clk);
1633 if (ret < 0) {
1634 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
1635 return ret;
1636 }
1637 }
1638
1639 if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ &&
1640 i2c_dev->bus_clk_rate <= I2C_MAX_FAST_MODE_PLUS_FREQ)
1641 i2c_dev->clk_divisor_non_hs_mode =
1642 i2c_dev->hw->clk_divisor_fast_plus_mode;
1643 else if (i2c_dev->bus_clk_rate > I2C_MAX_STANDARD_MODE_FREQ &&
1644 i2c_dev->bus_clk_rate <= I2C_MAX_FAST_MODE_FREQ)
1645 i2c_dev->clk_divisor_non_hs_mode =
1646 i2c_dev->hw->clk_divisor_fast_mode;
1647 else
1648 i2c_dev->clk_divisor_non_hs_mode =
1649 i2c_dev->hw->clk_divisor_std_mode;
1650
1651 ret = clk_prepare(i2c_dev->div_clk);
1652 if (ret < 0) {
1653 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
1654 goto unprepare_fast_clk;
1655 }
1656
1657 pm_runtime_irq_safe(&pdev->dev);
1658 pm_runtime_enable(&pdev->dev);
1659 if (!pm_runtime_enabled(&pdev->dev)) {
1660 ret = tegra_i2c_runtime_resume(&pdev->dev);
1661 if (ret < 0) {
1662 dev_err(&pdev->dev, "runtime resume failed\n");
1663 goto unprepare_div_clk;
1664 }
1665 } else {
1666 ret = pm_runtime_get_sync(i2c_dev->dev);
1667 if (ret < 0) {
1668 dev_err(&pdev->dev, "runtime resume failed\n");
1669 goto disable_rpm;
1670 }
1671 }
1672
1673 if (i2c_dev->is_multimaster_mode) {
1674 ret = clk_enable(i2c_dev->div_clk);
1675 if (ret < 0) {
1676 dev_err(i2c_dev->dev, "div_clk enable failed %d\n",
1677 ret);
1678 goto put_rpm;
1679 }
1680 }
1681
1682 if (i2c_dev->hw->supports_bus_clear)
1683 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
1684
1685 ret = tegra_i2c_init_dma(i2c_dev);
1686 if (ret < 0)
1687 goto disable_div_clk;
1688
1689 ret = tegra_i2c_init(i2c_dev, false);
1690 if (ret) {
1691 dev_err(&pdev->dev, "Failed to initialize i2c controller\n");
1692 goto release_dma;
1693 }
1694
1695 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN);
1696
1697 ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
1698 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
1699 if (ret) {
1700 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
1701 goto release_dma;
1702 }
1703
1704 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
1705 i2c_dev->adapter.owner = THIS_MODULE;
1706 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
1707 strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev),
1708 sizeof(i2c_dev->adapter.name));
1709 i2c_dev->adapter.dev.parent = &pdev->dev;
1710 i2c_dev->adapter.nr = pdev->id;
1711 i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
1712
1713 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
1714 if (ret)
1715 goto release_dma;
1716
1717 pm_runtime_put(&pdev->dev);
1718
1719 return 0;
1720
1721 release_dma:
1722 tegra_i2c_release_dma(i2c_dev);
1723
1724 disable_div_clk:
1725 if (i2c_dev->is_multimaster_mode)
1726 clk_disable(i2c_dev->div_clk);
1727
1728 put_rpm:
1729 if (pm_runtime_enabled(&pdev->dev))
1730 pm_runtime_put_sync(&pdev->dev);
1731 else
1732 tegra_i2c_runtime_suspend(&pdev->dev);
1733
1734 disable_rpm:
1735 if (pm_runtime_enabled(&pdev->dev))
1736 pm_runtime_disable(&pdev->dev);
1737
1738 unprepare_div_clk:
1739 clk_unprepare(i2c_dev->div_clk);
1740
1741 unprepare_fast_clk:
1742 if (!i2c_dev->hw->has_single_clk_source)
1743 clk_unprepare(i2c_dev->fast_clk);
1744
1745 return ret;
1746 }
1747
1748 static int tegra_i2c_remove(struct platform_device *pdev)
1749 {
1750 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1751
1752 i2c_del_adapter(&i2c_dev->adapter);
1753
1754 if (i2c_dev->is_multimaster_mode)
1755 clk_disable(i2c_dev->div_clk);
1756
1757 pm_runtime_disable(&pdev->dev);
1758 if (!pm_runtime_status_suspended(&pdev->dev))
1759 tegra_i2c_runtime_suspend(&pdev->dev);
1760
1761 clk_unprepare(i2c_dev->div_clk);
1762 if (!i2c_dev->hw->has_single_clk_source)
1763 clk_unprepare(i2c_dev->fast_clk);
1764
1765 tegra_i2c_release_dma(i2c_dev);
1766 return 0;
1767 }
1768
1769 static int __maybe_unused tegra_i2c_suspend(struct device *dev)
1770 {
1771 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1772 int err;
1773
1774 i2c_mark_adapter_suspended(&i2c_dev->adapter);
1775
1776 err = pm_runtime_force_suspend(dev);
1777 if (err < 0)
1778 return err;
1779
1780 return 0;
1781 }
1782
1783 static int __maybe_unused tegra_i2c_resume(struct device *dev)
1784 {
1785 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1786 int err;
1787
1788 err = tegra_i2c_runtime_resume(dev);
1789 if (err)
1790 return err;
1791
1792 err = tegra_i2c_init(i2c_dev, false);
1793 if (err)
1794 return err;
1795
1796 err = tegra_i2c_runtime_suspend(dev);
1797 if (err)
1798 return err;
1799
1800 err = pm_runtime_force_resume(dev);
1801 if (err < 0)
1802 return err;
1803
1804 i2c_mark_adapter_resumed(&i2c_dev->adapter);
1805
1806 return 0;
1807 }
1808
1809 static const struct dev_pm_ops tegra_i2c_pm = {
1810 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume)
1811 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
1812 NULL)
1813 };
1814
1815 static struct platform_driver tegra_i2c_driver = {
1816 .probe = tegra_i2c_probe,
1817 .remove = tegra_i2c_remove,
1818 .driver = {
1819 .name = "tegra-i2c",
1820 .of_match_table = tegra_i2c_of_match,
1821 .pm = &tegra_i2c_pm,
1822 },
1823 };
1824
1825 module_platform_driver(tegra_i2c_driver);
1826
1827 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1828 MODULE_AUTHOR("Colin Cross");
1829 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support