?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / infiniband / hw / bnxt_re / ib_verbs.c
blob95f6d493d1b98d909ef37030b4f5c22d68e61a91
1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: IB Verbs interpreter
37 */
38
39 #include <linux/interrupt.h>
40 #include <linux/types.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_ether.h>
44
45 #include <rdma/ib_verbs.h>
46 #include <rdma/ib_user_verbs.h>
47 #include <rdma/ib_umem.h>
48 #include <rdma/ib_addr.h>
49 #include <rdma/ib_mad.h>
50 #include <rdma/ib_cache.h>
51 #include <rdma/uverbs_ioctl.h>
52
53 #include "bnxt_ulp.h"
54
55 #include "roce_hsi.h"
56 #include "qplib_res.h"
57 #include "qplib_sp.h"
58 #include "qplib_fp.h"
59 #include "qplib_rcfw.h"
60
61 #include "bnxt_re.h"
62 #include "ib_verbs.h"
63 #include <rdma/bnxt_re-abi.h>
64
65 static int __from_ib_access_flags(int iflags)
66 {
67 int qflags = 0;
68
69 if (iflags & IB_ACCESS_LOCAL_WRITE)
70 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
71 if (iflags & IB_ACCESS_REMOTE_READ)
72 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ;
73 if (iflags & IB_ACCESS_REMOTE_WRITE)
74 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
75 if (iflags & IB_ACCESS_REMOTE_ATOMIC)
76 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
77 if (iflags & IB_ACCESS_MW_BIND)
78 qflags |= BNXT_QPLIB_ACCESS_MW_BIND;
79 if (iflags & IB_ZERO_BASED)
80 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED;
81 if (iflags & IB_ACCESS_ON_DEMAND)
82 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND;
83 return qflags;
84 };
85
86 static enum ib_access_flags __to_ib_access_flags(int qflags)
87 {
88 enum ib_access_flags iflags = 0;
89
90 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
91 iflags |= IB_ACCESS_LOCAL_WRITE;
92 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
93 iflags |= IB_ACCESS_REMOTE_WRITE;
94 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
95 iflags |= IB_ACCESS_REMOTE_READ;
96 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
97 iflags |= IB_ACCESS_REMOTE_ATOMIC;
98 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
99 iflags |= IB_ACCESS_MW_BIND;
100 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
101 iflags |= IB_ZERO_BASED;
102 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
103 iflags |= IB_ACCESS_ON_DEMAND;
104 return iflags;
105 };
106
107 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
108 struct bnxt_qplib_sge *sg_list, int num)
109 {
110 int i, total = 0;
111
112 for (i = 0; i < num; i++) {
113 sg_list[i].addr = ib_sg_list[i].addr;
114 sg_list[i].lkey = ib_sg_list[i].lkey;
115 sg_list[i].size = ib_sg_list[i].length;
116 total += sg_list[i].size;
117 }
118 return total;
119 }
120
121 /* Device */
122 int bnxt_re_query_device(struct ib_device *ibdev,
123 struct ib_device_attr *ib_attr,
124 struct ib_udata *udata)
125 {
126 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
127 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
128
129 memset(ib_attr, 0, sizeof(*ib_attr));
130 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver,
131 min(sizeof(dev_attr->fw_ver),
132 sizeof(ib_attr->fw_ver)));
133 bnxt_qplib_get_guid(rdev->netdev->dev_addr,
134 (u8 *)&ib_attr->sys_image_guid);
135 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE;
136 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M;
137
138 ib_attr->vendor_id = rdev->en_dev->pdev->vendor;
139 ib_attr->vendor_part_id = rdev->en_dev->pdev->device;
140 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device;
141 ib_attr->max_qp = dev_attr->max_qp;
142 ib_attr->max_qp_wr = dev_attr->max_qp_wqes;
143 ib_attr->device_cap_flags =
144 IB_DEVICE_CURR_QP_STATE_MOD
145 | IB_DEVICE_RC_RNR_NAK_GEN
146 | IB_DEVICE_SHUTDOWN_PORT
147 | IB_DEVICE_SYS_IMAGE_GUID
148 | IB_DEVICE_LOCAL_DMA_LKEY
149 | IB_DEVICE_RESIZE_MAX_WR
150 | IB_DEVICE_PORT_ACTIVE_EVENT
151 | IB_DEVICE_N_NOTIFY_CQ
152 | IB_DEVICE_MEM_WINDOW
153 | IB_DEVICE_MEM_WINDOW_TYPE_2B
154 | IB_DEVICE_MEM_MGT_EXTENSIONS;
155 ib_attr->max_send_sge = dev_attr->max_qp_sges;
156 ib_attr->max_recv_sge = dev_attr->max_qp_sges;
157 ib_attr->max_sge_rd = dev_attr->max_qp_sges;
158 ib_attr->max_cq = dev_attr->max_cq;
159 ib_attr->max_cqe = dev_attr->max_cq_wqes;
160 ib_attr->max_mr = dev_attr->max_mr;
161 ib_attr->max_pd = dev_attr->max_pd;
162 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
163 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;
164 ib_attr->atomic_cap = IB_ATOMIC_NONE;
165 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE;
166
167 ib_attr->max_ee_rd_atom = 0;
168 ib_attr->max_res_rd_atom = 0;
169 ib_attr->max_ee_init_rd_atom = 0;
170 ib_attr->max_ee = 0;
171 ib_attr->max_rdd = 0;
172 ib_attr->max_mw = dev_attr->max_mw;
173 ib_attr->max_raw_ipv6_qp = 0;
174 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp;
175 ib_attr->max_mcast_grp = 0;
176 ib_attr->max_mcast_qp_attach = 0;
177 ib_attr->max_total_mcast_qp_attach = 0;
178 ib_attr->max_ah = dev_attr->max_ah;
179
180 ib_attr->max_fmr = 0;
181 ib_attr->max_map_per_fmr = 0;
182
183 ib_attr->max_srq = dev_attr->max_srq;
184 ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
185 ib_attr->max_srq_sge = dev_attr->max_srq_sges;
186
187 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS;
188
189 ib_attr->max_pkeys = 1;
190 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY;
191 return 0;
192 }
193
194 /* Port */
195 int bnxt_re_query_port(struct ib_device *ibdev, u8 port_num,
196 struct ib_port_attr *port_attr)
197 {
198 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
199 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
200
201 memset(port_attr, 0, sizeof(*port_attr));
202
203 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) {
204 port_attr->state = IB_PORT_ACTIVE;
205 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
206 } else {
207 port_attr->state = IB_PORT_DOWN;
208 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED;
209 }
210 port_attr->max_mtu = IB_MTU_4096;
211 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu);
212 port_attr->gid_tbl_len = dev_attr->max_sgid;
213 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
214 IB_PORT_DEVICE_MGMT_SUP |
215 IB_PORT_VENDOR_CLASS_SUP;
216 port_attr->ip_gids = true;
217
218 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW;
219 port_attr->bad_pkey_cntr = 0;
220 port_attr->qkey_viol_cntr = 0;
221 port_attr->pkey_tbl_len = dev_attr->max_pkey;
222 port_attr->lid = 0;
223 port_attr->sm_lid = 0;
224 port_attr->lmc = 0;
225 port_attr->max_vl_num = 4;
226 port_attr->sm_sl = 0;
227 port_attr->subnet_timeout = 0;
228 port_attr->init_type_reply = 0;
229 port_attr->active_speed = rdev->active_speed;
230 port_attr->active_width = rdev->active_width;
231
232 return 0;
233 }
234
235 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u8 port_num,
236 struct ib_port_immutable *immutable)
237 {
238 struct ib_port_attr port_attr;
239
240 if (bnxt_re_query_port(ibdev, port_num, &port_attr))
241 return -EINVAL;
242
243 immutable->pkey_tbl_len = port_attr.pkey_tbl_len;
244 immutable->gid_tbl_len = port_attr.gid_tbl_len;
245 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
246 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP;
247 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
248 return 0;
249 }
250
251 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str)
252 {
253 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
254
255 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
256 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1],
257 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]);
258 }
259
260 int bnxt_re_query_pkey(struct ib_device *ibdev, u8 port_num,
261 u16 index, u16 *pkey)
262 {
263 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
264
265 /* Ignore port_num */
266
267 memset(pkey, 0, sizeof(*pkey));
268 return bnxt_qplib_get_pkey(&rdev->qplib_res,
269 &rdev->qplib_res.pkey_tbl, index, pkey);
270 }
271
272 int bnxt_re_query_gid(struct ib_device *ibdev, u8 port_num,
273 int index, union ib_gid *gid)
274 {
275 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
276 int rc = 0;
277
278 /* Ignore port_num */
279 memset(gid, 0, sizeof(*gid));
280 rc = bnxt_qplib_get_sgid(&rdev->qplib_res,
281 &rdev->qplib_res.sgid_tbl, index,
282 (struct bnxt_qplib_gid *)gid);
283 return rc;
284 }
285
286 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context)
287 {
288 int rc = 0;
289 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
290 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
291 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
292 struct bnxt_qplib_gid *gid_to_del;
293 u16 vlan_id = 0xFFFF;
294
295 /* Delete the entry from the hardware */
296 ctx = *context;
297 if (!ctx)
298 return -EINVAL;
299
300 if (sgid_tbl && sgid_tbl->active) {
301 if (ctx->idx >= sgid_tbl->max)
302 return -EINVAL;
303 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid;
304 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id;
305 /* DEL_GID is called in WQ context(netdevice_event_work_handler)
306 * or via the ib_unregister_device path. In the former case QP1
307 * may not be destroyed yet, in which case just return as FW
308 * needs that entry to be present and will fail it's deletion.
309 * We could get invoked again after QP1 is destroyed OR get an
310 * ADD_GID call with a different GID value for the same index
311 * where we issue MODIFY_GID cmd to update the GID entry -- TBD
312 */
313 if (ctx->idx == 0 &&
314 rdma_link_local_addr((struct in6_addr *)gid_to_del) &&
315 ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) {
316 ibdev_dbg(&rdev->ibdev,
317 "Trying to delete GID0 while QP1 is alive\n");
318 return -EFAULT;
319 }
320 ctx->refcnt--;
321 if (!ctx->refcnt) {
322 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del,
323 vlan_id, true);
324 if (rc) {
325 ibdev_err(&rdev->ibdev,
326 "Failed to remove GID: %#x", rc);
327 } else {
328 ctx_tbl = sgid_tbl->ctx;
329 ctx_tbl[ctx->idx] = NULL;
330 kfree(ctx);
331 }
332 }
333 } else {
334 return -EINVAL;
335 }
336 return rc;
337 }
338
339 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context)
340 {
341 int rc;
342 u32 tbl_idx = 0;
343 u16 vlan_id = 0xFFFF;
344 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
345 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
346 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
347
348 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL);
349 if (rc)
350 return rc;
351
352 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid,
353 rdev->qplib_res.netdev->dev_addr,
354 vlan_id, true, &tbl_idx);
355 if (rc == -EALREADY) {
356 ctx_tbl = sgid_tbl->ctx;
357 ctx_tbl[tbl_idx]->refcnt++;
358 *context = ctx_tbl[tbl_idx];
359 return 0;
360 }
361
362 if (rc < 0) {
363 ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc);
364 return rc;
365 }
366
367 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
368 if (!ctx)
369 return -ENOMEM;
370 ctx_tbl = sgid_tbl->ctx;
371 ctx->idx = tbl_idx;
372 ctx->refcnt = 1;
373 ctx_tbl[tbl_idx] = ctx;
374 *context = ctx;
375
376 return rc;
377 }
378
379 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev,
380 u8 port_num)
381 {
382 return IB_LINK_LAYER_ETHERNET;
383 }
384
385 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE)
386
387 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd)
388 {
389 struct bnxt_re_fence_data *fence = &pd->fence;
390 struct ib_mr *ib_mr = &fence->mr->ib_mr;
391 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe;
392
393 memset(wqe, 0, sizeof(*wqe));
394 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW;
395 wqe->wr_id = BNXT_QPLIB_FENCE_WRID;
396 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
397 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
398 wqe->bind.zero_based = false;
399 wqe->bind.parent_l_key = ib_mr->lkey;
400 wqe->bind.va = (u64)(unsigned long)fence->va;
401 wqe->bind.length = fence->size;
402 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ);
403 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1;
404
405 /* Save the initial rkey in fence structure for now;
406 * wqe->bind.r_key will be set at (re)bind time.
407 */
408 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey);
409 }
410
411 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp)
412 {
413 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp,
414 qplib_qp);
415 struct ib_pd *ib_pd = qp->ib_qp.pd;
416 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
417 struct bnxt_re_fence_data *fence = &pd->fence;
418 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe;
419 struct bnxt_qplib_swqe wqe;
420 int rc;
421
422 memcpy(&wqe, fence_wqe, sizeof(wqe));
423 wqe.bind.r_key = fence->bind_rkey;
424 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey);
425
426 ibdev_dbg(&qp->rdev->ibdev,
427 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n",
428 wqe.bind.r_key, qp->qplib_qp.id, pd);
429 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
430 if (rc) {
431 ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n");
432 return rc;
433 }
434 bnxt_qplib_post_send_db(&qp->qplib_qp);
435
436 return rc;
437 }
438
439 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd)
440 {
441 struct bnxt_re_fence_data *fence = &pd->fence;
442 struct bnxt_re_dev *rdev = pd->rdev;
443 struct device *dev = &rdev->en_dev->pdev->dev;
444 struct bnxt_re_mr *mr = fence->mr;
445
446 if (fence->mw) {
447 bnxt_re_dealloc_mw(fence->mw);
448 fence->mw = NULL;
449 }
450 if (mr) {
451 if (mr->ib_mr.rkey)
452 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr,
453 true);
454 if (mr->ib_mr.lkey)
455 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
456 kfree(mr);
457 fence->mr = NULL;
458 }
459 if (fence->dma_addr) {
460 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES,
461 DMA_BIDIRECTIONAL);
462 fence->dma_addr = 0;
463 }
464 }
465
466 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd)
467 {
468 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND;
469 struct bnxt_re_fence_data *fence = &pd->fence;
470 struct bnxt_re_dev *rdev = pd->rdev;
471 struct device *dev = &rdev->en_dev->pdev->dev;
472 struct bnxt_re_mr *mr = NULL;
473 dma_addr_t dma_addr = 0;
474 struct ib_mw *mw;
475 u64 pbl_tbl;
476 int rc;
477
478 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES,
479 DMA_BIDIRECTIONAL);
480 rc = dma_mapping_error(dev, dma_addr);
481 if (rc) {
482 ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n");
483 rc = -EIO;
484 fence->dma_addr = 0;
485 goto fail;
486 }
487 fence->dma_addr = dma_addr;
488
489 /* Allocate a MR */
490 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
491 if (!mr) {
492 rc = -ENOMEM;
493 goto fail;
494 }
495 fence->mr = mr;
496 mr->rdev = rdev;
497 mr->qplib_mr.pd = &pd->qplib_pd;
498 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
499 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
500 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
501 if (rc) {
502 ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n");
503 goto fail;
504 }
505
506 /* Register MR */
507 mr->ib_mr.lkey = mr->qplib_mr.lkey;
508 mr->qplib_mr.va = (u64)(unsigned long)fence->va;
509 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES;
510 pbl_tbl = dma_addr;
511 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl_tbl,
512 BNXT_RE_FENCE_PBL_SIZE, false, PAGE_SIZE);
513 if (rc) {
514 ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n");
515 goto fail;
516 }
517 mr->ib_mr.rkey = mr->qplib_mr.rkey;
518
519 /* Create a fence MW only for kernel consumers */
520 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL);
521 if (IS_ERR(mw)) {
522 ibdev_err(&rdev->ibdev,
523 "Failed to create fence-MW for PD: %p\n", pd);
524 rc = PTR_ERR(mw);
525 goto fail;
526 }
527 fence->mw = mw;
528
529 bnxt_re_create_fence_wqe(pd);
530 return 0;
531
532 fail:
533 bnxt_re_destroy_fence_mr(pd);
534 return rc;
535 }
536
537 /* Protection Domains */
538 void bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata)
539 {
540 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
541 struct bnxt_re_dev *rdev = pd->rdev;
542
543 bnxt_re_destroy_fence_mr(pd);
544
545 if (pd->qplib_pd.id)
546 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
547 &pd->qplib_pd);
548 }
549
550 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
551 {
552 struct ib_device *ibdev = ibpd->device;
553 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
554 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context(
555 udata, struct bnxt_re_ucontext, ib_uctx);
556 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd);
557 int rc;
558
559 pd->rdev = rdev;
560 if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) {
561 ibdev_err(&rdev->ibdev, "Failed to allocate HW PD");
562 rc = -ENOMEM;
563 goto fail;
564 }
565
566 if (udata) {
567 struct bnxt_re_pd_resp resp;
568
569 if (!ucntx->dpi.dbr) {
570 /* Allocate DPI in alloc_pd to avoid failing of
571 * ibv_devinfo and family of application when DPIs
572 * are depleted.
573 */
574 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl,
575 &ucntx->dpi, ucntx)) {
576 rc = -ENOMEM;
577 goto dbfail;
578 }
579 }
580
581 resp.pdid = pd->qplib_pd.id;
582 /* Still allow mapping this DBR to the new user PD. */
583 resp.dpi = ucntx->dpi.dpi;
584 resp.dbr = (u64)ucntx->dpi.umdbr;
585
586 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
587 if (rc) {
588 ibdev_err(&rdev->ibdev,
589 "Failed to copy user response\n");
590 goto dbfail;
591 }
592 }
593
594 if (!udata)
595 if (bnxt_re_create_fence_mr(pd))
596 ibdev_warn(&rdev->ibdev,
597 "Failed to create Fence-MR\n");
598 return 0;
599 dbfail:
600 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
601 &pd->qplib_pd);
602 fail:
603 return rc;
604 }
605
606 /* Address Handles */
607 void bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags)
608 {
609 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
610 struct bnxt_re_dev *rdev = ah->rdev;
611
612 bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah,
613 !(flags & RDMA_DESTROY_AH_SLEEPABLE));
614 }
615
616 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype)
617 {
618 u8 nw_type;
619
620 switch (ntype) {
621 case RDMA_NETWORK_IPV4:
622 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
623 break;
624 case RDMA_NETWORK_IPV6:
625 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
626 break;
627 default:
628 nw_type = CMDQ_CREATE_AH_TYPE_V1;
629 break;
630 }
631 return nw_type;
632 }
633
634 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr,
635 u32 flags, struct ib_udata *udata)
636 {
637 struct ib_pd *ib_pd = ib_ah->pd;
638 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
639 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
640 struct bnxt_re_dev *rdev = pd->rdev;
641 const struct ib_gid_attr *sgid_attr;
642 struct bnxt_re_gid_ctx *ctx;
643 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
644 u8 nw_type;
645 int rc;
646
647 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
648 ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set");
649 return -EINVAL;
650 }
651
652 ah->rdev = rdev;
653 ah->qplib_ah.pd = &pd->qplib_pd;
654
655 /* Supply the configuration for the HW */
656 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw,
657 sizeof(union ib_gid));
658 sgid_attr = grh->sgid_attr;
659 /* Get the HW context of the GID. The reference
660 * of GID table entry is already taken by the caller.
661 */
662 ctx = rdma_read_gid_hw_context(sgid_attr);
663 ah->qplib_ah.sgid_index = ctx->idx;
664 ah->qplib_ah.host_sgid_index = grh->sgid_index;
665 ah->qplib_ah.traffic_class = grh->traffic_class;
666 ah->qplib_ah.flow_label = grh->flow_label;
667 ah->qplib_ah.hop_limit = grh->hop_limit;
668 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
669
670 /* Get network header type for this GID */
671 nw_type = rdma_gid_attr_network_type(sgid_attr);
672 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type);
673
674 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
675 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah,
676 !(flags & RDMA_CREATE_AH_SLEEPABLE));
677 if (rc) {
678 ibdev_err(&rdev->ibdev, "Failed to allocate HW AH");
679 return rc;
680 }
681
682 /* Write AVID to shared page. */
683 if (udata) {
684 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
685 udata, struct bnxt_re_ucontext, ib_uctx);
686 unsigned long flag;
687 u32 *wrptr;
688
689 spin_lock_irqsave(&uctx->sh_lock, flag);
690 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT);
691 *wrptr = ah->qplib_ah.id;
692 wmb(); /* make sure cache is updated. */
693 spin_unlock_irqrestore(&uctx->sh_lock, flag);
694 }
695
696 return 0;
697 }
698
699 int bnxt_re_modify_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
700 {
701 return 0;
702 }
703
704 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
705 {
706 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
707
708 ah_attr->type = ib_ah->type;
709 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl);
710 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN);
711 rdma_ah_set_grh(ah_attr, NULL, 0,
712 ah->qplib_ah.host_sgid_index,
713 0, ah->qplib_ah.traffic_class);
714 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data);
715 rdma_ah_set_port_num(ah_attr, 1);
716 rdma_ah_set_static_rate(ah_attr, 0);
717 return 0;
718 }
719
720 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp)
721 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock)
722 {
723 unsigned long flags;
724
725 spin_lock_irqsave(&qp->scq->cq_lock, flags);
726 if (qp->rcq != qp->scq)
727 spin_lock(&qp->rcq->cq_lock);
728 else
729 __acquire(&qp->rcq->cq_lock);
730
731 return flags;
732 }
733
734 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp,
735 unsigned long flags)
736 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock)
737 {
738 if (qp->rcq != qp->scq)
739 spin_unlock(&qp->rcq->cq_lock);
740 else
741 __release(&qp->rcq->cq_lock);
742 spin_unlock_irqrestore(&qp->scq->cq_lock, flags);
743 }
744
745 static int bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp)
746 {
747 struct bnxt_re_qp *gsi_sqp;
748 struct bnxt_re_ah *gsi_sah;
749 struct bnxt_re_dev *rdev;
750 int rc = 0;
751
752 rdev = qp->rdev;
753 gsi_sqp = rdev->gsi_ctx.gsi_sqp;
754 gsi_sah = rdev->gsi_ctx.gsi_sah;
755
756 /* remove from active qp list */
757 mutex_lock(&rdev->qp_lock);
758 list_del(&gsi_sqp->list);
759 mutex_unlock(&rdev->qp_lock);
760 atomic_dec(&rdev->qp_count);
761
762 ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n");
763 bnxt_qplib_destroy_ah(&rdev->qplib_res,
764 &gsi_sah->qplib_ah,
765 true);
766 bnxt_qplib_clean_qp(&qp->qplib_qp);
767
768 ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n");
769 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp);
770 if (rc) {
771 ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed");
772 goto fail;
773 }
774 bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp);
775
776 kfree(rdev->gsi_ctx.sqp_tbl);
777 kfree(gsi_sah);
778 kfree(gsi_sqp);
779 rdev->gsi_ctx.gsi_sqp = NULL;
780 rdev->gsi_ctx.gsi_sah = NULL;
781 rdev->gsi_ctx.sqp_tbl = NULL;
782
783 return 0;
784 fail:
785 return rc;
786 }
787
788 /* Queue Pairs */
789 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata)
790 {
791 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
792 struct bnxt_re_dev *rdev = qp->rdev;
793 unsigned int flags;
794 int rc;
795
796 mutex_lock(&rdev->qp_lock);
797 list_del(&qp->list);
798 mutex_unlock(&rdev->qp_lock);
799 atomic_dec(&rdev->qp_count);
800
801 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp);
802
803 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
804 if (rc) {
805 ibdev_err(&rdev->ibdev, "Failed to destroy HW QP");
806 return rc;
807 }
808
809 if (rdma_is_kernel_res(&qp->ib_qp.res)) {
810 flags = bnxt_re_lock_cqs(qp);
811 bnxt_qplib_clean_qp(&qp->qplib_qp);
812 bnxt_re_unlock_cqs(qp, flags);
813 }
814
815 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp);
816
817 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) {
818 rc = bnxt_re_destroy_gsi_sqp(qp);
819 if (rc)
820 goto sh_fail;
821 }
822
823 ib_umem_release(qp->rumem);
824 ib_umem_release(qp->sumem);
825
826 kfree(qp);
827 return 0;
828 sh_fail:
829 return rc;
830 }
831
832 static u8 __from_ib_qp_type(enum ib_qp_type type)
833 {
834 switch (type) {
835 case IB_QPT_GSI:
836 return CMDQ_CREATE_QP1_TYPE_GSI;
837 case IB_QPT_RC:
838 return CMDQ_CREATE_QP_TYPE_RC;
839 case IB_QPT_UD:
840 return CMDQ_CREATE_QP_TYPE_UD;
841 default:
842 return IB_QPT_MAX;
843 }
844 }
845
846 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,
847 struct bnxt_re_qp *qp, struct ib_udata *udata)
848 {
849 struct bnxt_re_qp_req ureq;
850 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp;
851 struct ib_umem *umem;
852 int bytes = 0, psn_sz;
853 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context(
854 udata, struct bnxt_re_ucontext, ib_uctx);
855
856 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
857 return -EFAULT;
858
859 bytes = (qplib_qp->sq.max_wqe * BNXT_QPLIB_MAX_SQE_ENTRY_SIZE);
860 /* Consider mapping PSN search memory only for RC QPs. */
861 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) {
862 psn_sz = bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ?
863 sizeof(struct sq_psn_search_ext) :
864 sizeof(struct sq_psn_search);
865 bytes += (qplib_qp->sq.max_wqe * psn_sz);
866 }
867 bytes = PAGE_ALIGN(bytes);
868 umem = ib_umem_get(&rdev->ibdev, ureq.qpsva, bytes,
869 IB_ACCESS_LOCAL_WRITE);
870 if (IS_ERR(umem))
871 return PTR_ERR(umem);
872
873 qp->sumem = umem;
874 qplib_qp->sq.sg_info.sghead = umem->sg_head.sgl;
875 qplib_qp->sq.sg_info.npages = ib_umem_num_pages(umem);
876 qplib_qp->sq.sg_info.nmap = umem->nmap;
877 qplib_qp->sq.sg_info.pgsize = PAGE_SIZE;
878 qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT;
879 qplib_qp->qp_handle = ureq.qp_handle;
880
881 if (!qp->qplib_qp.srq) {
882 bytes = (qplib_qp->rq.max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE);
883 bytes = PAGE_ALIGN(bytes);
884 umem = ib_umem_get(&rdev->ibdev, ureq.qprva, bytes,
885 IB_ACCESS_LOCAL_WRITE);
886 if (IS_ERR(umem))
887 goto rqfail;
888 qp->rumem = umem;
889 qplib_qp->rq.sg_info.sghead = umem->sg_head.sgl;
890 qplib_qp->rq.sg_info.npages = ib_umem_num_pages(umem);
891 qplib_qp->rq.sg_info.nmap = umem->nmap;
892 qplib_qp->rq.sg_info.pgsize = PAGE_SIZE;
893 qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT;
894 }
895
896 qplib_qp->dpi = &cntx->dpi;
897 return 0;
898 rqfail:
899 ib_umem_release(qp->sumem);
900 qp->sumem = NULL;
901 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info));
902
903 return PTR_ERR(umem);
904 }
905
906 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah
907 (struct bnxt_re_pd *pd,
908 struct bnxt_qplib_res *qp1_res,
909 struct bnxt_qplib_qp *qp1_qp)
910 {
911 struct bnxt_re_dev *rdev = pd->rdev;
912 struct bnxt_re_ah *ah;
913 union ib_gid sgid;
914 int rc;
915
916 ah = kzalloc(sizeof(*ah), GFP_KERNEL);
917 if (!ah)
918 return NULL;
919
920 ah->rdev = rdev;
921 ah->qplib_ah.pd = &pd->qplib_pd;
922
923 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid);
924 if (rc)
925 goto fail;
926
927 /* supply the dgid data same as sgid */
928 memcpy(ah->qplib_ah.dgid.data, &sgid.raw,
929 sizeof(union ib_gid));
930 ah->qplib_ah.sgid_index = 0;
931
932 ah->qplib_ah.traffic_class = 0;
933 ah->qplib_ah.flow_label = 0;
934 ah->qplib_ah.hop_limit = 1;
935 ah->qplib_ah.sl = 0;
936 /* Have DMAC same as SMAC */
937 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr);
938
939 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false);
940 if (rc) {
941 ibdev_err(&rdev->ibdev,
942 "Failed to allocate HW AH for Shadow QP");
943 goto fail;
944 }
945
946 return ah;
947
948 fail:
949 kfree(ah);
950 return NULL;
951 }
952
953 static struct bnxt_re_qp *bnxt_re_create_shadow_qp
954 (struct bnxt_re_pd *pd,
955 struct bnxt_qplib_res *qp1_res,
956 struct bnxt_qplib_qp *qp1_qp)
957 {
958 struct bnxt_re_dev *rdev = pd->rdev;
959 struct bnxt_re_qp *qp;
960 int rc;
961
962 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
963 if (!qp)
964 return NULL;
965
966 qp->rdev = rdev;
967
968 /* Initialize the shadow QP structure from the QP1 values */
969 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
970
971 qp->qplib_qp.pd = &pd->qplib_pd;
972 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
973 qp->qplib_qp.type = IB_QPT_UD;
974
975 qp->qplib_qp.max_inline_data = 0;
976 qp->qplib_qp.sig_type = true;
977
978 /* Shadow QP SQ depth should be same as QP1 RQ depth */
979 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
980 qp->qplib_qp.sq.max_sge = 2;
981 /* Q full delta can be 1 since it is internal QP */
982 qp->qplib_qp.sq.q_full_delta = 1;
983 qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE;
984 qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT;
985
986 qp->qplib_qp.scq = qp1_qp->scq;
987 qp->qplib_qp.rcq = qp1_qp->rcq;
988
989 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
990 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
991 /* Q full delta can be 1 since it is internal QP */
992 qp->qplib_qp.rq.q_full_delta = 1;
993 qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE;
994 qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT;
995
996 qp->qplib_qp.mtu = qp1_qp->mtu;
997
998 qp->qplib_qp.sq_hdr_buf_size = 0;
999 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
1000 qp->qplib_qp.dpi = &rdev->dpi_privileged;
1001
1002 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp);
1003 if (rc)
1004 goto fail;
1005
1006 spin_lock_init(&qp->sq_lock);
1007 INIT_LIST_HEAD(&qp->list);
1008 mutex_lock(&rdev->qp_lock);
1009 list_add_tail(&qp->list, &rdev->qp_list);
1010 atomic_inc(&rdev->qp_count);
1011 mutex_unlock(&rdev->qp_lock);
1012 return qp;
1013 fail:
1014 kfree(qp);
1015 return NULL;
1016 }
1017
1018 static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp,
1019 struct ib_qp_init_attr *init_attr)
1020 {
1021 struct bnxt_qplib_dev_attr *dev_attr;
1022 struct bnxt_qplib_qp *qplqp;
1023 struct bnxt_re_dev *rdev;
1024 int entries;
1025
1026 rdev = qp->rdev;
1027 qplqp = &qp->qplib_qp;
1028 dev_attr = &rdev->dev_attr;
1029
1030 if (init_attr->srq) {
1031 struct bnxt_re_srq *srq;
1032
1033 srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq);
1034 if (!srq) {
1035 ibdev_err(&rdev->ibdev, "SRQ not found");
1036 return -EINVAL;
1037 }
1038 qplqp->srq = &srq->qplib_srq;
1039 qplqp->rq.max_wqe = 0;
1040 } else {
1041 /* Allocate 1 more than what's provided so posting max doesn't
1042 * mean empty.
1043 */
1044 entries = roundup_pow_of_two(init_attr->cap.max_recv_wr + 1);
1045 qplqp->rq.max_wqe = min_t(u32, entries,
1046 dev_attr->max_qp_wqes + 1);
1047
1048 qplqp->rq.q_full_delta = qplqp->rq.max_wqe -
1049 init_attr->cap.max_recv_wr;
1050 qplqp->rq.max_sge = init_attr->cap.max_recv_sge;
1051 if (qplqp->rq.max_sge > dev_attr->max_qp_sges)
1052 qplqp->rq.max_sge = dev_attr->max_qp_sges;
1053 }
1054 qplqp->rq.sg_info.pgsize = PAGE_SIZE;
1055 qplqp->rq.sg_info.pgshft = PAGE_SHIFT;
1056
1057 return 0;
1058 }
1059
1060 static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp)
1061 {
1062 struct bnxt_qplib_dev_attr *dev_attr;
1063 struct bnxt_qplib_qp *qplqp;
1064 struct bnxt_re_dev *rdev;
1065
1066 rdev = qp->rdev;
1067 qplqp = &qp->qplib_qp;
1068 dev_attr = &rdev->dev_attr;
1069
1070 qplqp->rq.max_sge = dev_attr->max_qp_sges;
1071 if (qplqp->rq.max_sge > dev_attr->max_qp_sges)
1072 qplqp->rq.max_sge = dev_attr->max_qp_sges;
1073 qplqp->rq.max_sge = 6;
1074 }
1075
1076 static void bnxt_re_init_sq_attr(struct bnxt_re_qp *qp,
1077 struct ib_qp_init_attr *init_attr,
1078 struct ib_udata *udata)
1079 {
1080 struct bnxt_qplib_dev_attr *dev_attr;
1081 struct bnxt_qplib_qp *qplqp;
1082 struct bnxt_re_dev *rdev;
1083 int entries;
1084
1085 rdev = qp->rdev;
1086 qplqp = &qp->qplib_qp;
1087 dev_attr = &rdev->dev_attr;
1088
1089 qplqp->sq.max_sge = init_attr->cap.max_send_sge;
1090 if (qplqp->sq.max_sge > dev_attr->max_qp_sges)
1091 qplqp->sq.max_sge = dev_attr->max_qp_sges;
1092 /*
1093 * Change the SQ depth if user has requested minimum using
1094 * configfs. Only supported for kernel consumers
1095 */
1096 entries = init_attr->cap.max_send_wr;
1097 /* Allocate 128 + 1 more than what's provided */
1098 entries = roundup_pow_of_two(entries + BNXT_QPLIB_RESERVED_QP_WRS + 1);
1099 qplqp->sq.max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes +
1100 BNXT_QPLIB_RESERVED_QP_WRS + 1);
1101 qplqp->sq.q_full_delta = BNXT_QPLIB_RESERVED_QP_WRS + 1;
1102 /*
1103 * Reserving one slot for Phantom WQE. Application can
1104 * post one extra entry in this case. But allowing this to avoid
1105 * unexpected Queue full condition
1106 */
1107 qplqp->sq.q_full_delta -= 1;
1108 qplqp->sq.sg_info.pgsize = PAGE_SIZE;
1109 qplqp->sq.sg_info.pgshft = PAGE_SHIFT;
1110 }
1111
1112 static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp,
1113 struct ib_qp_init_attr *init_attr)
1114 {
1115 struct bnxt_qplib_dev_attr *dev_attr;
1116 struct bnxt_qplib_qp *qplqp;
1117 struct bnxt_re_dev *rdev;
1118 int entries;
1119
1120 rdev = qp->rdev;
1121 qplqp = &qp->qplib_qp;
1122 dev_attr = &rdev->dev_attr;
1123
1124 entries = roundup_pow_of_two(init_attr->cap.max_send_wr + 1);
1125 qplqp->sq.max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1126 qplqp->sq.q_full_delta = qplqp->sq.max_wqe -
1127 init_attr->cap.max_send_wr;
1128 qplqp->sq.max_sge++; /* Need one extra sge to put UD header */
1129 if (qplqp->sq.max_sge > dev_attr->max_qp_sges)
1130 qplqp->sq.max_sge = dev_attr->max_qp_sges;
1131 }
1132
1133 static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev,
1134 struct ib_qp_init_attr *init_attr)
1135 {
1136 struct bnxt_qplib_chip_ctx *chip_ctx;
1137 int qptype;
1138
1139 chip_ctx = rdev->chip_ctx;
1140
1141 qptype = __from_ib_qp_type(init_attr->qp_type);
1142 if (qptype == IB_QPT_MAX) {
1143 ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype);
1144 qptype = -EOPNOTSUPP;
1145 goto out;
1146 }
1147
1148 if (bnxt_qplib_is_chip_gen_p5(chip_ctx) &&
1149 init_attr->qp_type == IB_QPT_GSI)
1150 qptype = CMDQ_CREATE_QP_TYPE_GSI;
1151 out:
1152 return qptype;
1153 }
1154
1155 static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1156 struct ib_qp_init_attr *init_attr,
1157 struct ib_udata *udata)
1158 {
1159 struct bnxt_qplib_dev_attr *dev_attr;
1160 struct bnxt_qplib_qp *qplqp;
1161 struct bnxt_re_dev *rdev;
1162 struct bnxt_re_cq *cq;
1163 int rc = 0, qptype;
1164
1165 rdev = qp->rdev;
1166 qplqp = &qp->qplib_qp;
1167 dev_attr = &rdev->dev_attr;
1168
1169 /* Setup misc params */
1170 ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr);
1171 qplqp->pd = &pd->qplib_pd;
1172 qplqp->qp_handle = (u64)qplqp;
1173 qplqp->max_inline_data = init_attr->cap.max_inline_data;
1174 qplqp->sig_type = ((init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ?
1175 true : false);
1176 qptype = bnxt_re_init_qp_type(rdev, init_attr);
1177 if (qptype < 0) {
1178 rc = qptype;
1179 goto out;
1180 }
1181 qplqp->type = (u8)qptype;
1182
1183 if (init_attr->qp_type == IB_QPT_RC) {
1184 qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom;
1185 qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
1186 }
1187 qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1188 qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */
1189 if (init_attr->create_flags)
1190 ibdev_dbg(&rdev->ibdev,
1191 "QP create flags 0x%x not supported",
1192 init_attr->create_flags);
1193
1194 /* Setup CQs */
1195 if (init_attr->send_cq) {
1196 cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq);
1197 if (!cq) {
1198 ibdev_err(&rdev->ibdev, "Send CQ not found");
1199 rc = -EINVAL;
1200 goto out;
1201 }
1202 qplqp->scq = &cq->qplib_cq;
1203 qp->scq = cq;
1204 }
1205
1206 if (init_attr->recv_cq) {
1207 cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq);
1208 if (!cq) {
1209 ibdev_err(&rdev->ibdev, "Receive CQ not found");
1210 rc = -EINVAL;
1211 goto out;
1212 }
1213 qplqp->rcq = &cq->qplib_cq;
1214 qp->rcq = cq;
1215 }
1216
1217 /* Setup RQ/SRQ */
1218 rc = bnxt_re_init_rq_attr(qp, init_attr);
1219 if (rc)
1220 goto out;
1221 if (init_attr->qp_type == IB_QPT_GSI)
1222 bnxt_re_adjust_gsi_rq_attr(qp);
1223
1224 /* Setup SQ */
1225 bnxt_re_init_sq_attr(qp, init_attr, udata);
1226 if (init_attr->qp_type == IB_QPT_GSI)
1227 bnxt_re_adjust_gsi_sq_attr(qp, init_attr);
1228
1229 if (udata) /* This will update DPI and qp_handle */
1230 rc = bnxt_re_init_user_qp(rdev, pd, qp, udata);
1231 out:
1232 return rc;
1233 }
1234
1235 static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp,
1236 struct bnxt_re_pd *pd)
1237 {
1238 struct bnxt_re_sqp_entries *sqp_tbl = NULL;
1239 struct bnxt_re_dev *rdev;
1240 struct bnxt_re_qp *sqp;
1241 struct bnxt_re_ah *sah;
1242 int rc = 0;
1243
1244 rdev = qp->rdev;
1245 /* Create a shadow QP to handle the QP1 traffic */
1246 sqp_tbl = kzalloc(sizeof(*sqp_tbl) * BNXT_RE_MAX_GSI_SQP_ENTRIES,
1247 GFP_KERNEL);
1248 if (!sqp_tbl)
1249 return -ENOMEM;
1250 rdev->gsi_ctx.sqp_tbl = sqp_tbl;
1251
1252 sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp);
1253 if (!sqp) {
1254 rc = -ENODEV;
1255 ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1");
1256 goto out;
1257 }
1258 rdev->gsi_ctx.gsi_sqp = sqp;
1259
1260 sqp->rcq = qp->rcq;
1261 sqp->scq = qp->scq;
1262 sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res,
1263 &qp->qplib_qp);
1264 if (!sah) {
1265 bnxt_qplib_destroy_qp(&rdev->qplib_res,
1266 &sqp->qplib_qp);
1267 rc = -ENODEV;
1268 ibdev_err(&rdev->ibdev,
1269 "Failed to create AH entry for ShadowQP");
1270 goto out;
1271 }
1272 rdev->gsi_ctx.gsi_sah = sah;
1273
1274 return 0;
1275 out:
1276 kfree(sqp_tbl);
1277 return rc;
1278 }
1279
1280 static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1281 struct ib_qp_init_attr *init_attr)
1282 {
1283 struct bnxt_re_dev *rdev;
1284 struct bnxt_qplib_qp *qplqp;
1285 int rc = 0;
1286
1287 rdev = qp->rdev;
1288 qplqp = &qp->qplib_qp;
1289
1290 qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1291 qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2;
1292
1293 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp);
1294 if (rc) {
1295 ibdev_err(&rdev->ibdev, "create HW QP1 failed!");
1296 goto out;
1297 }
1298
1299 rc = bnxt_re_create_shadow_gsi(qp, pd);
1300 out:
1301 return rc;
1302 }
1303
1304 static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev,
1305 struct ib_qp_init_attr *init_attr,
1306 struct bnxt_qplib_dev_attr *dev_attr)
1307 {
1308 bool rc = true;
1309
1310 if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes ||
1311 init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes ||
1312 init_attr->cap.max_send_sge > dev_attr->max_qp_sges ||
1313 init_attr->cap.max_recv_sge > dev_attr->max_qp_sges ||
1314 init_attr->cap.max_inline_data > dev_attr->max_inline_data) {
1315 ibdev_err(&rdev->ibdev,
1316 "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x",
1317 init_attr->cap.max_send_wr, dev_attr->max_qp_wqes,
1318 init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes,
1319 init_attr->cap.max_send_sge, dev_attr->max_qp_sges,
1320 init_attr->cap.max_recv_sge, dev_attr->max_qp_sges,
1321 init_attr->cap.max_inline_data,
1322 dev_attr->max_inline_data);
1323 rc = false;
1324 }
1325 return rc;
1326 }
1327
1328 struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd,
1329 struct ib_qp_init_attr *qp_init_attr,
1330 struct ib_udata *udata)
1331 {
1332 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1333 struct bnxt_re_dev *rdev = pd->rdev;
1334 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1335 struct bnxt_re_qp *qp;
1336 int rc;
1337
1338 rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr);
1339 if (!rc) {
1340 rc = -EINVAL;
1341 goto exit;
1342 }
1343
1344 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1345 if (!qp) {
1346 rc = -ENOMEM;
1347 goto exit;
1348 }
1349 qp->rdev = rdev;
1350 rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, udata);
1351 if (rc)
1352 goto fail;
1353
1354 if (qp_init_attr->qp_type == IB_QPT_GSI &&
1355 !(bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx))) {
1356 rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr);
1357 if (rc == -ENODEV)
1358 goto qp_destroy;
1359 if (rc)
1360 goto fail;
1361 } else {
1362 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
1363 if (rc) {
1364 ibdev_err(&rdev->ibdev, "Failed to create HW QP");
1365 goto free_umem;
1366 }
1367 if (udata) {
1368 struct bnxt_re_qp_resp resp;
1369
1370 resp.qpid = qp->qplib_qp.id;
1371 resp.rsvd = 0;
1372 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1373 if (rc) {
1374 ibdev_err(&rdev->ibdev, "Failed to copy QP udata");
1375 goto qp_destroy;
1376 }
1377 }
1378 }
1379
1380 qp->ib_qp.qp_num = qp->qplib_qp.id;
1381 if (qp_init_attr->qp_type == IB_QPT_GSI)
1382 rdev->gsi_ctx.gsi_qp = qp;
1383 spin_lock_init(&qp->sq_lock);
1384 spin_lock_init(&qp->rq_lock);
1385 INIT_LIST_HEAD(&qp->list);
1386 mutex_lock(&rdev->qp_lock);
1387 list_add_tail(&qp->list, &rdev->qp_list);
1388 mutex_unlock(&rdev->qp_lock);
1389 atomic_inc(&rdev->qp_count);
1390
1391 return &qp->ib_qp;
1392 qp_destroy:
1393 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
1394 free_umem:
1395 ib_umem_release(qp->rumem);
1396 ib_umem_release(qp->sumem);
1397 fail:
1398 kfree(qp);
1399 exit:
1400 return ERR_PTR(rc);
1401 }
1402
1403 static u8 __from_ib_qp_state(enum ib_qp_state state)
1404 {
1405 switch (state) {
1406 case IB_QPS_RESET:
1407 return CMDQ_MODIFY_QP_NEW_STATE_RESET;
1408 case IB_QPS_INIT:
1409 return CMDQ_MODIFY_QP_NEW_STATE_INIT;
1410 case IB_QPS_RTR:
1411 return CMDQ_MODIFY_QP_NEW_STATE_RTR;
1412 case IB_QPS_RTS:
1413 return CMDQ_MODIFY_QP_NEW_STATE_RTS;
1414 case IB_QPS_SQD:
1415 return CMDQ_MODIFY_QP_NEW_STATE_SQD;
1416 case IB_QPS_SQE:
1417 return CMDQ_MODIFY_QP_NEW_STATE_SQE;
1418 case IB_QPS_ERR:
1419 default:
1420 return CMDQ_MODIFY_QP_NEW_STATE_ERR;
1421 }
1422 }
1423
1424 static enum ib_qp_state __to_ib_qp_state(u8 state)
1425 {
1426 switch (state) {
1427 case CMDQ_MODIFY_QP_NEW_STATE_RESET:
1428 return IB_QPS_RESET;
1429 case CMDQ_MODIFY_QP_NEW_STATE_INIT:
1430 return IB_QPS_INIT;
1431 case CMDQ_MODIFY_QP_NEW_STATE_RTR:
1432 return IB_QPS_RTR;
1433 case CMDQ_MODIFY_QP_NEW_STATE_RTS:
1434 return IB_QPS_RTS;
1435 case CMDQ_MODIFY_QP_NEW_STATE_SQD:
1436 return IB_QPS_SQD;
1437 case CMDQ_MODIFY_QP_NEW_STATE_SQE:
1438 return IB_QPS_SQE;
1439 case CMDQ_MODIFY_QP_NEW_STATE_ERR:
1440 default:
1441 return IB_QPS_ERR;
1442 }
1443 }
1444
1445 static u32 __from_ib_mtu(enum ib_mtu mtu)
1446 {
1447 switch (mtu) {
1448 case IB_MTU_256:
1449 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256;
1450 case IB_MTU_512:
1451 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512;
1452 case IB_MTU_1024:
1453 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024;
1454 case IB_MTU_2048:
1455 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1456 case IB_MTU_4096:
1457 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096;
1458 default:
1459 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1460 }
1461 }
1462
1463 static enum ib_mtu __to_ib_mtu(u32 mtu)
1464 {
1465 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) {
1466 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256:
1467 return IB_MTU_256;
1468 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512:
1469 return IB_MTU_512;
1470 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024:
1471 return IB_MTU_1024;
1472 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048:
1473 return IB_MTU_2048;
1474 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096:
1475 return IB_MTU_4096;
1476 default:
1477 return IB_MTU_2048;
1478 }
1479 }
1480
1481 /* Shared Receive Queues */
1482 void bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata)
1483 {
1484 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1485 ib_srq);
1486 struct bnxt_re_dev *rdev = srq->rdev;
1487 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1488 struct bnxt_qplib_nq *nq = NULL;
1489
1490 if (qplib_srq->cq)
1491 nq = qplib_srq->cq->nq;
1492 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq);
1493 ib_umem_release(srq->umem);
1494 atomic_dec(&rdev->srq_count);
1495 if (nq)
1496 nq->budget--;
1497 }
1498
1499 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev,
1500 struct bnxt_re_pd *pd,
1501 struct bnxt_re_srq *srq,
1502 struct ib_udata *udata)
1503 {
1504 struct bnxt_re_srq_req ureq;
1505 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1506 struct ib_umem *umem;
1507 int bytes = 0;
1508 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context(
1509 udata, struct bnxt_re_ucontext, ib_uctx);
1510
1511 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
1512 return -EFAULT;
1513
1514 bytes = (qplib_srq->max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE);
1515 bytes = PAGE_ALIGN(bytes);
1516 umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes,
1517 IB_ACCESS_LOCAL_WRITE);
1518 if (IS_ERR(umem))
1519 return PTR_ERR(umem);
1520
1521 srq->umem = umem;
1522 qplib_srq->sg_info.sghead = umem->sg_head.sgl;
1523 qplib_srq->sg_info.npages = ib_umem_num_pages(umem);
1524 qplib_srq->sg_info.nmap = umem->nmap;
1525 qplib_srq->sg_info.pgsize = PAGE_SIZE;
1526 qplib_srq->sg_info.pgshft = PAGE_SHIFT;
1527 qplib_srq->srq_handle = ureq.srq_handle;
1528 qplib_srq->dpi = &cntx->dpi;
1529
1530 return 0;
1531 }
1532
1533 int bnxt_re_create_srq(struct ib_srq *ib_srq,
1534 struct ib_srq_init_attr *srq_init_attr,
1535 struct ib_udata *udata)
1536 {
1537 struct ib_pd *ib_pd = ib_srq->pd;
1538 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1539 struct bnxt_re_dev *rdev = pd->rdev;
1540 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1541 struct bnxt_re_srq *srq =
1542 container_of(ib_srq, struct bnxt_re_srq, ib_srq);
1543 struct bnxt_qplib_nq *nq = NULL;
1544 int rc, entries;
1545
1546 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) {
1547 ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded");
1548 rc = -EINVAL;
1549 goto exit;
1550 }
1551
1552 if (srq_init_attr->srq_type != IB_SRQT_BASIC) {
1553 rc = -EOPNOTSUPP;
1554 goto exit;
1555 }
1556
1557 srq->rdev = rdev;
1558 srq->qplib_srq.pd = &pd->qplib_pd;
1559 srq->qplib_srq.dpi = &rdev->dpi_privileged;
1560 /* Allocate 1 more than what's provided so posting max doesn't
1561 * mean empty
1562 */
1563 entries = roundup_pow_of_two(srq_init_attr->attr.max_wr + 1);
1564 if (entries > dev_attr->max_srq_wqes + 1)
1565 entries = dev_attr->max_srq_wqes + 1;
1566
1567 srq->qplib_srq.max_wqe = entries;
1568 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge;
1569 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit;
1570 srq->srq_limit = srq_init_attr->attr.srq_limit;
1571 srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id;
1572 nq = &rdev->nq[0];
1573
1574 if (udata) {
1575 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata);
1576 if (rc)
1577 goto fail;
1578 }
1579
1580 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq);
1581 if (rc) {
1582 ibdev_err(&rdev->ibdev, "Create HW SRQ failed!");
1583 goto fail;
1584 }
1585
1586 if (udata) {
1587 struct bnxt_re_srq_resp resp;
1588
1589 resp.srqid = srq->qplib_srq.id;
1590 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1591 if (rc) {
1592 ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!");
1593 bnxt_qplib_destroy_srq(&rdev->qplib_res,
1594 &srq->qplib_srq);
1595 goto fail;
1596 }
1597 }
1598 if (nq)
1599 nq->budget++;
1600 atomic_inc(&rdev->srq_count);
1601
1602 return 0;
1603
1604 fail:
1605 ib_umem_release(srq->umem);
1606 exit:
1607 return rc;
1608 }
1609
1610 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr,
1611 enum ib_srq_attr_mask srq_attr_mask,
1612 struct ib_udata *udata)
1613 {
1614 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1615 ib_srq);
1616 struct bnxt_re_dev *rdev = srq->rdev;
1617 int rc;
1618
1619 switch (srq_attr_mask) {
1620 case IB_SRQ_MAX_WR:
1621 /* SRQ resize is not supported */
1622 break;
1623 case IB_SRQ_LIMIT:
1624 /* Change the SRQ threshold */
1625 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe)
1626 return -EINVAL;
1627
1628 srq->qplib_srq.threshold = srq_attr->srq_limit;
1629 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq);
1630 if (rc) {
1631 ibdev_err(&rdev->ibdev, "Modify HW SRQ failed!");
1632 return rc;
1633 }
1634 /* On success, update the shadow */
1635 srq->srq_limit = srq_attr->srq_limit;
1636 /* No need to Build and send response back to udata */
1637 break;
1638 default:
1639 ibdev_err(&rdev->ibdev,
1640 "Unsupported srq_attr_mask 0x%x", srq_attr_mask);
1641 return -EINVAL;
1642 }
1643 return 0;
1644 }
1645
1646 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr)
1647 {
1648 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1649 ib_srq);
1650 struct bnxt_re_srq tsrq;
1651 struct bnxt_re_dev *rdev = srq->rdev;
1652 int rc;
1653
1654 /* Get live SRQ attr */
1655 tsrq.qplib_srq.id = srq->qplib_srq.id;
1656 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq);
1657 if (rc) {
1658 ibdev_err(&rdev->ibdev, "Query HW SRQ failed!");
1659 return rc;
1660 }
1661 srq_attr->max_wr = srq->qplib_srq.max_wqe;
1662 srq_attr->max_sge = srq->qplib_srq.max_sge;
1663 srq_attr->srq_limit = tsrq.qplib_srq.threshold;
1664
1665 return 0;
1666 }
1667
1668 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr,
1669 const struct ib_recv_wr **bad_wr)
1670 {
1671 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1672 ib_srq);
1673 struct bnxt_qplib_swqe wqe;
1674 unsigned long flags;
1675 int rc = 0;
1676
1677 spin_lock_irqsave(&srq->lock, flags);
1678 while (wr) {
1679 /* Transcribe each ib_recv_wr to qplib_swqe */
1680 wqe.num_sge = wr->num_sge;
1681 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
1682 wqe.wr_id = wr->wr_id;
1683 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
1684
1685 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe);
1686 if (rc) {
1687 *bad_wr = wr;
1688 break;
1689 }
1690 wr = wr->next;
1691 }
1692 spin_unlock_irqrestore(&srq->lock, flags);
1693
1694 return rc;
1695 }
1696 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
1697 struct bnxt_re_qp *qp1_qp,
1698 int qp_attr_mask)
1699 {
1700 struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp;
1701 int rc = 0;
1702
1703 if (qp_attr_mask & IB_QP_STATE) {
1704 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1705 qp->qplib_qp.state = qp1_qp->qplib_qp.state;
1706 }
1707 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1708 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1709 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index;
1710 }
1711
1712 if (qp_attr_mask & IB_QP_QKEY) {
1713 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1714 /* Using a Random QKEY */
1715 qp->qplib_qp.qkey = 0x81818181;
1716 }
1717 if (qp_attr_mask & IB_QP_SQ_PSN) {
1718 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1719 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn;
1720 }
1721
1722 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1723 if (rc)
1724 ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1");
1725 return rc;
1726 }
1727
1728 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1729 int qp_attr_mask, struct ib_udata *udata)
1730 {
1731 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1732 struct bnxt_re_dev *rdev = qp->rdev;
1733 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1734 enum ib_qp_state curr_qp_state, new_qp_state;
1735 int rc, entries;
1736 unsigned int flags;
1737 u8 nw_type;
1738
1739 qp->qplib_qp.modify_flags = 0;
1740 if (qp_attr_mask & IB_QP_STATE) {
1741 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
1742 new_qp_state = qp_attr->qp_state;
1743 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state,
1744 ib_qp->qp_type, qp_attr_mask)) {
1745 ibdev_err(&rdev->ibdev,
1746 "Invalid attribute mask: %#x specified ",
1747 qp_attr_mask);
1748 ibdev_err(&rdev->ibdev,
1749 "for qpn: %#x type: %#x",
1750 ib_qp->qp_num, ib_qp->qp_type);
1751 ibdev_err(&rdev->ibdev,
1752 "curr_qp_state=0x%x, new_qp_state=0x%x\n",
1753 curr_qp_state, new_qp_state);
1754 return -EINVAL;
1755 }
1756 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1757 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state);
1758
1759 if (!qp->sumem &&
1760 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
1761 ibdev_dbg(&rdev->ibdev,
1762 "Move QP = %p to flush list\n", qp);
1763 flags = bnxt_re_lock_cqs(qp);
1764 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
1765 bnxt_re_unlock_cqs(qp, flags);
1766 }
1767 if (!qp->sumem &&
1768 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) {
1769 ibdev_dbg(&rdev->ibdev,
1770 "Move QP = %p out of flush list\n", qp);
1771 flags = bnxt_re_lock_cqs(qp);
1772 bnxt_qplib_clean_qp(&qp->qplib_qp);
1773 bnxt_re_unlock_cqs(qp, flags);
1774 }
1775 }
1776 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
1777 qp->qplib_qp.modify_flags |=
1778 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
1779 qp->qplib_qp.en_sqd_async_notify = true;
1780 }
1781 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
1782 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS;
1783 qp->qplib_qp.access =
1784 __from_ib_access_flags(qp_attr->qp_access_flags);
1785 /* LOCAL_WRITE access must be set to allow RC receive */
1786 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
1787 /* Temp: Set all params on QP as of now */
1788 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE;
1789 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ;
1790 }
1791 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1792 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1793 qp->qplib_qp.pkey_index = qp_attr->pkey_index;
1794 }
1795 if (qp_attr_mask & IB_QP_QKEY) {
1796 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1797 qp->qplib_qp.qkey = qp_attr->qkey;
1798 }
1799 if (qp_attr_mask & IB_QP_AV) {
1800 const struct ib_global_route *grh =
1801 rdma_ah_read_grh(&qp_attr->ah_attr);
1802 const struct ib_gid_attr *sgid_attr;
1803 struct bnxt_re_gid_ctx *ctx;
1804
1805 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
1806 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
1807 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
1808 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
1809 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
1810 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
1811 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
1812 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw,
1813 sizeof(qp->qplib_qp.ah.dgid.data));
1814 qp->qplib_qp.ah.flow_label = grh->flow_label;
1815 sgid_attr = grh->sgid_attr;
1816 /* Get the HW context of the GID. The reference
1817 * of GID table entry is already taken by the caller.
1818 */
1819 ctx = rdma_read_gid_hw_context(sgid_attr);
1820 qp->qplib_qp.ah.sgid_index = ctx->idx;
1821 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index;
1822 qp->qplib_qp.ah.hop_limit = grh->hop_limit;
1823 qp->qplib_qp.ah.traffic_class = grh->traffic_class;
1824 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr);
1825 ether_addr_copy(qp->qplib_qp.ah.dmac,
1826 qp_attr->ah_attr.roce.dmac);
1827
1828 rc = rdma_read_gid_l2_fields(sgid_attr, NULL,
1829 &qp->qplib_qp.smac[0]);
1830 if (rc)
1831 return rc;
1832
1833 nw_type = rdma_gid_attr_network_type(sgid_attr);
1834 switch (nw_type) {
1835 case RDMA_NETWORK_IPV4:
1836 qp->qplib_qp.nw_type =
1837 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4;
1838 break;
1839 case RDMA_NETWORK_IPV6:
1840 qp->qplib_qp.nw_type =
1841 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6;
1842 break;
1843 default:
1844 qp->qplib_qp.nw_type =
1845 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1;
1846 break;
1847 }
1848 }
1849
1850 if (qp_attr_mask & IB_QP_PATH_MTU) {
1851 qp->qplib_qp.modify_flags |=
1852 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1853 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu);
1854 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu);
1855 } else if (qp_attr->qp_state == IB_QPS_RTR) {
1856 qp->qplib_qp.modify_flags |=
1857 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1858 qp->qplib_qp.path_mtu =
1859 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu));
1860 qp->qplib_qp.mtu =
1861 ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1862 }
1863
1864 if (qp_attr_mask & IB_QP_TIMEOUT) {
1865 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT;
1866 qp->qplib_qp.timeout = qp_attr->timeout;
1867 }
1868 if (qp_attr_mask & IB_QP_RETRY_CNT) {
1869 qp->qplib_qp.modify_flags |=
1870 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT;
1871 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt;
1872 }
1873 if (qp_attr_mask & IB_QP_RNR_RETRY) {
1874 qp->qplib_qp.modify_flags |=
1875 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY;
1876 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry;
1877 }
1878 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) {
1879 qp->qplib_qp.modify_flags |=
1880 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER;
1881 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer;
1882 }
1883 if (qp_attr_mask & IB_QP_RQ_PSN) {
1884 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN;
1885 qp->qplib_qp.rq.psn = qp_attr->rq_psn;
1886 }
1887 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1888 qp->qplib_qp.modify_flags |=
1889 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC;
1890 /* Cap the max_rd_atomic to device max */
1891 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic,
1892 dev_attr->max_qp_rd_atom);
1893 }
1894 if (qp_attr_mask & IB_QP_SQ_PSN) {
1895 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1896 qp->qplib_qp.sq.psn = qp_attr->sq_psn;
1897 }
1898 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1899 if (qp_attr->max_dest_rd_atomic >
1900 dev_attr->max_qp_init_rd_atom) {
1901 ibdev_err(&rdev->ibdev,
1902 "max_dest_rd_atomic requested%d is > dev_max%d",
1903 qp_attr->max_dest_rd_atomic,
1904 dev_attr->max_qp_init_rd_atom);
1905 return -EINVAL;
1906 }
1907
1908 qp->qplib_qp.modify_flags |=
1909 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC;
1910 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;
1911 }
1912 if (qp_attr_mask & IB_QP_CAP) {
1913 qp->qplib_qp.modify_flags |=
1914 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |
1915 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
1916 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE |
1917 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE |
1918 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA;
1919 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) ||
1920 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) ||
1921 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) ||
1922 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) ||
1923 (qp_attr->cap.max_inline_data >=
1924 dev_attr->max_inline_data)) {
1925 ibdev_err(&rdev->ibdev,
1926 "Create QP failed - max exceeded");
1927 return -EINVAL;
1928 }
1929 entries = roundup_pow_of_two(qp_attr->cap.max_send_wr);
1930 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
1931 dev_attr->max_qp_wqes + 1);
1932 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
1933 qp_attr->cap.max_send_wr;
1934 /*
1935 * Reserving one slot for Phantom WQE. Some application can
1936 * post one extra entry in this case. Allowing this to avoid
1937 * unexpected Queue full condition
1938 */
1939 qp->qplib_qp.sq.q_full_delta -= 1;
1940 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
1941 if (qp->qplib_qp.rq.max_wqe) {
1942 entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr);
1943 qp->qplib_qp.rq.max_wqe =
1944 min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1945 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
1946 qp_attr->cap.max_recv_wr;
1947 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
1948 } else {
1949 /* SRQ was used prior, just ignore the RQ caps */
1950 }
1951 }
1952 if (qp_attr_mask & IB_QP_DEST_QPN) {
1953 qp->qplib_qp.modify_flags |=
1954 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID;
1955 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num;
1956 }
1957 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1958 if (rc) {
1959 ibdev_err(&rdev->ibdev, "Failed to modify HW QP");
1960 return rc;
1961 }
1962 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp)
1963 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask);
1964 return rc;
1965 }
1966
1967 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1968 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
1969 {
1970 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1971 struct bnxt_re_dev *rdev = qp->rdev;
1972 struct bnxt_qplib_qp *qplib_qp;
1973 int rc;
1974
1975 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL);
1976 if (!qplib_qp)
1977 return -ENOMEM;
1978
1979 qplib_qp->id = qp->qplib_qp.id;
1980 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
1981
1982 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp);
1983 if (rc) {
1984 ibdev_err(&rdev->ibdev, "Failed to query HW QP");
1985 goto out;
1986 }
1987 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state);
1988 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0;
1989 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access);
1990 qp_attr->pkey_index = qplib_qp->pkey_index;
1991 qp_attr->qkey = qplib_qp->qkey;
1992 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
1993 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label,
1994 qplib_qp->ah.host_sgid_index,
1995 qplib_qp->ah.hop_limit,
1996 qplib_qp->ah.traffic_class);
1997 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data);
1998 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl);
1999 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac);
2000 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu);
2001 qp_attr->timeout = qplib_qp->timeout;
2002 qp_attr->retry_cnt = qplib_qp->retry_cnt;
2003 qp_attr->rnr_retry = qplib_qp->rnr_retry;
2004 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer;
2005 qp_attr->rq_psn = qplib_qp->rq.psn;
2006 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic;
2007 qp_attr->sq_psn = qplib_qp->sq.psn;
2008 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic;
2009 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR :
2010 IB_SIGNAL_REQ_WR;
2011 qp_attr->dest_qp_num = qplib_qp->dest_qpn;
2012
2013 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
2014 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
2015 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe;
2016 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge;
2017 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
2018 qp_init_attr->cap = qp_attr->cap;
2019
2020 out:
2021 kfree(qplib_qp);
2022 return rc;
2023 }
2024
2025 /* Routine for sending QP1 packets for RoCE V1 an V2
2026 */
2027 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
2028 const struct ib_send_wr *wr,
2029 struct bnxt_qplib_swqe *wqe,
2030 int payload_size)
2031 {
2032 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah,
2033 ib_ah);
2034 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;
2035 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr;
2036 struct bnxt_qplib_sge sge;
2037 u8 nw_type;
2038 u16 ether_type;
2039 union ib_gid dgid;
2040 bool is_eth = false;
2041 bool is_vlan = false;
2042 bool is_grh = false;
2043 bool is_udp = false;
2044 u8 ip_version = 0;
2045 u16 vlan_id = 0xFFFF;
2046 void *buf;
2047 int i, rc = 0;
2048
2049 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
2050
2051 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL);
2052 if (rc)
2053 return rc;
2054
2055 /* Get network header type for this GID */
2056 nw_type = rdma_gid_attr_network_type(sgid_attr);
2057 switch (nw_type) {
2058 case RDMA_NETWORK_IPV4:
2059 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET;
2060 break;
2061 case RDMA_NETWORK_IPV6:
2062 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET;
2063 break;
2064 default:
2065 nw_type = BNXT_RE_ROCE_V1_PACKET;
2066 break;
2067 }
2068 memcpy(&dgid.raw, &qplib_ah->dgid, 16);
2069 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2070 if (is_udp) {
2071 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) {
2072 ip_version = 4;
2073 ether_type = ETH_P_IP;
2074 } else {
2075 ip_version = 6;
2076 ether_type = ETH_P_IPV6;
2077 }
2078 is_grh = false;
2079 } else {
2080 ether_type = ETH_P_IBOE;
2081 is_grh = true;
2082 }
2083
2084 is_eth = true;
2085 is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false;
2086
2087 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh,
2088 ip_version, is_udp, 0, &qp->qp1_hdr);
2089
2090 /* ETH */
2091 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac);
2092 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac);
2093
2094 /* For vlan, check the sgid for vlan existence */
2095
2096 if (!is_vlan) {
2097 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type);
2098 } else {
2099 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type);
2100 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id);
2101 }
2102
2103 if (is_grh || (ip_version == 6)) {
2104 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw,
2105 sizeof(sgid_attr->gid));
2106 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data,
2107 sizeof(sgid_attr->gid));
2108 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit;
2109 }
2110
2111 if (ip_version == 4) {
2112 qp->qp1_hdr.ip4.tos = 0;
2113 qp->qp1_hdr.ip4.id = 0;
2114 qp->qp1_hdr.ip4.frag_off = htons(IP_DF);
2115 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit;
2116
2117 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4);
2118 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4);
2119 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr);
2120 }
2121
2122 if (is_udp) {
2123 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT);
2124 qp->qp1_hdr.udp.sport = htons(0x8CD1);
2125 qp->qp1_hdr.udp.csum = 0;
2126 }
2127
2128 /* BTH */
2129 if (wr->opcode == IB_WR_SEND_WITH_IMM) {
2130 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2131 qp->qp1_hdr.immediate_present = 1;
2132 } else {
2133 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2134 }
2135 if (wr->send_flags & IB_SEND_SOLICITED)
2136 qp->qp1_hdr.bth.solicited_event = 1;
2137 /* pad_count */
2138 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3;
2139
2140 /* P_key for QP1 is for all members */
2141 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF);
2142 qp->qp1_hdr.bth.destination_qpn = IB_QP1;
2143 qp->qp1_hdr.bth.ack_req = 0;
2144 qp->send_psn++;
2145 qp->send_psn &= BTH_PSN_MASK;
2146 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn);
2147 /* DETH */
2148 /* Use the priviledged Q_Key for QP1 */
2149 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY);
2150 qp->qp1_hdr.deth.source_qpn = IB_QP1;
2151
2152 /* Pack the QP1 to the transmit buffer */
2153 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
2154 if (buf) {
2155 ib_ud_header_pack(&qp->qp1_hdr, buf);
2156 for (i = wqe->num_sge; i; i--) {
2157 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
2158 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
2159 wqe->sg_list[i].size = wqe->sg_list[i - 1].size;
2160 }
2161
2162 /*
2163 * Max Header buf size for IPV6 RoCE V2 is 86,
2164 * which is same as the QP1 SQ header buffer.
2165 * Header buf size for IPV4 RoCE V2 can be 66.
2166 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20).
2167 * Subtract 20 bytes from QP1 SQ header buf size
2168 */
2169 if (is_udp && ip_version == 4)
2170 sge.size -= 20;
2171 /*
2172 * Max Header buf size for RoCE V1 is 78.
2173 * ETH(14) + VLAN(4) + GRH(40) + BTH(20).
2174 * Subtract 8 bytes from QP1 SQ header buf size
2175 */
2176 if (!is_udp)
2177 sge.size -= 8;
2178
2179 /* Subtract 4 bytes for non vlan packets */
2180 if (!is_vlan)
2181 sge.size -= 4;
2182
2183 wqe->sg_list[0].addr = sge.addr;
2184 wqe->sg_list[0].lkey = sge.lkey;
2185 wqe->sg_list[0].size = sge.size;
2186 wqe->num_sge++;
2187
2188 } else {
2189 ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!");
2190 rc = -ENOMEM;
2191 }
2192 return rc;
2193 }
2194
2195 /* For the MAD layer, it only provides the recv SGE the size of
2196 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH,
2197 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire
2198 * receive packet (334 bytes) with no VLAN and then copy the GRH
2199 * and the MAD datagram out to the provided SGE.
2200 */
2201 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp,
2202 const struct ib_recv_wr *wr,
2203 struct bnxt_qplib_swqe *wqe,
2204 int payload_size)
2205 {
2206 struct bnxt_re_sqp_entries *sqp_entry;
2207 struct bnxt_qplib_sge ref, sge;
2208 struct bnxt_re_dev *rdev;
2209 u32 rq_prod_index;
2210
2211 rdev = qp->rdev;
2212
2213 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp);
2214
2215 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge))
2216 return -ENOMEM;
2217
2218 /* Create 1 SGE to receive the entire
2219 * ethernet packet
2220 */
2221 /* Save the reference from ULP */
2222 ref.addr = wqe->sg_list[0].addr;
2223 ref.lkey = wqe->sg_list[0].lkey;
2224 ref.size = wqe->sg_list[0].size;
2225
2226 sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index];
2227
2228 /* SGE 1 */
2229 wqe->sg_list[0].addr = sge.addr;
2230 wqe->sg_list[0].lkey = sge.lkey;
2231 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
2232 sge.size -= wqe->sg_list[0].size;
2233
2234 sqp_entry->sge.addr = ref.addr;
2235 sqp_entry->sge.lkey = ref.lkey;
2236 sqp_entry->sge.size = ref.size;
2237 /* Store the wrid for reporting completion */
2238 sqp_entry->wrid = wqe->wr_id;
2239 /* change the wqe->wrid to table index */
2240 wqe->wr_id = rq_prod_index;
2241 return 0;
2242 }
2243
2244 static int is_ud_qp(struct bnxt_re_qp *qp)
2245 {
2246 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD ||
2247 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI);
2248 }
2249
2250 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
2251 const struct ib_send_wr *wr,
2252 struct bnxt_qplib_swqe *wqe)
2253 {
2254 struct bnxt_re_ah *ah = NULL;
2255
2256 if (is_ud_qp(qp)) {
2257 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah);
2258 wqe->send.q_key = ud_wr(wr)->remote_qkey;
2259 wqe->send.dst_qp = ud_wr(wr)->remote_qpn;
2260 wqe->send.avid = ah->qplib_ah.id;
2261 }
2262 switch (wr->opcode) {
2263 case IB_WR_SEND:
2264 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND;
2265 break;
2266 case IB_WR_SEND_WITH_IMM:
2267 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
2268 wqe->send.imm_data = wr->ex.imm_data;
2269 break;
2270 case IB_WR_SEND_WITH_INV:
2271 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
2272 wqe->send.inv_key = wr->ex.invalidate_rkey;
2273 break;
2274 default:
2275 return -EINVAL;
2276 }
2277 if (wr->send_flags & IB_SEND_SIGNALED)
2278 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2279 if (wr->send_flags & IB_SEND_FENCE)
2280 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2281 if (wr->send_flags & IB_SEND_SOLICITED)
2282 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2283 if (wr->send_flags & IB_SEND_INLINE)
2284 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2285
2286 return 0;
2287 }
2288
2289 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr,
2290 struct bnxt_qplib_swqe *wqe)
2291 {
2292 switch (wr->opcode) {
2293 case IB_WR_RDMA_WRITE:
2294 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE;
2295 break;
2296 case IB_WR_RDMA_WRITE_WITH_IMM:
2297 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
2298 wqe->rdma.imm_data = wr->ex.imm_data;
2299 break;
2300 case IB_WR_RDMA_READ:
2301 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
2302 wqe->rdma.inv_key = wr->ex.invalidate_rkey;
2303 break;
2304 default:
2305 return -EINVAL;
2306 }
2307 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr;
2308 wqe->rdma.r_key = rdma_wr(wr)->rkey;
2309 if (wr->send_flags & IB_SEND_SIGNALED)
2310 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2311 if (wr->send_flags & IB_SEND_FENCE)
2312 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2313 if (wr->send_flags & IB_SEND_SOLICITED)
2314 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2315 if (wr->send_flags & IB_SEND_INLINE)
2316 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2317
2318 return 0;
2319 }
2320
2321 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr,
2322 struct bnxt_qplib_swqe *wqe)
2323 {
2324 switch (wr->opcode) {
2325 case IB_WR_ATOMIC_CMP_AND_SWP:
2326 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
2327 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2328 wqe->atomic.swap_data = atomic_wr(wr)->swap;
2329 break;
2330 case IB_WR_ATOMIC_FETCH_AND_ADD:
2331 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD;
2332 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2333 break;
2334 default:
2335 return -EINVAL;
2336 }
2337 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr;
2338 wqe->atomic.r_key = atomic_wr(wr)->rkey;
2339 if (wr->send_flags & IB_SEND_SIGNALED)
2340 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2341 if (wr->send_flags & IB_SEND_FENCE)
2342 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2343 if (wr->send_flags & IB_SEND_SOLICITED)
2344 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2345 return 0;
2346 }
2347
2348 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr,
2349 struct bnxt_qplib_swqe *wqe)
2350 {
2351 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV;
2352 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey;
2353
2354 /* Need unconditional fence for local invalidate
2355 * opcode to work as expected.
2356 */
2357 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2358
2359 if (wr->send_flags & IB_SEND_SIGNALED)
2360 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2361 if (wr->send_flags & IB_SEND_SOLICITED)
2362 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2363
2364 return 0;
2365 }
2366
2367 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr,
2368 struct bnxt_qplib_swqe *wqe)
2369 {
2370 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr);
2371 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl;
2372 int access = wr->access;
2373
2374 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0];
2375 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0];
2376 wqe->frmr.page_list = mr->pages;
2377 wqe->frmr.page_list_len = mr->npages;
2378 wqe->frmr.levels = qplib_frpl->hwq.level;
2379 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR;
2380
2381 /* Need unconditional fence for reg_mr
2382 * opcode to function as expected.
2383 */
2384
2385 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2386
2387 if (wr->wr.send_flags & IB_SEND_SIGNALED)
2388 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2389
2390 if (access & IB_ACCESS_LOCAL_WRITE)
2391 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
2392 if (access & IB_ACCESS_REMOTE_READ)
2393 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ;
2394 if (access & IB_ACCESS_REMOTE_WRITE)
2395 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE;
2396 if (access & IB_ACCESS_REMOTE_ATOMIC)
2397 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC;
2398 if (access & IB_ACCESS_MW_BIND)
2399 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND;
2400
2401 wqe->frmr.l_key = wr->key;
2402 wqe->frmr.length = wr->mr->length;
2403 wqe->frmr.pbl_pg_sz_log = (wr->mr->page_size >> PAGE_SHIFT_4K) - 1;
2404 wqe->frmr.va = wr->mr->iova;
2405 return 0;
2406 }
2407
2408 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev,
2409 const struct ib_send_wr *wr,
2410 struct bnxt_qplib_swqe *wqe)
2411 {
2412 /* Copy the inline data to the data field */
2413 u8 *in_data;
2414 u32 i, sge_len;
2415 void *sge_addr;
2416
2417 in_data = wqe->inline_data;
2418 for (i = 0; i < wr->num_sge; i++) {
2419 sge_addr = (void *)(unsigned long)
2420 wr->sg_list[i].addr;
2421 sge_len = wr->sg_list[i].length;
2422
2423 if ((sge_len + wqe->inline_len) >
2424 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) {
2425 ibdev_err(&rdev->ibdev,
2426 "Inline data size requested > supported value");
2427 return -EINVAL;
2428 }
2429 sge_len = wr->sg_list[i].length;
2430
2431 memcpy(in_data, sge_addr, sge_len);
2432 in_data += wr->sg_list[i].length;
2433 wqe->inline_len += wr->sg_list[i].length;
2434 }
2435 return wqe->inline_len;
2436 }
2437
2438 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev,
2439 const struct ib_send_wr *wr,
2440 struct bnxt_qplib_swqe *wqe)
2441 {
2442 int payload_sz = 0;
2443
2444 if (wr->send_flags & IB_SEND_INLINE)
2445 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe);
2446 else
2447 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list,
2448 wqe->num_sge);
2449
2450 return payload_sz;
2451 }
2452
2453 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp)
2454 {
2455 if ((qp->ib_qp.qp_type == IB_QPT_UD ||
2456 qp->ib_qp.qp_type == IB_QPT_GSI ||
2457 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) &&
2458 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) {
2459 int qp_attr_mask;
2460 struct ib_qp_attr qp_attr;
2461
2462 qp_attr_mask = IB_QP_STATE;
2463 qp_attr.qp_state = IB_QPS_RTS;
2464 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL);
2465 qp->qplib_qp.wqe_cnt = 0;
2466 }
2467 }
2468
2469 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
2470 struct bnxt_re_qp *qp,
2471 const struct ib_send_wr *wr)
2472 {
2473 int rc = 0, payload_sz = 0;
2474 unsigned long flags;
2475
2476 spin_lock_irqsave(&qp->sq_lock, flags);
2477 while (wr) {
2478 struct bnxt_qplib_swqe wqe = {};
2479
2480 /* Common */
2481 wqe.num_sge = wr->num_sge;
2482 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2483 ibdev_err(&rdev->ibdev,
2484 "Limit exceeded for Send SGEs");
2485 rc = -EINVAL;
2486 goto bad;
2487 }
2488
2489 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2490 if (payload_sz < 0) {
2491 rc = -EINVAL;
2492 goto bad;
2493 }
2494 wqe.wr_id = wr->wr_id;
2495
2496 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND;
2497
2498 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2499 if (!rc)
2500 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2501 bad:
2502 if (rc) {
2503 ibdev_err(&rdev->ibdev,
2504 "Post send failed opcode = %#x rc = %d",
2505 wr->opcode, rc);
2506 break;
2507 }
2508 wr = wr->next;
2509 }
2510 bnxt_qplib_post_send_db(&qp->qplib_qp);
2511 bnxt_ud_qp_hw_stall_workaround(qp);
2512 spin_unlock_irqrestore(&qp->sq_lock, flags);
2513 return rc;
2514 }
2515
2516 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr,
2517 const struct ib_send_wr **bad_wr)
2518 {
2519 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2520 struct bnxt_qplib_swqe wqe;
2521 int rc = 0, payload_sz = 0;
2522 unsigned long flags;
2523
2524 spin_lock_irqsave(&qp->sq_lock, flags);
2525 while (wr) {
2526 /* House keeping */
2527 memset(&wqe, 0, sizeof(wqe));
2528
2529 /* Common */
2530 wqe.num_sge = wr->num_sge;
2531 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2532 ibdev_err(&qp->rdev->ibdev,
2533 "Limit exceeded for Send SGEs");
2534 rc = -EINVAL;
2535 goto bad;
2536 }
2537
2538 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2539 if (payload_sz < 0) {
2540 rc = -EINVAL;
2541 goto bad;
2542 }
2543 wqe.wr_id = wr->wr_id;
2544
2545 switch (wr->opcode) {
2546 case IB_WR_SEND:
2547 case IB_WR_SEND_WITH_IMM:
2548 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) {
2549 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
2550 payload_sz);
2551 if (rc)
2552 goto bad;
2553 wqe.rawqp1.lflags |=
2554 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC;
2555 }
2556 switch (wr->send_flags) {
2557 case IB_SEND_IP_CSUM:
2558 wqe.rawqp1.lflags |=
2559 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM;
2560 break;
2561 default:
2562 break;
2563 }
2564 /* fall through */
2565 case IB_WR_SEND_WITH_INV:
2566 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2567 break;
2568 case IB_WR_RDMA_WRITE:
2569 case IB_WR_RDMA_WRITE_WITH_IMM:
2570 case IB_WR_RDMA_READ:
2571 rc = bnxt_re_build_rdma_wqe(wr, &wqe);
2572 break;
2573 case IB_WR_ATOMIC_CMP_AND_SWP:
2574 case IB_WR_ATOMIC_FETCH_AND_ADD:
2575 rc = bnxt_re_build_atomic_wqe(wr, &wqe);
2576 break;
2577 case IB_WR_RDMA_READ_WITH_INV:
2578 ibdev_err(&qp->rdev->ibdev,
2579 "RDMA Read with Invalidate is not supported");
2580 rc = -EINVAL;
2581 goto bad;
2582 case IB_WR_LOCAL_INV:
2583 rc = bnxt_re_build_inv_wqe(wr, &wqe);
2584 break;
2585 case IB_WR_REG_MR:
2586 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
2587 break;
2588 default:
2589 /* Unsupported WRs */
2590 ibdev_err(&qp->rdev->ibdev,
2591 "WR (%#x) is not supported", wr->opcode);
2592 rc = -EINVAL;
2593 goto bad;
2594 }
2595 if (!rc)
2596 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2597 bad:
2598 if (rc) {
2599 ibdev_err(&qp->rdev->ibdev,
2600 "post_send failed op:%#x qps = %#x rc = %d\n",
2601 wr->opcode, qp->qplib_qp.state, rc);
2602 *bad_wr = wr;
2603 break;
2604 }
2605 wr = wr->next;
2606 }
2607 bnxt_qplib_post_send_db(&qp->qplib_qp);
2608 bnxt_ud_qp_hw_stall_workaround(qp);
2609 spin_unlock_irqrestore(&qp->sq_lock, flags);
2610
2611 return rc;
2612 }
2613
2614 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
2615 struct bnxt_re_qp *qp,
2616 const struct ib_recv_wr *wr)
2617 {
2618 struct bnxt_qplib_swqe wqe;
2619 int rc = 0;
2620
2621 memset(&wqe, 0, sizeof(wqe));
2622 while (wr) {
2623 /* House keeping */
2624 memset(&wqe, 0, sizeof(wqe));
2625
2626 /* Common */
2627 wqe.num_sge = wr->num_sge;
2628 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2629 ibdev_err(&rdev->ibdev,
2630 "Limit exceeded for Receive SGEs");
2631 rc = -EINVAL;
2632 break;
2633 }
2634 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
2635 wqe.wr_id = wr->wr_id;
2636 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2637
2638 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2639 if (rc)
2640 break;
2641
2642 wr = wr->next;
2643 }
2644 if (!rc)
2645 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2646 return rc;
2647 }
2648
2649 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr,
2650 const struct ib_recv_wr **bad_wr)
2651 {
2652 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2653 struct bnxt_qplib_swqe wqe;
2654 int rc = 0, payload_sz = 0;
2655 unsigned long flags;
2656 u32 count = 0;
2657
2658 spin_lock_irqsave(&qp->rq_lock, flags);
2659 while (wr) {
2660 /* House keeping */
2661 memset(&wqe, 0, sizeof(wqe));
2662
2663 /* Common */
2664 wqe.num_sge = wr->num_sge;
2665 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2666 ibdev_err(&qp->rdev->ibdev,
2667 "Limit exceeded for Receive SGEs");
2668 rc = -EINVAL;
2669 *bad_wr = wr;
2670 break;
2671 }
2672
2673 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
2674 wr->num_sge);
2675 wqe.wr_id = wr->wr_id;
2676 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2677
2678 if (ib_qp->qp_type == IB_QPT_GSI &&
2679 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI)
2680 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
2681 payload_sz);
2682 if (!rc)
2683 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2684 if (rc) {
2685 *bad_wr = wr;
2686 break;
2687 }
2688
2689 /* Ring DB if the RQEs posted reaches a threshold value */
2690 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) {
2691 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2692 count = 0;
2693 }
2694
2695 wr = wr->next;
2696 }
2697
2698 if (count)
2699 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2700
2701 spin_unlock_irqrestore(&qp->rq_lock, flags);
2702
2703 return rc;
2704 }
2705
2706 /* Completion Queues */
2707 void bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
2708 {
2709 struct bnxt_re_cq *cq;
2710 struct bnxt_qplib_nq *nq;
2711 struct bnxt_re_dev *rdev;
2712
2713 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
2714 rdev = cq->rdev;
2715 nq = cq->qplib_cq.nq;
2716
2717 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2718 ib_umem_release(cq->umem);
2719
2720 atomic_dec(&rdev->cq_count);
2721 nq->budget--;
2722 kfree(cq->cql);
2723 }
2724
2725 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
2726 struct ib_udata *udata)
2727 {
2728 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev);
2729 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
2730 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);
2731 int rc, entries;
2732 int cqe = attr->cqe;
2733 struct bnxt_qplib_nq *nq = NULL;
2734 unsigned int nq_alloc_cnt;
2735
2736 /* Validate CQ fields */
2737 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
2738 ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded");
2739 return -EINVAL;
2740 }
2741
2742 cq->rdev = rdev;
2743 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);
2744
2745 entries = roundup_pow_of_two(cqe + 1);
2746 if (entries > dev_attr->max_cq_wqes + 1)
2747 entries = dev_attr->max_cq_wqes + 1;
2748
2749 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE;
2750 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT;
2751 if (udata) {
2752 struct bnxt_re_cq_req req;
2753 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
2754 udata, struct bnxt_re_ucontext, ib_uctx);
2755 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
2756 rc = -EFAULT;
2757 goto fail;
2758 }
2759
2760 cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va,
2761 entries * sizeof(struct cq_base),
2762 IB_ACCESS_LOCAL_WRITE);
2763 if (IS_ERR(cq->umem)) {
2764 rc = PTR_ERR(cq->umem);
2765 goto fail;
2766 }
2767 cq->qplib_cq.sg_info.sghead = cq->umem->sg_head.sgl;
2768 cq->qplib_cq.sg_info.npages = ib_umem_num_pages(cq->umem);
2769 cq->qplib_cq.sg_info.nmap = cq->umem->nmap;
2770 cq->qplib_cq.dpi = &uctx->dpi;
2771 } else {
2772 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL);
2773 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe),
2774 GFP_KERNEL);
2775 if (!cq->cql) {
2776 rc = -ENOMEM;
2777 goto fail;
2778 }
2779
2780 cq->qplib_cq.dpi = &rdev->dpi_privileged;
2781 }
2782 /*
2783 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a
2784 * used for getting the NQ index.
2785 */
2786 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt);
2787 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)];
2788 cq->qplib_cq.max_wqe = entries;
2789 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id;
2790 cq->qplib_cq.nq = nq;
2791
2792 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq);
2793 if (rc) {
2794 ibdev_err(&rdev->ibdev, "Failed to create HW CQ");
2795 goto fail;
2796 }
2797
2798 cq->ib_cq.cqe = entries;
2799 cq->cq_period = cq->qplib_cq.period;
2800 nq->budget++;
2801
2802 atomic_inc(&rdev->cq_count);
2803 spin_lock_init(&cq->cq_lock);
2804
2805 if (udata) {
2806 struct bnxt_re_cq_resp resp;
2807
2808 resp.cqid = cq->qplib_cq.id;
2809 resp.tail = cq->qplib_cq.hwq.cons;
2810 resp.phase = cq->qplib_cq.period;
2811 resp.rsvd = 0;
2812 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
2813 if (rc) {
2814 ibdev_err(&rdev->ibdev, "Failed to copy CQ udata");
2815 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2816 goto c2fail;
2817 }
2818 }
2819
2820 return 0;
2821
2822 c2fail:
2823 ib_umem_release(cq->umem);
2824 fail:
2825 kfree(cq->cql);
2826 return rc;
2827 }
2828
2829 static u8 __req_to_ib_wc_status(u8 qstatus)
2830 {
2831 switch (qstatus) {
2832 case CQ_REQ_STATUS_OK:
2833 return IB_WC_SUCCESS;
2834 case CQ_REQ_STATUS_BAD_RESPONSE_ERR:
2835 return IB_WC_BAD_RESP_ERR;
2836 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR:
2837 return IB_WC_LOC_LEN_ERR;
2838 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR:
2839 return IB_WC_LOC_QP_OP_ERR;
2840 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR:
2841 return IB_WC_LOC_PROT_ERR;
2842 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR:
2843 return IB_WC_GENERAL_ERR;
2844 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR:
2845 return IB_WC_REM_INV_REQ_ERR;
2846 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR:
2847 return IB_WC_REM_ACCESS_ERR;
2848 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR:
2849 return IB_WC_REM_OP_ERR;
2850 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR:
2851 return IB_WC_RNR_RETRY_EXC_ERR;
2852 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR:
2853 return IB_WC_RETRY_EXC_ERR;
2854 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR:
2855 return IB_WC_WR_FLUSH_ERR;
2856 default:
2857 return IB_WC_GENERAL_ERR;
2858 }
2859 return 0;
2860 }
2861
2862 static u8 __rawqp1_to_ib_wc_status(u8 qstatus)
2863 {
2864 switch (qstatus) {
2865 case CQ_RES_RAWETH_QP1_STATUS_OK:
2866 return IB_WC_SUCCESS;
2867 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR:
2868 return IB_WC_LOC_ACCESS_ERR;
2869 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR:
2870 return IB_WC_LOC_LEN_ERR;
2871 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR:
2872 return IB_WC_LOC_PROT_ERR;
2873 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR:
2874 return IB_WC_LOC_QP_OP_ERR;
2875 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR:
2876 return IB_WC_GENERAL_ERR;
2877 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR:
2878 return IB_WC_WR_FLUSH_ERR;
2879 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR:
2880 return IB_WC_WR_FLUSH_ERR;
2881 default:
2882 return IB_WC_GENERAL_ERR;
2883 }
2884 }
2885
2886 static u8 __rc_to_ib_wc_status(u8 qstatus)
2887 {
2888 switch (qstatus) {
2889 case CQ_RES_RC_STATUS_OK:
2890 return IB_WC_SUCCESS;
2891 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR:
2892 return IB_WC_LOC_ACCESS_ERR;
2893 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR:
2894 return IB_WC_LOC_LEN_ERR;
2895 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR:
2896 return IB_WC_LOC_PROT_ERR;
2897 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR:
2898 return IB_WC_LOC_QP_OP_ERR;
2899 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR:
2900 return IB_WC_GENERAL_ERR;
2901 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR:
2902 return IB_WC_REM_INV_REQ_ERR;
2903 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR:
2904 return IB_WC_WR_FLUSH_ERR;
2905 case CQ_RES_RC_STATUS_HW_FLUSH_ERR:
2906 return IB_WC_WR_FLUSH_ERR;
2907 default:
2908 return IB_WC_GENERAL_ERR;
2909 }
2910 }
2911
2912 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
2913 {
2914 switch (cqe->type) {
2915 case BNXT_QPLIB_SWQE_TYPE_SEND:
2916 wc->opcode = IB_WC_SEND;
2917 break;
2918 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
2919 wc->opcode = IB_WC_SEND;
2920 wc->wc_flags |= IB_WC_WITH_IMM;
2921 break;
2922 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
2923 wc->opcode = IB_WC_SEND;
2924 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2925 break;
2926 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
2927 wc->opcode = IB_WC_RDMA_WRITE;
2928 break;
2929 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
2930 wc->opcode = IB_WC_RDMA_WRITE;
2931 wc->wc_flags |= IB_WC_WITH_IMM;
2932 break;
2933 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
2934 wc->opcode = IB_WC_RDMA_READ;
2935 break;
2936 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
2937 wc->opcode = IB_WC_COMP_SWAP;
2938 break;
2939 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
2940 wc->opcode = IB_WC_FETCH_ADD;
2941 break;
2942 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
2943 wc->opcode = IB_WC_LOCAL_INV;
2944 break;
2945 case BNXT_QPLIB_SWQE_TYPE_REG_MR:
2946 wc->opcode = IB_WC_REG_MR;
2947 break;
2948 default:
2949 wc->opcode = IB_WC_SEND;
2950 break;
2951 }
2952
2953 wc->status = __req_to_ib_wc_status(cqe->status);
2954 }
2955
2956 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
2957 u16 raweth_qp1_flags2)
2958 {
2959 bool is_ipv6 = false, is_ipv4 = false;
2960
2961 /* raweth_qp1_flags Bit 9-6 indicates itype */
2962 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
2963 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
2964 return -1;
2965
2966 if (raweth_qp1_flags2 &
2967 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
2968 raweth_qp1_flags2 &
2969 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
2970 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
2971 (raweth_qp1_flags2 &
2972 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
2973 (is_ipv6 = true) : (is_ipv4 = true);
2974 return ((is_ipv6) ?
2975 BNXT_RE_ROCEV2_IPV6_PACKET :
2976 BNXT_RE_ROCEV2_IPV4_PACKET);
2977 } else {
2978 return BNXT_RE_ROCE_V1_PACKET;
2979 }
2980 }
2981
2982 static int bnxt_re_to_ib_nw_type(int nw_type)
2983 {
2984 u8 nw_hdr_type = 0xFF;
2985
2986 switch (nw_type) {
2987 case BNXT_RE_ROCE_V1_PACKET:
2988 nw_hdr_type = RDMA_NETWORK_ROCE_V1;
2989 break;
2990 case BNXT_RE_ROCEV2_IPV4_PACKET:
2991 nw_hdr_type = RDMA_NETWORK_IPV4;
2992 break;
2993 case BNXT_RE_ROCEV2_IPV6_PACKET:
2994 nw_hdr_type = RDMA_NETWORK_IPV6;
2995 break;
2996 }
2997 return nw_hdr_type;
2998 }
2999
3000 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev,
3001 void *rq_hdr_buf)
3002 {
3003 u8 *tmp_buf = NULL;
3004 struct ethhdr *eth_hdr;
3005 u16 eth_type;
3006 bool rc = false;
3007
3008 tmp_buf = (u8 *)rq_hdr_buf;
3009 /*
3010 * If dest mac is not same as I/F mac, this could be a
3011 * loopback address or multicast address, check whether
3012 * it is a loopback packet
3013 */
3014 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) {
3015 tmp_buf += 4;
3016 /* Check the ether type */
3017 eth_hdr = (struct ethhdr *)tmp_buf;
3018 eth_type = ntohs(eth_hdr->h_proto);
3019 switch (eth_type) {
3020 case ETH_P_IBOE:
3021 rc = true;
3022 break;
3023 case ETH_P_IP:
3024 case ETH_P_IPV6: {
3025 u32 len;
3026 struct udphdr *udp_hdr;
3027
3028 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) :
3029 sizeof(struct ipv6hdr));
3030 tmp_buf += sizeof(struct ethhdr) + len;
3031 udp_hdr = (struct udphdr *)tmp_buf;
3032 if (ntohs(udp_hdr->dest) ==
3033 ROCE_V2_UDP_DPORT)
3034 rc = true;
3035 break;
3036 }
3037 default:
3038 break;
3039 }
3040 }
3041
3042 return rc;
3043 }
3044
3045 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp,
3046 struct bnxt_qplib_cqe *cqe)
3047 {
3048 struct bnxt_re_dev *rdev = gsi_qp->rdev;
3049 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3050 struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp;
3051 struct bnxt_re_ah *gsi_sah;
3052 struct ib_send_wr *swr;
3053 struct ib_ud_wr udwr;
3054 struct ib_recv_wr rwr;
3055 int pkt_type = 0;
3056 u32 tbl_idx;
3057 void *rq_hdr_buf;
3058 dma_addr_t rq_hdr_buf_map;
3059 dma_addr_t shrq_hdr_buf_map;
3060 u32 offset = 0;
3061 u32 skip_bytes = 0;
3062 struct ib_sge s_sge[2];
3063 struct ib_sge r_sge[2];
3064 int rc;
3065
3066 memset(&udwr, 0, sizeof(udwr));
3067 memset(&rwr, 0, sizeof(rwr));
3068 memset(&s_sge, 0, sizeof(s_sge));
3069 memset(&r_sge, 0, sizeof(r_sge));
3070
3071 swr = &udwr.wr;
3072 tbl_idx = cqe->wr_id;
3073
3074 rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf +
3075 (tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size);
3076 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3077 tbl_idx);
3078
3079 /* Shadow QP header buffer */
3080 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3081 tbl_idx);
3082 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3083
3084 /* Store this cqe */
3085 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe));
3086 sqp_entry->qp1_qp = gsi_qp;
3087
3088 /* Find packet type from the cqe */
3089
3090 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags,
3091 cqe->raweth_qp1_flags2);
3092 if (pkt_type < 0) {
3093 ibdev_err(&rdev->ibdev, "Invalid packet\n");
3094 return -EINVAL;
3095 }
3096
3097 /* Adjust the offset for the user buffer and post in the rq */
3098
3099 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET)
3100 offset = 20;
3101
3102 /*
3103 * QP1 loopback packet has 4 bytes of internal header before
3104 * ether header. Skip these four bytes.
3105 */
3106 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf))
3107 skip_bytes = 4;
3108
3109 /* First send SGE . Skip the ether header*/
3110 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
3111 + skip_bytes;
3112 s_sge[0].lkey = 0xFFFFFFFF;
3113 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 :
3114 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
3115
3116 /* Second Send SGE */
3117 s_sge[1].addr = s_sge[0].addr + s_sge[0].length +
3118 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE;
3119 if (pkt_type != BNXT_RE_ROCE_V1_PACKET)
3120 s_sge[1].addr += 8;
3121 s_sge[1].lkey = 0xFFFFFFFF;
3122 s_sge[1].length = 256;
3123
3124 /* First recv SGE */
3125
3126 r_sge[0].addr = shrq_hdr_buf_map;
3127 r_sge[0].lkey = 0xFFFFFFFF;
3128 r_sge[0].length = 40;
3129
3130 r_sge[1].addr = sqp_entry->sge.addr + offset;
3131 r_sge[1].lkey = sqp_entry->sge.lkey;
3132 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset;
3133
3134 /* Create receive work request */
3135 rwr.num_sge = 2;
3136 rwr.sg_list = r_sge;
3137 rwr.wr_id = tbl_idx;
3138 rwr.next = NULL;
3139
3140 rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr);
3141 if (rc) {
3142 ibdev_err(&rdev->ibdev,
3143 "Failed to post Rx buffers to shadow QP");
3144 return -ENOMEM;
3145 }
3146
3147 swr->num_sge = 2;
3148 swr->sg_list = s_sge;
3149 swr->wr_id = tbl_idx;
3150 swr->opcode = IB_WR_SEND;
3151 swr->next = NULL;
3152 gsi_sah = rdev->gsi_ctx.gsi_sah;
3153 udwr.ah = &gsi_sah->ib_ah;
3154 udwr.remote_qpn = gsi_sqp->qplib_qp.id;
3155 udwr.remote_qkey = gsi_sqp->qplib_qp.qkey;
3156
3157 /* post data received in the send queue */
3158 rc = bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr);
3159
3160 return 0;
3161 }
3162
3163 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
3164 struct bnxt_qplib_cqe *cqe)
3165 {
3166 wc->opcode = IB_WC_RECV;
3167 wc->status = __rawqp1_to_ib_wc_status(cqe->status);
3168 wc->wc_flags |= IB_WC_GRH;
3169 }
3170
3171 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe,
3172 u16 *vid, u8 *sl)
3173 {
3174 bool ret = false;
3175 u32 metadata;
3176 u16 tpid;
3177
3178 metadata = orig_cqe->raweth_qp1_metadata;
3179 if (orig_cqe->raweth_qp1_flags2 &
3180 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) {
3181 tpid = ((metadata &
3182 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >>
3183 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT);
3184 if (tpid == ETH_P_8021Q) {
3185 *vid = metadata &
3186 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK;
3187 *sl = (metadata &
3188 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >>
3189 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT;
3190 ret = true;
3191 }
3192 }
3193
3194 return ret;
3195 }
3196
3197 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
3198 struct bnxt_qplib_cqe *cqe)
3199 {
3200 wc->opcode = IB_WC_RECV;
3201 wc->status = __rc_to_ib_wc_status(cqe->status);
3202
3203 if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
3204 wc->wc_flags |= IB_WC_WITH_IMM;
3205 if (cqe->flags & CQ_RES_RC_FLAGS_INV)
3206 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3207 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
3208 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
3209 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3210 }
3211
3212 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp,
3213 struct ib_wc *wc,
3214 struct bnxt_qplib_cqe *cqe)
3215 {
3216 struct bnxt_re_dev *rdev = gsi_sqp->rdev;
3217 struct bnxt_re_qp *gsi_qp = NULL;
3218 struct bnxt_qplib_cqe *orig_cqe = NULL;
3219 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3220 int nw_type;
3221 u32 tbl_idx;
3222 u16 vlan_id;
3223 u8 sl;
3224
3225 tbl_idx = cqe->wr_id;
3226
3227 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3228 gsi_qp = sqp_entry->qp1_qp;
3229 orig_cqe = &sqp_entry->cqe;
3230
3231 wc->wr_id = sqp_entry->wrid;
3232 wc->byte_len = orig_cqe->length;
3233 wc->qp = &gsi_qp->ib_qp;
3234
3235 wc->ex.imm_data = orig_cqe->immdata;
3236 wc->src_qp = orig_cqe->src_qp;
3237 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
3238 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) {
3239 wc->vlan_id = vlan_id;
3240 wc->sl = sl;
3241 wc->wc_flags |= IB_WC_WITH_VLAN;
3242 }
3243 wc->port_num = 1;
3244 wc->vendor_err = orig_cqe->status;
3245
3246 wc->opcode = IB_WC_RECV;
3247 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status);
3248 wc->wc_flags |= IB_WC_GRH;
3249
3250 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags,
3251 orig_cqe->raweth_qp1_flags2);
3252 if (nw_type >= 0) {
3253 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3254 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3255 }
3256 }
3257
3258 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp,
3259 struct ib_wc *wc,
3260 struct bnxt_qplib_cqe *cqe)
3261 {
3262 u8 nw_type;
3263
3264 wc->opcode = IB_WC_RECV;
3265 wc->status = __rc_to_ib_wc_status(cqe->status);
3266
3267 if (cqe->flags & CQ_RES_UD_FLAGS_IMM)
3268 wc->wc_flags |= IB_WC_WITH_IMM;
3269 /* report only on GSI QP for Thor */
3270 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) {
3271 wc->wc_flags |= IB_WC_GRH;
3272 memcpy(wc->smac, cqe->smac, ETH_ALEN);
3273 wc->wc_flags |= IB_WC_WITH_SMAC;
3274 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) {
3275 wc->vlan_id = (cqe->cfa_meta & 0xFFF);
3276 if (wc->vlan_id < 0x1000)
3277 wc->wc_flags |= IB_WC_WITH_VLAN;
3278 }
3279 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >>
3280 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT;
3281 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3282 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3283 }
3284
3285 }
3286
3287 static int send_phantom_wqe(struct bnxt_re_qp *qp)
3288 {
3289 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp;
3290 unsigned long flags;
3291 int rc = 0;
3292
3293 spin_lock_irqsave(&qp->sq_lock, flags);
3294
3295 rc = bnxt_re_bind_fence_mw(lib_qp);
3296 if (!rc) {
3297 lib_qp->sq.phantom_wqe_cnt++;
3298 ibdev_dbg(&qp->rdev->ibdev,
3299 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n",
3300 lib_qp->id, lib_qp->sq.hwq.prod,
3301 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq),
3302 lib_qp->sq.phantom_wqe_cnt);
3303 }
3304
3305 spin_unlock_irqrestore(&qp->sq_lock, flags);
3306 return rc;
3307 }
3308
3309 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc)
3310 {
3311 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3312 struct bnxt_re_qp *qp, *sh_qp;
3313 struct bnxt_qplib_cqe *cqe;
3314 int i, ncqe, budget;
3315 struct bnxt_qplib_q *sq;
3316 struct bnxt_qplib_qp *lib_qp;
3317 u32 tbl_idx;
3318 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3319 unsigned long flags;
3320
3321 spin_lock_irqsave(&cq->cq_lock, flags);
3322 budget = min_t(u32, num_entries, cq->max_cql);
3323 num_entries = budget;
3324 if (!cq->cql) {
3325 ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use");
3326 goto exit;
3327 }
3328 cqe = &cq->cql[0];
3329 while (budget) {
3330 lib_qp = NULL;
3331 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp);
3332 if (lib_qp) {
3333 sq = &lib_qp->sq;
3334 if (sq->send_phantom) {
3335 qp = container_of(lib_qp,
3336 struct bnxt_re_qp, qplib_qp);
3337 if (send_phantom_wqe(qp) == -ENOMEM)
3338 ibdev_err(&cq->rdev->ibdev,
3339 "Phantom failed! Scheduled to send again\n");
3340 else
3341 sq->send_phantom = false;
3342 }
3343 }
3344 if (ncqe < budget)
3345 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq,
3346 cqe + ncqe,
3347 budget - ncqe);
3348
3349 if (!ncqe)
3350 break;
3351
3352 for (i = 0; i < ncqe; i++, cqe++) {
3353 /* Transcribe each qplib_wqe back to ib_wc */
3354 memset(wc, 0, sizeof(*wc));
3355
3356 wc->wr_id = cqe->wr_id;
3357 wc->byte_len = cqe->length;
3358 qp = container_of
3359 ((struct bnxt_qplib_qp *)
3360 (unsigned long)(cqe->qp_handle),
3361 struct bnxt_re_qp, qplib_qp);
3362 if (!qp) {
3363 ibdev_err(&cq->rdev->ibdev, "POLL CQ : bad QP handle");
3364 continue;
3365 }
3366 wc->qp = &qp->ib_qp;
3367 wc->ex.imm_data = cqe->immdata;
3368 wc->src_qp = cqe->src_qp;
3369 memcpy(wc->smac, cqe->smac, ETH_ALEN);
3370 wc->port_num = 1;
3371 wc->vendor_err = cqe->status;
3372
3373 switch (cqe->opcode) {
3374 case CQ_BASE_CQE_TYPE_REQ:
3375 sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3376 if (sh_qp &&
3377 qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3378 /* Handle this completion with
3379 * the stored completion
3380 */
3381 memset(wc, 0, sizeof(*wc));
3382 continue;
3383 }
3384 bnxt_re_process_req_wc(wc, cqe);
3385 break;
3386 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
3387 if (!cqe->status) {
3388 int rc = 0;
3389
3390 rc = bnxt_re_process_raw_qp_pkt_rx
3391 (qp, cqe);
3392 if (!rc) {
3393 memset(wc, 0, sizeof(*wc));
3394 continue;
3395 }
3396 cqe->status = -1;
3397 }
3398 /* Errors need not be looped back.
3399 * But change the wr_id to the one
3400 * stored in the table
3401 */
3402 tbl_idx = cqe->wr_id;
3403 sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx];
3404 wc->wr_id = sqp_entry->wrid;
3405 bnxt_re_process_res_rawqp1_wc(wc, cqe);
3406 break;
3407 case CQ_BASE_CQE_TYPE_RES_RC:
3408 bnxt_re_process_res_rc_wc(wc, cqe);
3409 break;
3410 case CQ_BASE_CQE_TYPE_RES_UD:
3411 sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3412 if (sh_qp &&
3413 qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3414 /* Handle this completion with
3415 * the stored completion
3416 */
3417 if (cqe->status) {
3418 continue;
3419 } else {
3420 bnxt_re_process_res_shadow_qp_wc
3421 (qp, wc, cqe);
3422 break;
3423 }
3424 }
3425 bnxt_re_process_res_ud_wc(qp, wc, cqe);
3426 break;
3427 default:
3428 ibdev_err(&cq->rdev->ibdev,
3429 "POLL CQ : type 0x%x not handled",
3430 cqe->opcode);
3431 continue;
3432 }
3433 wc++;
3434 budget--;
3435 }
3436 }
3437 exit:
3438 spin_unlock_irqrestore(&cq->cq_lock, flags);
3439 return num_entries - budget;
3440 }
3441
3442 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
3443 enum ib_cq_notify_flags ib_cqn_flags)
3444 {
3445 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3446 int type = 0, rc = 0;
3447 unsigned long flags;
3448
3449 spin_lock_irqsave(&cq->cq_lock, flags);
3450 /* Trigger on the very next completion */
3451 if (ib_cqn_flags & IB_CQ_NEXT_COMP)
3452 type = DBC_DBC_TYPE_CQ_ARMALL;
3453 /* Trigger on the next solicited completion */
3454 else if (ib_cqn_flags & IB_CQ_SOLICITED)
3455 type = DBC_DBC_TYPE_CQ_ARMSE;
3456
3457 /* Poll to see if there are missed events */
3458 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
3459 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) {
3460 rc = 1;
3461 goto exit;
3462 }
3463 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
3464
3465 exit:
3466 spin_unlock_irqrestore(&cq->cq_lock, flags);
3467 return rc;
3468 }
3469
3470 /* Memory Regions */
3471 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags)
3472 {
3473 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3474 struct bnxt_re_dev *rdev = pd->rdev;
3475 struct bnxt_re_mr *mr;
3476 u64 pbl = 0;
3477 int rc;
3478
3479 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3480 if (!mr)
3481 return ERR_PTR(-ENOMEM);
3482
3483 mr->rdev = rdev;
3484 mr->qplib_mr.pd = &pd->qplib_pd;
3485 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3486 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3487
3488 /* Allocate and register 0 as the address */
3489 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3490 if (rc)
3491 goto fail;
3492
3493 mr->qplib_mr.hwq.level = PBL_LVL_MAX;
3494 mr->qplib_mr.total_size = -1; /* Infinte length */
3495 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl, 0, false,
3496 PAGE_SIZE);
3497 if (rc)
3498 goto fail_mr;
3499
3500 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3501 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ |
3502 IB_ACCESS_REMOTE_ATOMIC))
3503 mr->ib_mr.rkey = mr->ib_mr.lkey;
3504 atomic_inc(&rdev->mr_count);
3505
3506 return &mr->ib_mr;
3507
3508 fail_mr:
3509 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3510 fail:
3511 kfree(mr);
3512 return ERR_PTR(rc);
3513 }
3514
3515 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
3516 {
3517 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3518 struct bnxt_re_dev *rdev = mr->rdev;
3519 int rc;
3520
3521 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3522 if (rc) {
3523 ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc);
3524 return rc;
3525 }
3526
3527 if (mr->pages) {
3528 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
3529 &mr->qplib_frpl);
3530 kfree(mr->pages);
3531 mr->npages = 0;
3532 mr->pages = NULL;
3533 }
3534 ib_umem_release(mr->ib_umem);
3535
3536 kfree(mr);
3537 atomic_dec(&rdev->mr_count);
3538 return rc;
3539 }
3540
3541 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr)
3542 {
3543 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3544
3545 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs))
3546 return -ENOMEM;
3547
3548 mr->pages[mr->npages++] = addr;
3549 return 0;
3550 }
3551
3552 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents,
3553 unsigned int *sg_offset)
3554 {
3555 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3556
3557 mr->npages = 0;
3558 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page);
3559 }
3560
3561 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type,
3562 u32 max_num_sg, struct ib_udata *udata)
3563 {
3564 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3565 struct bnxt_re_dev *rdev = pd->rdev;
3566 struct bnxt_re_mr *mr = NULL;
3567 int rc;
3568
3569 if (type != IB_MR_TYPE_MEM_REG) {
3570 ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type);
3571 return ERR_PTR(-EINVAL);
3572 }
3573 if (max_num_sg > MAX_PBL_LVL_1_PGS)
3574 return ERR_PTR(-EINVAL);
3575
3576 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3577 if (!mr)
3578 return ERR_PTR(-ENOMEM);
3579
3580 mr->rdev = rdev;
3581 mr->qplib_mr.pd = &pd->qplib_pd;
3582 mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR;
3583 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3584
3585 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3586 if (rc)
3587 goto bail;
3588
3589 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3590 mr->ib_mr.rkey = mr->ib_mr.lkey;
3591
3592 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
3593 if (!mr->pages) {
3594 rc = -ENOMEM;
3595 goto fail;
3596 }
3597 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res,
3598 &mr->qplib_frpl, max_num_sg);
3599 if (rc) {
3600 ibdev_err(&rdev->ibdev,
3601 "Failed to allocate HW FR page list");
3602 goto fail_mr;
3603 }
3604
3605 atomic_inc(&rdev->mr_count);
3606 return &mr->ib_mr;
3607
3608 fail_mr:
3609 kfree(mr->pages);
3610 fail:
3611 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3612 bail:
3613 kfree(mr);
3614 return ERR_PTR(rc);
3615 }
3616
3617 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type,
3618 struct ib_udata *udata)
3619 {
3620 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3621 struct bnxt_re_dev *rdev = pd->rdev;
3622 struct bnxt_re_mw *mw;
3623 int rc;
3624
3625 mw = kzalloc(sizeof(*mw), GFP_KERNEL);
3626 if (!mw)
3627 return ERR_PTR(-ENOMEM);
3628 mw->rdev = rdev;
3629 mw->qplib_mw.pd = &pd->qplib_pd;
3630
3631 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ?
3632 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 :
3633 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B);
3634 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw);
3635 if (rc) {
3636 ibdev_err(&rdev->ibdev, "Allocate MW failed!");
3637 goto fail;
3638 }
3639 mw->ib_mw.rkey = mw->qplib_mw.rkey;
3640
3641 atomic_inc(&rdev->mw_count);
3642 return &mw->ib_mw;
3643
3644 fail:
3645 kfree(mw);
3646 return ERR_PTR(rc);
3647 }
3648
3649 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw)
3650 {
3651 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw);
3652 struct bnxt_re_dev *rdev = mw->rdev;
3653 int rc;
3654
3655 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw);
3656 if (rc) {
3657 ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc);
3658 return rc;
3659 }
3660
3661 kfree(mw);
3662 atomic_dec(&rdev->mw_count);
3663 return rc;
3664 }
3665
3666 static int bnxt_re_page_size_ok(int page_shift)
3667 {
3668 switch (page_shift) {
3669 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K:
3670 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K:
3671 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K:
3672 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M:
3673 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K:
3674 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M:
3675 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M:
3676 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G:
3677 return 1;
3678 default:
3679 return 0;
3680 }
3681 }
3682
3683 static int fill_umem_pbl_tbl(struct ib_umem *umem, u64 *pbl_tbl_orig,
3684 int page_shift)
3685 {
3686 u64 *pbl_tbl = pbl_tbl_orig;
3687 u64 page_size = BIT_ULL(page_shift);
3688 struct ib_block_iter biter;
3689
3690 rdma_for_each_block(umem->sg_head.sgl, &biter, umem->nmap, page_size)
3691 *pbl_tbl++ = rdma_block_iter_dma_address(&biter);
3692
3693 return pbl_tbl - pbl_tbl_orig;
3694 }
3695
3696 /* uverbs */
3697 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
3698 u64 virt_addr, int mr_access_flags,
3699 struct ib_udata *udata)
3700 {
3701 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3702 struct bnxt_re_dev *rdev = pd->rdev;
3703 struct bnxt_re_mr *mr;
3704 struct ib_umem *umem;
3705 u64 *pbl_tbl = NULL;
3706 int umem_pgs, page_shift, rc;
3707
3708 if (length > BNXT_RE_MAX_MR_SIZE) {
3709 ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n",
3710 length, BNXT_RE_MAX_MR_SIZE);
3711 return ERR_PTR(-ENOMEM);
3712 }
3713
3714 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3715 if (!mr)
3716 return ERR_PTR(-ENOMEM);
3717
3718 mr->rdev = rdev;
3719 mr->qplib_mr.pd = &pd->qplib_pd;
3720 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3721 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR;
3722
3723 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3724 if (rc) {
3725 ibdev_err(&rdev->ibdev, "Failed to allocate MR");
3726 goto free_mr;
3727 }
3728 /* The fixed portion of the rkey is the same as the lkey */
3729 mr->ib_mr.rkey = mr->qplib_mr.rkey;
3730
3731 umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags);
3732 if (IS_ERR(umem)) {
3733 ibdev_err(&rdev->ibdev, "Failed to get umem");
3734 rc = -EFAULT;
3735 goto free_mrw;
3736 }
3737 mr->ib_umem = umem;
3738
3739 mr->qplib_mr.va = virt_addr;
3740 umem_pgs = ib_umem_page_count(umem);
3741 if (!umem_pgs) {
3742 ibdev_err(&rdev->ibdev, "umem is invalid!");
3743 rc = -EINVAL;
3744 goto free_umem;
3745 }
3746 mr->qplib_mr.total_size = length;
3747
3748 pbl_tbl = kcalloc(umem_pgs, sizeof(u64 *), GFP_KERNEL);
3749 if (!pbl_tbl) {
3750 rc = -ENOMEM;
3751 goto free_umem;
3752 }
3753
3754 page_shift = __ffs(ib_umem_find_best_pgsz(umem,
3755 BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M,
3756 virt_addr));
3757
3758 if (!bnxt_re_page_size_ok(page_shift)) {
3759 ibdev_err(&rdev->ibdev, "umem page size unsupported!");
3760 rc = -EFAULT;
3761 goto fail;
3762 }
3763
3764 if (page_shift == BNXT_RE_PAGE_SHIFT_4K &&
3765 length > BNXT_RE_MAX_MR_SIZE_LOW) {
3766 ibdev_err(&rdev->ibdev, "Requested MR Sz:%llu Max sup:%llu",
3767 length, (u64)BNXT_RE_MAX_MR_SIZE_LOW);
3768 rc = -EINVAL;
3769 goto fail;
3770 }
3771
3772 /* Map umem buf ptrs to the PBL */
3773 umem_pgs = fill_umem_pbl_tbl(umem, pbl_tbl, page_shift);
3774 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, pbl_tbl,
3775 umem_pgs, false, 1 << page_shift);
3776 if (rc) {
3777 ibdev_err(&rdev->ibdev, "Failed to register user MR");
3778 goto fail;
3779 }
3780
3781 kfree(pbl_tbl);
3782
3783 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3784 mr->ib_mr.rkey = mr->qplib_mr.lkey;
3785 atomic_inc(&rdev->mr_count);
3786
3787 return &mr->ib_mr;
3788 fail:
3789 kfree(pbl_tbl);
3790 free_umem:
3791 ib_umem_release(umem);
3792 free_mrw:
3793 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3794 free_mr:
3795 kfree(mr);
3796 return ERR_PTR(rc);
3797 }
3798
3799 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata)
3800 {
3801 struct ib_device *ibdev = ctx->device;
3802 struct bnxt_re_ucontext *uctx =
3803 container_of(ctx, struct bnxt_re_ucontext, ib_uctx);
3804 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
3805 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
3806 struct bnxt_re_uctx_resp resp;
3807 u32 chip_met_rev_num = 0;
3808 int rc;
3809
3810 ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver);
3811
3812 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) {
3813 ibdev_dbg(ibdev, " is different from the device %d ",
3814 BNXT_RE_ABI_VERSION);
3815 return -EPERM;
3816 }
3817
3818 uctx->rdev = rdev;
3819
3820 uctx->shpg = (void *)__get_free_page(GFP_KERNEL);
3821 if (!uctx->shpg) {
3822 rc = -ENOMEM;
3823 goto fail;
3824 }
3825 spin_lock_init(&uctx->sh_lock);
3826
3827 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX;
3828 chip_met_rev_num = rdev->chip_ctx->chip_num;
3829 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) <<
3830 BNXT_RE_CHIP_ID0_CHIP_REV_SFT;
3831 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) <<
3832 BNXT_RE_CHIP_ID0_CHIP_MET_SFT;
3833 resp.chip_id0 = chip_met_rev_num;
3834 /* Future extension of chip info */
3835 resp.chip_id1 = 0;
3836 /*Temp, Use xa_alloc instead */
3837 resp.dev_id = rdev->en_dev->pdev->devfn;
3838 resp.max_qp = rdev->qplib_ctx.qpc_count;
3839 resp.pg_size = PAGE_SIZE;
3840 resp.cqe_sz = sizeof(struct cq_base);
3841 resp.max_cqd = dev_attr->max_cq_wqes;
3842 resp.rsvd = 0;
3843
3844 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
3845 if (rc) {
3846 ibdev_err(ibdev, "Failed to copy user context");
3847 rc = -EFAULT;
3848 goto cfail;
3849 }
3850
3851 return 0;
3852 cfail:
3853 free_page((unsigned long)uctx->shpg);
3854 uctx->shpg = NULL;
3855 fail:
3856 return rc;
3857 }
3858
3859 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)
3860 {
3861 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3862 struct bnxt_re_ucontext,
3863 ib_uctx);
3864
3865 struct bnxt_re_dev *rdev = uctx->rdev;
3866
3867 if (uctx->shpg)
3868 free_page((unsigned long)uctx->shpg);
3869
3870 if (uctx->dpi.dbr) {
3871 /* Free DPI only if this is the first PD allocated by the
3872 * application and mark the context dpi as NULL
3873 */
3874 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
3875 &rdev->qplib_res.dpi_tbl, &uctx->dpi);
3876 uctx->dpi.dbr = NULL;
3877 }
3878 }
3879
3880 /* Helper function to mmap the virtual memory from user app */
3881 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)
3882 {
3883 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3884 struct bnxt_re_ucontext,
3885 ib_uctx);
3886 struct bnxt_re_dev *rdev = uctx->rdev;
3887 u64 pfn;
3888
3889 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
3890 return -EINVAL;
3891
3892 if (vma->vm_pgoff) {
3893 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
3894 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
3895 PAGE_SIZE, vma->vm_page_prot)) {
3896 ibdev_err(&rdev->ibdev, "Failed to map DPI");
3897 return -EAGAIN;
3898 }
3899 } else {
3900 pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT;
3901 if (remap_pfn_range(vma, vma->vm_start,
3902 pfn, PAGE_SIZE, vma->vm_page_prot)) {
3903 ibdev_err(&rdev->ibdev, "Failed to map shared page");
3904 return -EAGAIN;
3905 }
3906 }
3907
3908 return 0;
3909 }
Linux with added FPC-III support