drivers/infiniband/hw/bnxt_re/qplib_rcfw.h

   1 /*
   2  * Broadcom NetXtreme-E RoCE driver.
   3  *
   4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
   5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * BSD license below:
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  *
  36  * Description: RDMA Controller HW interface (header)
  37  */
  38
  39 #ifndef __BNXT_QPLIB_RCFW_H__
  40 #define __BNXT_QPLIB_RCFW_H__
  41
  42 #define RCFW_CMDQ_TRIG_VAL              1
  43 #define RCFW_COMM_PCI_BAR_REGION        0
  44 #define RCFW_COMM_CONS_PCI_BAR_REGION   2
  45 #define RCFW_COMM_BASE_OFFSET           0x600
  46 #define RCFW_PF_COMM_PROD_OFFSET        0xc
  47 #define RCFW_VF_COMM_PROD_OFFSET        0xc
  48 #define RCFW_COMM_TRIG_OFFSET           0x100
  49 #define RCFW_COMM_SIZE                  0x104
  50
  51 #define RCFW_DBR_PCI_BAR_REGION         2
  52 #define RCFW_DBR_BASE_PAGE_SHIFT        12
  53
  54 #define RCFW_CMD_PREP(req, CMD, cmd_flags)                              \
  55         do {                                                            \
  56                 memset(&(req), 0, sizeof((req)));                       \
  57                 (req).opcode = CMDQ_BASE_OPCODE_##CMD;                  \
  58                 (req).cmd_size = sizeof((req));                         \
  59                 (req).flags = cpu_to_le16(cmd_flags);                   \
  60         } while (0)
  61
  62 #define RCFW_CMD_WAIT_TIME_MS           20000 /* 20 Seconds timeout */
  63
  64 /* Cmdq contains a fix number of a 16-Byte slots */
  65 struct bnxt_qplib_cmdqe {
  66         u8              data[16];
  67 };
  68
  69 /* CMDQ elements */
  70 #define BNXT_QPLIB_CMDQE_MAX_CNT_256    256
  71 #define BNXT_QPLIB_CMDQE_MAX_CNT_8192   8192
  72 #define BNXT_QPLIB_CMDQE_UNITS          sizeof(struct bnxt_qplib_cmdqe)
  73 #define BNXT_QPLIB_CMDQE_BYTES(depth)   ((depth) * BNXT_QPLIB_CMDQE_UNITS)
  74
  75 static inline u32 bnxt_qplib_cmdqe_npages(u32 depth)
  76 {
  77         u32 npages;
  78
  79         npages = BNXT_QPLIB_CMDQE_BYTES(depth) / PAGE_SIZE;
  80         if (BNXT_QPLIB_CMDQE_BYTES(depth) % PAGE_SIZE)
  81                 npages++;
  82         return npages;
  83 }
  84
  85 static inline u32 bnxt_qplib_cmdqe_page_size(u32 depth)
  86 {
  87         return (bnxt_qplib_cmdqe_npages(depth) * PAGE_SIZE);
  88 }
  89
  90 static inline u32 bnxt_qplib_cmdqe_cnt_per_pg(u32 depth)
  91 {
  92         return (bnxt_qplib_cmdqe_page_size(depth) /
  93                  BNXT_QPLIB_CMDQE_UNITS);
  94 }
  95
  96 /* Set the cmd_size to a factor of CMDQE unit */
  97 static inline void bnxt_qplib_set_cmd_slots(struct cmdq_base *req)
  98 {
  99         req->cmd_size = (req->cmd_size + BNXT_QPLIB_CMDQE_UNITS - 1) /
 100                          BNXT_QPLIB_CMDQE_UNITS;
 101 }
 102
 103 #define MAX_CMDQ_IDX(depth)             ((depth) - 1)
 104
 105 static inline u32 bnxt_qplib_max_cmdq_idx_per_pg(u32 depth)
 106 {
 107         return (bnxt_qplib_cmdqe_cnt_per_pg(depth) - 1);
 108 }
 109
 110 #define RCFW_MAX_COOKIE_VALUE           0x7FFF
 111 #define RCFW_CMD_IS_BLOCKING            0x8000
 112 #define RCFW_BLOCKED_CMD_WAIT_COUNT     0x4E20
 113
 114 #define HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK 0x1000900020011ULL
 115
 116 static inline u32 get_cmdq_pg(u32 val, u32 depth)
 117 {
 118         return (val & ~(bnxt_qplib_max_cmdq_idx_per_pg(depth))) /
 119                 (bnxt_qplib_cmdqe_cnt_per_pg(depth));
 120 }
 121
 122 static inline u32 get_cmdq_idx(u32 val, u32 depth)
 123 {
 124         return val & (bnxt_qplib_max_cmdq_idx_per_pg(depth));
 125 }
 126
 127 /* Crsq buf is 1024-Byte */
 128 struct bnxt_qplib_crsbe {
 129         u8                      data[1024];
 130 };
 131
 132 /* CREQ */
 133 /* Allocate 1 per QP for async error notification for now */
 134 #define BNXT_QPLIB_CREQE_MAX_CNT        (64 * 1024)
 135 #define BNXT_QPLIB_CREQE_UNITS          16      /* 16-Bytes per prod unit */
 136 #define BNXT_QPLIB_CREQE_CNT_PER_PG     (PAGE_SIZE / BNXT_QPLIB_CREQE_UNITS)
 137
 138 #define MAX_CREQ_IDX                    (BNXT_QPLIB_CREQE_MAX_CNT - 1)
 139 #define MAX_CREQ_IDX_PER_PG             (BNXT_QPLIB_CREQE_CNT_PER_PG - 1)
 140
 141 static inline u32 get_creq_pg(u32 val)
 142 {
 143         return (val & ~MAX_CREQ_IDX_PER_PG) / BNXT_QPLIB_CREQE_CNT_PER_PG;
 144 }
 145
 146 static inline u32 get_creq_idx(u32 val)
 147 {
 148         return val & MAX_CREQ_IDX_PER_PG;
 149 }
 150
 151 #define BNXT_QPLIB_CREQE_PER_PG (PAGE_SIZE / sizeof(struct creq_base))
 152
 153 #define CREQ_CMP_VALID(hdr, raw_cons, cp_bit)                   \
 154         (!!((hdr)->v & CREQ_BASE_V) ==                          \
 155            !((raw_cons) & (cp_bit)))
 156
 157 #define CREQ_DB_KEY_CP                  (0x2 << CMPL_DOORBELL_KEY_SFT)
 158 #define CREQ_DB_IDX_VALID               CMPL_DOORBELL_IDX_VALID
 159 #define CREQ_DB_IRQ_DIS                 CMPL_DOORBELL_MASK
 160 #define CREQ_DB_CP_FLAGS_REARM          (CREQ_DB_KEY_CP |       \
 161                                          CREQ_DB_IDX_VALID)
 162 #define CREQ_DB_CP_FLAGS                (CREQ_DB_KEY_CP |       \
 163                                          CREQ_DB_IDX_VALID |    \
 164                                          CREQ_DB_IRQ_DIS)
 165
 166 static inline void bnxt_qplib_ring_creq_db64(void __iomem *db, u32 index,
 167                                              u32 xid, bool arm)
 168 {
 169         u64 val = 0;
 170
 171         val = xid & DBC_DBC_XID_MASK;
 172         val |= DBC_DBC_PATH_ROCE;
 173         val |= arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;
 174         val <<= 32;
 175         val |= index & DBC_DBC_INDEX_MASK;
 176
 177         writeq(val, db);
 178 }
 179
 180 static inline void bnxt_qplib_ring_creq_db_rearm(void __iomem *db, u32 raw_cons,
 181                                                  u32 max_elements, u32 xid,
 182                                                  bool gen_p5)
 183 {
 184         u32 index = raw_cons & (max_elements - 1);
 185
 186         if (gen_p5)
 187                 bnxt_qplib_ring_creq_db64(db, index, xid, true);
 188         else
 189                 writel(CREQ_DB_CP_FLAGS_REARM | (index & DBC_DBC32_XID_MASK),
 190                        db);
 191 }
 192
 193 static inline void bnxt_qplib_ring_creq_db(void __iomem *db, u32 raw_cons,
 194                                            u32 max_elements, u32 xid,
 195                                            bool gen_p5)
 196 {
 197         u32 index = raw_cons & (max_elements - 1);
 198
 199         if (gen_p5)
 200                 bnxt_qplib_ring_creq_db64(db, index, xid, true);
 201         else
 202                 writel(CREQ_DB_CP_FLAGS | (index & DBC_DBC32_XID_MASK),
 203                        db);
 204 }
 205
 206 #define CREQ_ENTRY_POLL_BUDGET          0x100
 207
 208 /* HWQ */
 209 typedef int (*aeq_handler_t)(struct bnxt_qplib_rcfw *, void *, void *);
 210
 211 struct bnxt_qplib_crsqe {
 212         struct creq_qp_event    *resp;
 213         u32                     req_size;
 214 };
 215
 216 struct bnxt_qplib_rcfw_sbuf {
 217         void *sb;
 218         dma_addr_t dma_addr;
 219         u32 size;
 220 };
 221
 222 struct bnxt_qplib_qp_node {
 223         u32 qp_id;              /* QP id */
 224         void *qp_handle;        /* ptr to qplib_qp */
 225 };
 226
 227 #define BNXT_QPLIB_OOS_COUNT_MASK 0xFFFFFFFF
 228
 229 #define FIRMWARE_INITIALIZED_FLAG       (0)
 230 #define FIRMWARE_FIRST_FLAG             (31)
 231 #define FIRMWARE_TIMED_OUT              (3)
 232 struct bnxt_qplib_cmdq_mbox {
 233         struct bnxt_qplib_reg_desc      reg;
 234         void __iomem                    *prod;
 235         void __iomem                    *db;
 236 };
 237
 238 struct bnxt_qplib_cmdq_ctx {
 239         struct bnxt_qplib_hwq           hwq;
 240         struct bnxt_qplib_cmdq_mbox     cmdq_mbox;
 241         wait_queue_head_t               waitq;
 242         unsigned long                   flags;
 243         unsigned long                   *cmdq_bitmap;
 244         u32                             bmap_size;
 245         u32                             seq_num;
 246 };
 247
 248 struct bnxt_qplib_creq_db {
 249         struct bnxt_qplib_reg_desc      reg;
 250         struct bnxt_qplib_db_info       dbinfo;
 251 };
 252
 253 struct bnxt_qplib_creq_stat {
 254         u64     creq_qp_event_processed;
 255         u64     creq_func_event_processed;
 256 };
 257
 258 struct bnxt_qplib_creq_ctx {
 259         struct bnxt_qplib_hwq           hwq;
 260         struct bnxt_qplib_creq_db       creq_db;
 261         struct bnxt_qplib_creq_stat     stats;
 262         struct tasklet_struct           creq_tasklet;
 263         aeq_handler_t                   aeq_handler;
 264         u16                             ring_id;
 265         int                             msix_vec;
 266         bool                            requested; /*irq handler installed */
 267 };
 268
 269 /* RCFW Communication Channels */
 270 struct bnxt_qplib_rcfw {
 271         struct pci_dev          *pdev;
 272         struct bnxt_qplib_res   *res;
 273         struct bnxt_qplib_cmdq_ctx      cmdq;
 274         struct bnxt_qplib_creq_ctx      creq;
 275         struct bnxt_qplib_crsqe         *crsqe_tbl;
 276         int qp_tbl_size;
 277         struct bnxt_qplib_qp_node *qp_tbl;
 278         u64 oos_prev;
 279         u32 init_oos_stats;
 280         u32 cmdq_depth;
 281 };
 282
 283 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
 284 int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res,
 285                                   struct bnxt_qplib_rcfw *rcfw,
 286                                   struct bnxt_qplib_ctx *ctx,
 287                                   int qp_tbl_sz);
 288 void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill);
 289 void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
 290 int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector,
 291                               bool need_init);
 292 int bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw,
 293                                    int msix_vector,
 294                                    int cp_bar_reg_off, int virt_fn,
 295                                    aeq_handler_t aeq_handler);
 296
 297 struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf(
 298                                 struct bnxt_qplib_rcfw *rcfw,
 299                                 u32 size);
 300 void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw,
 301                                struct bnxt_qplib_rcfw_sbuf *sbuf);
 302 int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
 303                                  struct cmdq_base *req, struct creq_base *resp,
 304                                  void *sbuf, u8 is_block);
 305
 306 int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw);
 307 int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
 308                          struct bnxt_qplib_ctx *ctx, int is_virtfn);
 309 void bnxt_qplib_mark_qp_error(void *qp_handle);
 310 #endif /* __BNXT_QPLIB_RCFW_H__ */