drivers/infiniband/hw/bnxt_re/qplib_res.h

   1 /*
   2  * Broadcom NetXtreme-E RoCE driver.
   3  *
   4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
   5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * BSD license below:
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  *
  36  * Description: QPLib resource manager (header)
  37  */
  38
  39 #ifndef __BNXT_QPLIB_RES_H__
  40 #define __BNXT_QPLIB_RES_H__
  41
  42 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero;
  43
  44 #define PTR_CNT_PER_PG          (PAGE_SIZE / sizeof(void *))
  45 #define PTR_MAX_IDX_PER_PG      (PTR_CNT_PER_PG - 1)
  46 #define PTR_PG(x)               (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG)
  47 #define PTR_IDX(x)              ((x) & PTR_MAX_IDX_PER_PG)
  48
  49 #define HWQ_CMP(idx, hwq)       ((idx) & ((hwq)->max_elements - 1))
  50
  51 #define HWQ_FREE_SLOTS(hwq)     (hwq->max_elements - \
  52                                 ((HWQ_CMP(hwq->prod, hwq)\
  53                                 - HWQ_CMP(hwq->cons, hwq))\
  54                                 & (hwq->max_elements - 1)))
  55 enum bnxt_qplib_hwq_type {
  56         HWQ_TYPE_CTX,
  57         HWQ_TYPE_QUEUE,
  58         HWQ_TYPE_L2_CMPL,
  59         HWQ_TYPE_MR
  60 };
  61
  62 #define MAX_PBL_LVL_0_PGS               1
  63 #define MAX_PBL_LVL_1_PGS               512
  64 #define MAX_PBL_LVL_1_PGS_SHIFT         9
  65 #define MAX_PBL_LVL_1_PGS_FOR_LVL_2     256
  66 #define MAX_PBL_LVL_2_PGS               (256 * 512)
  67 #define MAX_PDL_LVL_SHIFT               9
  68
  69 enum bnxt_qplib_pbl_lvl {
  70         PBL_LVL_0,
  71         PBL_LVL_1,
  72         PBL_LVL_2,
  73         PBL_LVL_MAX
  74 };
  75
  76 #define ROCE_PG_SIZE_4K         (4 * 1024)
  77 #define ROCE_PG_SIZE_8K         (8 * 1024)
  78 #define ROCE_PG_SIZE_64K        (64 * 1024)
  79 #define ROCE_PG_SIZE_2M         (2 * 1024 * 1024)
  80 #define ROCE_PG_SIZE_8M         (8 * 1024 * 1024)
  81 #define ROCE_PG_SIZE_1G         (1024 * 1024 * 1024)
  82
  83 struct bnxt_qplib_reg_desc {
  84         u8              bar_id;
  85         resource_size_t bar_base;
  86         void __iomem    *bar_reg;
  87         size_t          len;
  88 };
  89
  90 struct bnxt_qplib_pbl {
  91         u32                             pg_count;
  92         u32                             pg_size;
  93         void                            **pg_arr;
  94         dma_addr_t                      *pg_map_arr;
  95 };
  96
  97 struct bnxt_qplib_sg_info {
  98         struct scatterlist              *sghead;
  99         u32                             nmap;
 100         u32                             npages;
 101         u32                             pgshft;
 102         u32                             pgsize;
 103         bool                            nopte;
 104 };
 105
 106 struct bnxt_qplib_hwq_attr {
 107         struct bnxt_qplib_res           *res;
 108         struct bnxt_qplib_sg_info       *sginfo;
 109         enum bnxt_qplib_hwq_type        type;
 110         u32                             depth;
 111         u32                             stride;
 112         u32                             aux_stride;
 113         u32                             aux_depth;
 114 };
 115
 116 struct bnxt_qplib_hwq {
 117         struct pci_dev                  *pdev;
 118         /* lock to protect qplib_hwq */
 119         spinlock_t                      lock;
 120         struct bnxt_qplib_pbl           pbl[PBL_LVL_MAX + 1];
 121         enum bnxt_qplib_pbl_lvl         level;          /* 0, 1, or 2 */
 122         /* ptr for easy access to the PBL entries */
 123         void                            **pbl_ptr;
 124         /* ptr for easy access to the dma_addr */
 125         dma_addr_t                      *pbl_dma_ptr;
 126         u32                             max_elements;
 127         u32                             depth;
 128         u16                             element_size;   /* Size of each entry */
 129
 130         u32                             prod;           /* raw */
 131         u32                             cons;           /* raw */
 132         u8                              cp_bit;
 133         u8                              is_user;
 134 };
 135
 136 struct bnxt_qplib_db_info {
 137         void __iomem            *db;
 138         void __iomem            *priv_db;
 139         struct bnxt_qplib_hwq   *hwq;
 140         u32                     xid;
 141 };
 142
 143 /* Tables */
 144 struct bnxt_qplib_pd_tbl {
 145         unsigned long                   *tbl;
 146         u32                             max;
 147 };
 148
 149 struct bnxt_qplib_sgid_tbl {
 150         struct bnxt_qplib_gid_info      *tbl;
 151         u16                             *hw_id;
 152         u16                             max;
 153         u16                             active;
 154         void                            *ctx;
 155         u8                              *vlan;
 156 };
 157
 158 struct bnxt_qplib_pkey_tbl {
 159         u16                             *tbl;
 160         u16                             max;
 161         u16                             active;
 162 };
 163
 164 struct bnxt_qplib_dpi {
 165         u32                             dpi;
 166         void __iomem                    *dbr;
 167         u64                             umdbr;
 168 };
 169
 170 struct bnxt_qplib_dpi_tbl {
 171         void                            **app_tbl;
 172         unsigned long                   *tbl;
 173         u16                             max;
 174         void __iomem                    *dbr_bar_reg_iomem;
 175         u64                             unmapped_dbr;
 176 };
 177
 178 struct bnxt_qplib_stats {
 179         dma_addr_t                      dma_map;
 180         void                            *dma;
 181         u32                             size;
 182         u32                             fw_id;
 183 };
 184
 185 struct bnxt_qplib_vf_res {
 186         u32 max_qp_per_vf;
 187         u32 max_mrw_per_vf;
 188         u32 max_srq_per_vf;
 189         u32 max_cq_per_vf;
 190         u32 max_gid_per_vf;
 191 };
 192
 193 #define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE        448
 194 #define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE       64
 195 #define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE        64
 196 #define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE       128
 197
 198 #define MAX_TQM_ALLOC_REQ               48
 199 #define MAX_TQM_ALLOC_BLK_SIZE          8
 200 struct bnxt_qplib_tqm_ctx {
 201         struct bnxt_qplib_hwq           pde;
 202         u8                              pde_level; /* Original level */
 203         struct bnxt_qplib_hwq           qtbl[MAX_TQM_ALLOC_REQ];
 204         u8                              qcount[MAX_TQM_ALLOC_REQ];
 205 };
 206
 207 struct bnxt_qplib_ctx {
 208         u32                             qpc_count;
 209         struct bnxt_qplib_hwq           qpc_tbl;
 210         u32                             mrw_count;
 211         struct bnxt_qplib_hwq           mrw_tbl;
 212         u32                             srqc_count;
 213         struct bnxt_qplib_hwq           srqc_tbl;
 214         u32                             cq_count;
 215         struct bnxt_qplib_hwq           cq_tbl;
 216         struct bnxt_qplib_hwq           tim_tbl;
 217         struct bnxt_qplib_tqm_ctx       tqm_ctx;
 218         struct bnxt_qplib_stats         stats;
 219         struct bnxt_qplib_vf_res        vf_res;
 220         u64                             hwrm_intf_ver;
 221 };
 222
 223 struct bnxt_qplib_chip_ctx {
 224         u16     chip_num;
 225         u8      chip_rev;
 226         u8      chip_metal;
 227 };
 228
 229 #define CHIP_NUM_57508          0x1750
 230 #define CHIP_NUM_57504          0x1751
 231 #define CHIP_NUM_57502          0x1752
 232
 233 struct bnxt_qplib_res {
 234         struct pci_dev                  *pdev;
 235         struct bnxt_qplib_chip_ctx      *cctx;
 236         struct net_device               *netdev;
 237
 238         struct bnxt_qplib_rcfw          *rcfw;
 239         struct bnxt_qplib_pd_tbl        pd_tbl;
 240         struct bnxt_qplib_sgid_tbl      sgid_tbl;
 241         struct bnxt_qplib_pkey_tbl      pkey_tbl;
 242         struct bnxt_qplib_dpi_tbl       dpi_tbl;
 243         bool                            prio;
 244 };
 245
 246 static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx)
 247 {
 248         return (cctx->chip_num == CHIP_NUM_57508 ||
 249                 cctx->chip_num == CHIP_NUM_57504 ||
 250                 cctx->chip_num == CHIP_NUM_57502);
 251 }
 252
 253 static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res)
 254 {
 255         return bnxt_qplib_is_chip_gen_p5(res->cctx) ?
 256                                         HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL;
 257 }
 258
 259 static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx)
 260 {
 261         return bnxt_qplib_is_chip_gen_p5(cctx) ?
 262                RING_ALLOC_REQ_RING_TYPE_NQ :
 263                RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL;
 264 }
 265
 266
 267 #define to_bnxt_qplib(ptr, type, member)        \
 268         container_of(ptr, type, member)
 269
 270 struct bnxt_qplib_pd;
 271 struct bnxt_qplib_dev_attr;
 272
 273 void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res,
 274                          struct bnxt_qplib_hwq *hwq);
 275 int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq,
 276                               struct bnxt_qplib_hwq_attr *hwq_attr);
 277 void bnxt_qplib_get_guid(u8 *dev_addr, u8 *guid);
 278 int bnxt_qplib_alloc_pd(struct bnxt_qplib_pd_tbl *pd_tbl,
 279                         struct bnxt_qplib_pd *pd);
 280 int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res,
 281                           struct bnxt_qplib_pd_tbl *pd_tbl,
 282                           struct bnxt_qplib_pd *pd);
 283 int bnxt_qplib_alloc_dpi(struct bnxt_qplib_dpi_tbl *dpit,
 284                          struct bnxt_qplib_dpi     *dpi,
 285                          void                      *app);
 286 int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res,
 287                            struct bnxt_qplib_dpi_tbl *dpi_tbl,
 288                            struct bnxt_qplib_dpi *dpi);
 289 void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res);
 290 int bnxt_qplib_init_res(struct bnxt_qplib_res *res);
 291 void bnxt_qplib_free_res(struct bnxt_qplib_res *res);
 292 int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev,
 293                          struct net_device *netdev,
 294                          struct bnxt_qplib_dev_attr *dev_attr);
 295 void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res,
 296                          struct bnxt_qplib_ctx *ctx);
 297 int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res,
 298                          struct bnxt_qplib_ctx *ctx,
 299                          bool virt_fn, bool is_p5);
 300
 301 static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info,
 302                                         bool arm)
 303 {
 304         u32 key;
 305
 306         key = info->hwq->cons & (info->hwq->max_elements - 1);
 307         key |= (CMPL_DOORBELL_IDX_VALID |
 308                 (CMPL_DOORBELL_KEY_CMPL & CMPL_DOORBELL_KEY_MASK));
 309         if (!arm)
 310                 key |= CMPL_DOORBELL_MASK;
 311         writel(key, info->db);
 312 }
 313
 314 static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info,
 315                                       u32 type)
 316 {
 317         u64 key = 0;
 318
 319         key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
 320         key <<= 32;
 321         key |= (info->hwq->cons & (info->hwq->max_elements - 1)) &
 322                 DBC_DBC_INDEX_MASK;
 323         writeq(key, info->db);
 324 }
 325
 326 static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info,
 327                                            u32 type)
 328 {
 329         u64 key = 0;
 330
 331         key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
 332         key <<= 32;
 333         key |= (info->hwq->prod & (info->hwq->max_elements - 1)) &
 334                 DBC_DBC_INDEX_MASK;
 335         writeq(key, info->db);
 336 }
 337
 338 static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info,
 339                                        u32 type)
 340 {
 341         u64 key = 0;
 342
 343         key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
 344         key <<= 32;
 345         writeq(key, info->priv_db);
 346 }
 347
 348 static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info,
 349                                          u32 th)
 350 {
 351         u64 key = 0;
 352
 353         key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | th;
 354         key <<= 32;
 355         key |=  th & DBC_DBC_INDEX_MASK;
 356         writeq(key, info->priv_db);
 357 }
 358
 359 static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info,
 360                                          struct bnxt_qplib_chip_ctx *cctx,
 361                                          bool arm)
 362 {
 363         u32 type;
 364
 365         type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;
 366         if (bnxt_qplib_is_chip_gen_p5(cctx))
 367                 bnxt_qplib_ring_db(info, type);
 368         else
 369                 bnxt_qplib_ring_db32(info, arm);
 370 }
 371 #endif /* __BNXT_QPLIB_RES_H__ */