drivers/media/i2c/ov2659.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Omnivision OV2659 CMOS Image Sensor driver
   4  *
   5  * Copyright (C) 2015 Texas Instruments, Inc.
   6  *
   7  * Benoit Parrot <bparrot@ti.com>
   8  * Lad, Prabhakar <prabhakar.csengg@gmail.com>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/delay.h>
  13 #include <linux/gpio/consumer.h>
  14 #include <linux/i2c.h>
  15 #include <linux/module.h>
  16 #include <linux/of_graph.h>
  17 #include <linux/pm_runtime.h>
  18
  19 #include <media/i2c/ov2659.h>
  20 #include <media/v4l2-ctrls.h>
  21 #include <media/v4l2-event.h>
  22 #include <media/v4l2-fwnode.h>
  23 #include <media/v4l2-image-sizes.h>
  24 #include <media/v4l2-subdev.h>
  25
  26 #define DRIVER_NAME "ov2659"
  27
  28 /*
  29  * OV2659 register definitions
  30  */
  31 #define REG_SOFTWARE_STANDBY            0x0100
  32 #define REG_SOFTWARE_RESET              0x0103
  33 #define REG_IO_CTRL00                   0x3000
  34 #define REG_IO_CTRL01                   0x3001
  35 #define REG_IO_CTRL02                   0x3002
  36 #define REG_OUTPUT_VALUE00              0x3008
  37 #define REG_OUTPUT_VALUE01              0x3009
  38 #define REG_OUTPUT_VALUE02              0x300d
  39 #define REG_OUTPUT_SELECT00             0x300e
  40 #define REG_OUTPUT_SELECT01             0x300f
  41 #define REG_OUTPUT_SELECT02             0x3010
  42 #define REG_OUTPUT_DRIVE                0x3011
  43 #define REG_INPUT_READOUT00             0x302d
  44 #define REG_INPUT_READOUT01             0x302e
  45 #define REG_INPUT_READOUT02             0x302f
  46
  47 #define REG_SC_PLL_CTRL0                0x3003
  48 #define REG_SC_PLL_CTRL1                0x3004
  49 #define REG_SC_PLL_CTRL2                0x3005
  50 #define REG_SC_PLL_CTRL3                0x3006
  51 #define REG_SC_CHIP_ID_H                0x300a
  52 #define REG_SC_CHIP_ID_L                0x300b
  53 #define REG_SC_PWC                      0x3014
  54 #define REG_SC_CLKRST0                  0x301a
  55 #define REG_SC_CLKRST1                  0x301b
  56 #define REG_SC_CLKRST2                  0x301c
  57 #define REG_SC_CLKRST3                  0x301d
  58 #define REG_SC_SUB_ID                   0x302a
  59 #define REG_SC_SCCB_ID                  0x302b
  60
  61 #define REG_GROUP_ADDRESS_00            0x3200
  62 #define REG_GROUP_ADDRESS_01            0x3201
  63 #define REG_GROUP_ADDRESS_02            0x3202
  64 #define REG_GROUP_ADDRESS_03            0x3203
  65 #define REG_GROUP_ACCESS                0x3208
  66
  67 #define REG_AWB_R_GAIN_H                0x3400
  68 #define REG_AWB_R_GAIN_L                0x3401
  69 #define REG_AWB_G_GAIN_H                0x3402
  70 #define REG_AWB_G_GAIN_L                0x3403
  71 #define REG_AWB_B_GAIN_H                0x3404
  72 #define REG_AWB_B_GAIN_L                0x3405
  73 #define REG_AWB_MANUAL_CONTROL          0x3406
  74
  75 #define REG_TIMING_HS_H                 0x3800
  76 #define REG_TIMING_HS_L                 0x3801
  77 #define REG_TIMING_VS_H                 0x3802
  78 #define REG_TIMING_VS_L                 0x3803
  79 #define REG_TIMING_HW_H                 0x3804
  80 #define REG_TIMING_HW_L                 0x3805
  81 #define REG_TIMING_VH_H                 0x3806
  82 #define REG_TIMING_VH_L                 0x3807
  83 #define REG_TIMING_DVPHO_H              0x3808
  84 #define REG_TIMING_DVPHO_L              0x3809
  85 #define REG_TIMING_DVPVO_H              0x380a
  86 #define REG_TIMING_DVPVO_L              0x380b
  87 #define REG_TIMING_HTS_H                0x380c
  88 #define REG_TIMING_HTS_L                0x380d
  89 #define REG_TIMING_VTS_H                0x380e
  90 #define REG_TIMING_VTS_L                0x380f
  91 #define REG_TIMING_HOFFS_H              0x3810
  92 #define REG_TIMING_HOFFS_L              0x3811
  93 #define REG_TIMING_VOFFS_H              0x3812
  94 #define REG_TIMING_VOFFS_L              0x3813
  95 #define REG_TIMING_XINC                 0x3814
  96 #define REG_TIMING_YINC                 0x3815
  97 #define REG_TIMING_VERT_FORMAT          0x3820
  98 #define REG_TIMING_HORIZ_FORMAT         0x3821
  99
 100 #define REG_FORMAT_CTRL00               0x4300
 101
 102 #define REG_VFIFO_READ_START_H          0x4608
 103 #define REG_VFIFO_READ_START_L          0x4609
 104
 105 #define REG_DVP_CTRL02                  0x4708
 106
 107 #define REG_ISP_CTRL00                  0x5000
 108 #define REG_ISP_CTRL01                  0x5001
 109 #define REG_ISP_CTRL02                  0x5002
 110
 111 #define REG_LENC_RED_X0_H               0x500c
 112 #define REG_LENC_RED_X0_L               0x500d
 113 #define REG_LENC_RED_Y0_H               0x500e
 114 #define REG_LENC_RED_Y0_L               0x500f
 115 #define REG_LENC_RED_A1                 0x5010
 116 #define REG_LENC_RED_B1                 0x5011
 117 #define REG_LENC_RED_A2_B2              0x5012
 118 #define REG_LENC_GREEN_X0_H             0x5013
 119 #define REG_LENC_GREEN_X0_L             0x5014
 120 #define REG_LENC_GREEN_Y0_H             0x5015
 121 #define REG_LENC_GREEN_Y0_L             0x5016
 122 #define REG_LENC_GREEN_A1               0x5017
 123 #define REG_LENC_GREEN_B1               0x5018
 124 #define REG_LENC_GREEN_A2_B2            0x5019
 125 #define REG_LENC_BLUE_X0_H              0x501a
 126 #define REG_LENC_BLUE_X0_L              0x501b
 127 #define REG_LENC_BLUE_Y0_H              0x501c
 128 #define REG_LENC_BLUE_Y0_L              0x501d
 129 #define REG_LENC_BLUE_A1                0x501e
 130 #define REG_LENC_BLUE_B1                0x501f
 131 #define REG_LENC_BLUE_A2_B2             0x5020
 132
 133 #define REG_AWB_CTRL00                  0x5035
 134 #define REG_AWB_CTRL01                  0x5036
 135 #define REG_AWB_CTRL02                  0x5037
 136 #define REG_AWB_CTRL03                  0x5038
 137 #define REG_AWB_CTRL04                  0x5039
 138 #define REG_AWB_LOCAL_LIMIT             0x503a
 139 #define REG_AWB_CTRL12                  0x5049
 140 #define REG_AWB_CTRL13                  0x504a
 141 #define REG_AWB_CTRL14                  0x504b
 142
 143 #define REG_SHARPENMT_THRESH1           0x5064
 144 #define REG_SHARPENMT_THRESH2           0x5065
 145 #define REG_SHARPENMT_OFFSET1           0x5066
 146 #define REG_SHARPENMT_OFFSET2           0x5067
 147 #define REG_DENOISE_THRESH1             0x5068
 148 #define REG_DENOISE_THRESH2             0x5069
 149 #define REG_DENOISE_OFFSET1             0x506a
 150 #define REG_DENOISE_OFFSET2             0x506b
 151 #define REG_SHARPEN_THRESH1             0x506c
 152 #define REG_SHARPEN_THRESH2             0x506d
 153 #define REG_CIP_CTRL00                  0x506e
 154 #define REG_CIP_CTRL01                  0x506f
 155
 156 #define REG_CMX_SIGN                    0x5079
 157 #define REG_CMX_MISC_CTRL               0x507a
 158
 159 #define REG_PRE_ISP_CTRL00              0x50a0
 160 #define TEST_PATTERN_ENABLE             BIT(7)
 161 #define VERTICAL_COLOR_BAR_MASK         0x53
 162
 163 #define REG_NULL                        0x0000  /* Array end token */
 164
 165 #define OV265X_ID(_msb, _lsb)           ((_msb) << 8 | (_lsb))
 166 #define OV2659_ID                       0x2656
 167
 168 struct sensor_register {
 169         u16 addr;
 170         u8 value;
 171 };
 172
 173 struct ov2659_framesize {
 174         u16 width;
 175         u16 height;
 176         u16 max_exp_lines;
 177         const struct sensor_register *regs;
 178 };
 179
 180 struct ov2659_pll_ctrl {
 181         u8 ctrl1;
 182         u8 ctrl2;
 183         u8 ctrl3;
 184 };
 185
 186 struct ov2659_pixfmt {
 187         u32 code;
 188         /* Output format Register Value (REG_FORMAT_CTRL00) */
 189         struct sensor_register *format_ctrl_regs;
 190 };
 191
 192 struct pll_ctrl_reg {
 193         unsigned int div;
 194         unsigned char reg;
 195 };
 196
 197 struct ov2659 {
 198         struct v4l2_subdev sd;
 199         struct media_pad pad;
 200         struct v4l2_mbus_framefmt format;
 201         unsigned int xvclk_frequency;
 202         const struct ov2659_platform_data *pdata;
 203         struct mutex lock;
 204         struct i2c_client *client;
 205         struct v4l2_ctrl_handler ctrls;
 206         struct v4l2_ctrl *link_frequency;
 207         const struct ov2659_framesize *frame_size;
 208         struct sensor_register *format_ctrl_regs;
 209         struct ov2659_pll_ctrl pll;
 210         int streaming;
 211         /* used to control the sensor PWDN pin */
 212         struct gpio_desc *pwdn_gpio;
 213         /* used to control the sensor RESETB pin */
 214         struct gpio_desc *resetb_gpio;
 215 };
 216
 217 static const struct sensor_register ov2659_init_regs[] = {
 218         { REG_IO_CTRL00, 0x03 },
 219         { REG_IO_CTRL01, 0xff },
 220         { REG_IO_CTRL02, 0xe0 },
 221         { 0x3633, 0x3d },
 222         { 0x3620, 0x02 },
 223         { 0x3631, 0x11 },
 224         { 0x3612, 0x04 },
 225         { 0x3630, 0x20 },
 226         { 0x4702, 0x02 },
 227         { 0x370c, 0x34 },
 228         { REG_TIMING_HS_H, 0x00 },
 229         { REG_TIMING_HS_L, 0x00 },
 230         { REG_TIMING_VS_H, 0x00 },
 231         { REG_TIMING_VS_L, 0x00 },
 232         { REG_TIMING_HW_H, 0x06 },
 233         { REG_TIMING_HW_L, 0x5f },
 234         { REG_TIMING_VH_H, 0x04 },
 235         { REG_TIMING_VH_L, 0xb7 },
 236         { REG_TIMING_DVPHO_H, 0x03 },
 237         { REG_TIMING_DVPHO_L, 0x20 },
 238         { REG_TIMING_DVPVO_H, 0x02 },
 239         { REG_TIMING_DVPVO_L, 0x58 },
 240         { REG_TIMING_HTS_H, 0x05 },
 241         { REG_TIMING_HTS_L, 0x14 },
 242         { REG_TIMING_VTS_H, 0x02 },
 243         { REG_TIMING_VTS_L, 0x68 },
 244         { REG_TIMING_HOFFS_L, 0x08 },
 245         { REG_TIMING_VOFFS_L, 0x02 },
 246         { REG_TIMING_XINC, 0x31 },
 247         { REG_TIMING_YINC, 0x31 },
 248         { 0x3a02, 0x02 },
 249         { 0x3a03, 0x68 },
 250         { 0x3a08, 0x00 },
 251         { 0x3a09, 0x5c },
 252         { 0x3a0a, 0x00 },
 253         { 0x3a0b, 0x4d },
 254         { 0x3a0d, 0x08 },
 255         { 0x3a0e, 0x06 },
 256         { 0x3a14, 0x02 },
 257         { 0x3a15, 0x28 },
 258         { REG_DVP_CTRL02, 0x01 },
 259         { 0x3623, 0x00 },
 260         { 0x3634, 0x76 },
 261         { 0x3701, 0x44 },
 262         { 0x3702, 0x18 },
 263         { 0x3703, 0x24 },
 264         { 0x3704, 0x24 },
 265         { 0x3705, 0x0c },
 266         { REG_TIMING_VERT_FORMAT, 0x81 },
 267         { REG_TIMING_HORIZ_FORMAT, 0x01 },
 268         { 0x370a, 0x52 },
 269         { REG_VFIFO_READ_START_H, 0x00 },
 270         { REG_VFIFO_READ_START_L, 0x80 },
 271         { REG_FORMAT_CTRL00, 0x30 },
 272         { 0x5086, 0x02 },
 273         { REG_ISP_CTRL00, 0xfb },
 274         { REG_ISP_CTRL01, 0x1f },
 275         { REG_ISP_CTRL02, 0x00 },
 276         { 0x5025, 0x0e },
 277         { 0x5026, 0x18 },
 278         { 0x5027, 0x34 },
 279         { 0x5028, 0x4c },
 280         { 0x5029, 0x62 },
 281         { 0x502a, 0x74 },
 282         { 0x502b, 0x85 },
 283         { 0x502c, 0x92 },
 284         { 0x502d, 0x9e },
 285         { 0x502e, 0xb2 },
 286         { 0x502f, 0xc0 },
 287         { 0x5030, 0xcc },
 288         { 0x5031, 0xe0 },
 289         { 0x5032, 0xee },
 290         { 0x5033, 0xf6 },
 291         { 0x5034, 0x11 },
 292         { 0x5070, 0x1c },
 293         { 0x5071, 0x5b },
 294         { 0x5072, 0x05 },
 295         { 0x5073, 0x20 },
 296         { 0x5074, 0x94 },
 297         { 0x5075, 0xb4 },
 298         { 0x5076, 0xb4 },
 299         { 0x5077, 0xaf },
 300         { 0x5078, 0x05 },
 301         { REG_CMX_SIGN, 0x98 },
 302         { REG_CMX_MISC_CTRL, 0x21 },
 303         { REG_AWB_CTRL00, 0x6a },
 304         { REG_AWB_CTRL01, 0x11 },
 305         { REG_AWB_CTRL02, 0x92 },
 306         { REG_AWB_CTRL03, 0x21 },
 307         { REG_AWB_CTRL04, 0xe1 },
 308         { REG_AWB_LOCAL_LIMIT, 0x01 },
 309         { 0x503c, 0x05 },
 310         { 0x503d, 0x08 },
 311         { 0x503e, 0x08 },
 312         { 0x503f, 0x64 },
 313         { 0x5040, 0x58 },
 314         { 0x5041, 0x2a },
 315         { 0x5042, 0xc5 },
 316         { 0x5043, 0x2e },
 317         { 0x5044, 0x3a },
 318         { 0x5045, 0x3c },
 319         { 0x5046, 0x44 },
 320         { 0x5047, 0xf8 },
 321         { 0x5048, 0x08 },
 322         { REG_AWB_CTRL12, 0x70 },
 323         { REG_AWB_CTRL13, 0xf0 },
 324         { REG_AWB_CTRL14, 0xf0 },
 325         { REG_LENC_RED_X0_H, 0x03 },
 326         { REG_LENC_RED_X0_L, 0x20 },
 327         { REG_LENC_RED_Y0_H, 0x02 },
 328         { REG_LENC_RED_Y0_L, 0x5c },
 329         { REG_LENC_RED_A1, 0x48 },
 330         { REG_LENC_RED_B1, 0x00 },
 331         { REG_LENC_RED_A2_B2, 0x66 },
 332         { REG_LENC_GREEN_X0_H, 0x03 },
 333         { REG_LENC_GREEN_X0_L, 0x30 },
 334         { REG_LENC_GREEN_Y0_H, 0x02 },
 335         { REG_LENC_GREEN_Y0_L, 0x7c },
 336         { REG_LENC_GREEN_A1, 0x40 },
 337         { REG_LENC_GREEN_B1, 0x00 },
 338         { REG_LENC_GREEN_A2_B2, 0x66 },
 339         { REG_LENC_BLUE_X0_H, 0x03 },
 340         { REG_LENC_BLUE_X0_L, 0x10 },
 341         { REG_LENC_BLUE_Y0_H, 0x02 },
 342         { REG_LENC_BLUE_Y0_L, 0x7c },
 343         { REG_LENC_BLUE_A1, 0x3a },
 344         { REG_LENC_BLUE_B1, 0x00 },
 345         { REG_LENC_BLUE_A2_B2, 0x66 },
 346         { REG_CIP_CTRL00, 0x44 },
 347         { REG_SHARPENMT_THRESH1, 0x08 },
 348         { REG_SHARPENMT_THRESH2, 0x10 },
 349         { REG_SHARPENMT_OFFSET1, 0x12 },
 350         { REG_SHARPENMT_OFFSET2, 0x02 },
 351         { REG_SHARPEN_THRESH1, 0x08 },
 352         { REG_SHARPEN_THRESH2, 0x10 },
 353         { REG_CIP_CTRL01, 0xa6 },
 354         { REG_DENOISE_THRESH1, 0x08 },
 355         { REG_DENOISE_THRESH2, 0x10 },
 356         { REG_DENOISE_OFFSET1, 0x04 },
 357         { REG_DENOISE_OFFSET2, 0x12 },
 358         { 0x507e, 0x40 },
 359         { 0x507f, 0x20 },
 360         { 0x507b, 0x02 },
 361         { REG_CMX_MISC_CTRL, 0x01 },
 362         { 0x5084, 0x0c },
 363         { 0x5085, 0x3e },
 364         { 0x5005, 0x80 },
 365         { 0x3a0f, 0x30 },
 366         { 0x3a10, 0x28 },
 367         { 0x3a1b, 0x32 },
 368         { 0x3a1e, 0x26 },
 369         { 0x3a11, 0x60 },
 370         { 0x3a1f, 0x14 },
 371         { 0x5060, 0x69 },
 372         { 0x5061, 0x7d },
 373         { 0x5062, 0x7d },
 374         { 0x5063, 0x69 },
 375         { REG_NULL, 0x00 },
 376 };
 377
 378 /* 1280X720 720p */
 379 static struct sensor_register ov2659_720p[] = {
 380         { REG_TIMING_HS_H, 0x00 },
 381         { REG_TIMING_HS_L, 0xa0 },
 382         { REG_TIMING_VS_H, 0x00 },
 383         { REG_TIMING_VS_L, 0xf0 },
 384         { REG_TIMING_HW_H, 0x05 },
 385         { REG_TIMING_HW_L, 0xbf },
 386         { REG_TIMING_VH_H, 0x03 },
 387         { REG_TIMING_VH_L, 0xcb },
 388         { REG_TIMING_DVPHO_H, 0x05 },
 389         { REG_TIMING_DVPHO_L, 0x00 },
 390         { REG_TIMING_DVPVO_H, 0x02 },
 391         { REG_TIMING_DVPVO_L, 0xd0 },
 392         { REG_TIMING_HTS_H, 0x06 },
 393         { REG_TIMING_HTS_L, 0x4c },
 394         { REG_TIMING_VTS_H, 0x02 },
 395         { REG_TIMING_VTS_L, 0xe8 },
 396         { REG_TIMING_HOFFS_L, 0x10 },
 397         { REG_TIMING_VOFFS_L, 0x06 },
 398         { REG_TIMING_XINC, 0x11 },
 399         { REG_TIMING_YINC, 0x11 },
 400         { REG_TIMING_VERT_FORMAT, 0x80 },
 401         { REG_TIMING_HORIZ_FORMAT, 0x00 },
 402         { 0x370a, 0x12 },
 403         { 0x3a03, 0xe8 },
 404         { 0x3a09, 0x6f },
 405         { 0x3a0b, 0x5d },
 406         { 0x3a15, 0x9a },
 407         { REG_VFIFO_READ_START_H, 0x00 },
 408         { REG_VFIFO_READ_START_L, 0x80 },
 409         { REG_ISP_CTRL02, 0x00 },
 410         { REG_NULL, 0x00 },
 411 };
 412
 413 /* 1600X1200 UXGA */
 414 static struct sensor_register ov2659_uxga[] = {
 415         { REG_TIMING_HS_H, 0x00 },
 416         { REG_TIMING_HS_L, 0x00 },
 417         { REG_TIMING_VS_H, 0x00 },
 418         { REG_TIMING_VS_L, 0x00 },
 419         { REG_TIMING_HW_H, 0x06 },
 420         { REG_TIMING_HW_L, 0x5f },
 421         { REG_TIMING_VH_H, 0x04 },
 422         { REG_TIMING_VH_L, 0xbb },
 423         { REG_TIMING_DVPHO_H, 0x06 },
 424         { REG_TIMING_DVPHO_L, 0x40 },
 425         { REG_TIMING_DVPVO_H, 0x04 },
 426         { REG_TIMING_DVPVO_L, 0xb0 },
 427         { REG_TIMING_HTS_H, 0x07 },
 428         { REG_TIMING_HTS_L, 0x9f },
 429         { REG_TIMING_VTS_H, 0x04 },
 430         { REG_TIMING_VTS_L, 0xd0 },
 431         { REG_TIMING_HOFFS_L, 0x10 },
 432         { REG_TIMING_VOFFS_L, 0x06 },
 433         { REG_TIMING_XINC, 0x11 },
 434         { REG_TIMING_YINC, 0x11 },
 435         { 0x3a02, 0x04 },
 436         { 0x3a03, 0xd0 },
 437         { 0x3a08, 0x00 },
 438         { 0x3a09, 0xb8 },
 439         { 0x3a0a, 0x00 },
 440         { 0x3a0b, 0x9a },
 441         { 0x3a0d, 0x08 },
 442         { 0x3a0e, 0x06 },
 443         { 0x3a14, 0x04 },
 444         { 0x3a15, 0x50 },
 445         { 0x3623, 0x00 },
 446         { 0x3634, 0x44 },
 447         { 0x3701, 0x44 },
 448         { 0x3702, 0x30 },
 449         { 0x3703, 0x48 },
 450         { 0x3704, 0x48 },
 451         { 0x3705, 0x18 },
 452         { REG_TIMING_VERT_FORMAT, 0x80 },
 453         { REG_TIMING_HORIZ_FORMAT, 0x00 },
 454         { 0x370a, 0x12 },
 455         { REG_VFIFO_READ_START_H, 0x00 },
 456         { REG_VFIFO_READ_START_L, 0x80 },
 457         { REG_ISP_CTRL02, 0x00 },
 458         { REG_NULL, 0x00 },
 459 };
 460
 461 /* 1280X1024 SXGA */
 462 static struct sensor_register ov2659_sxga[] = {
 463         { REG_TIMING_HS_H, 0x00 },
 464         { REG_TIMING_HS_L, 0x00 },
 465         { REG_TIMING_VS_H, 0x00 },
 466         { REG_TIMING_VS_L, 0x00 },
 467         { REG_TIMING_HW_H, 0x06 },
 468         { REG_TIMING_HW_L, 0x5f },
 469         { REG_TIMING_VH_H, 0x04 },
 470         { REG_TIMING_VH_L, 0xb7 },
 471         { REG_TIMING_DVPHO_H, 0x05 },
 472         { REG_TIMING_DVPHO_L, 0x00 },
 473         { REG_TIMING_DVPVO_H, 0x04 },
 474         { REG_TIMING_DVPVO_L, 0x00 },
 475         { REG_TIMING_HTS_H, 0x07 },
 476         { REG_TIMING_HTS_L, 0x9c },
 477         { REG_TIMING_VTS_H, 0x04 },
 478         { REG_TIMING_VTS_L, 0xd0 },
 479         { REG_TIMING_HOFFS_L, 0x10 },
 480         { REG_TIMING_VOFFS_L, 0x06 },
 481         { REG_TIMING_XINC, 0x11 },
 482         { REG_TIMING_YINC, 0x11 },
 483         { 0x3a02, 0x02 },
 484         { 0x3a03, 0x68 },
 485         { 0x3a08, 0x00 },
 486         { 0x3a09, 0x5c },
 487         { 0x3a0a, 0x00 },
 488         { 0x3a0b, 0x4d },
 489         { 0x3a0d, 0x08 },
 490         { 0x3a0e, 0x06 },
 491         { 0x3a14, 0x02 },
 492         { 0x3a15, 0x28 },
 493         { 0x3623, 0x00 },
 494         { 0x3634, 0x76 },
 495         { 0x3701, 0x44 },
 496         { 0x3702, 0x18 },
 497         { 0x3703, 0x24 },
 498         { 0x3704, 0x24 },
 499         { 0x3705, 0x0c },
 500         { REG_TIMING_VERT_FORMAT, 0x80 },
 501         { REG_TIMING_HORIZ_FORMAT, 0x00 },
 502         { 0x370a, 0x52 },
 503         { REG_VFIFO_READ_START_H, 0x00 },
 504         { REG_VFIFO_READ_START_L, 0x80 },
 505         { REG_ISP_CTRL02, 0x00 },
 506         { REG_NULL, 0x00 },
 507 };
 508
 509 /* 1024X768 SXGA */
 510 static struct sensor_register ov2659_xga[] = {
 511         { REG_TIMING_HS_H, 0x00 },
 512         { REG_TIMING_HS_L, 0x00 },
 513         { REG_TIMING_VS_H, 0x00 },
 514         { REG_TIMING_VS_L, 0x00 },
 515         { REG_TIMING_HW_H, 0x06 },
 516         { REG_TIMING_HW_L, 0x5f },
 517         { REG_TIMING_VH_H, 0x04 },
 518         { REG_TIMING_VH_L, 0xb7 },
 519         { REG_TIMING_DVPHO_H, 0x04 },
 520         { REG_TIMING_DVPHO_L, 0x00 },
 521         { REG_TIMING_DVPVO_H, 0x03 },
 522         { REG_TIMING_DVPVO_L, 0x00 },
 523         { REG_TIMING_HTS_H, 0x07 },
 524         { REG_TIMING_HTS_L, 0x9c },
 525         { REG_TIMING_VTS_H, 0x04 },
 526         { REG_TIMING_VTS_L, 0xd0 },
 527         { REG_TIMING_HOFFS_L, 0x10 },
 528         { REG_TIMING_VOFFS_L, 0x06 },
 529         { REG_TIMING_XINC, 0x11 },
 530         { REG_TIMING_YINC, 0x11 },
 531         { 0x3a02, 0x02 },
 532         { 0x3a03, 0x68 },
 533         { 0x3a08, 0x00 },
 534         { 0x3a09, 0x5c },
 535         { 0x3a0a, 0x00 },
 536         { 0x3a0b, 0x4d },
 537         { 0x3a0d, 0x08 },
 538         { 0x3a0e, 0x06 },
 539         { 0x3a14, 0x02 },
 540         { 0x3a15, 0x28 },
 541         { 0x3623, 0x00 },
 542         { 0x3634, 0x76 },
 543         { 0x3701, 0x44 },
 544         { 0x3702, 0x18 },
 545         { 0x3703, 0x24 },
 546         { 0x3704, 0x24 },
 547         { 0x3705, 0x0c },
 548         { REG_TIMING_VERT_FORMAT, 0x80 },
 549         { REG_TIMING_HORIZ_FORMAT, 0x00 },
 550         { 0x370a, 0x52 },
 551         { REG_VFIFO_READ_START_H, 0x00 },
 552         { REG_VFIFO_READ_START_L, 0x80 },
 553         { REG_ISP_CTRL02, 0x00 },
 554         { REG_NULL, 0x00 },
 555 };
 556
 557 /* 800X600 SVGA */
 558 static struct sensor_register ov2659_svga[] = {
 559         { REG_TIMING_HS_H, 0x00 },
 560         { REG_TIMING_HS_L, 0x00 },
 561         { REG_TIMING_VS_H, 0x00 },
 562         { REG_TIMING_VS_L, 0x00 },
 563         { REG_TIMING_HW_H, 0x06 },
 564         { REG_TIMING_HW_L, 0x5f },
 565         { REG_TIMING_VH_H, 0x04 },
 566         { REG_TIMING_VH_L, 0xb7 },
 567         { REG_TIMING_DVPHO_H, 0x03 },
 568         { REG_TIMING_DVPHO_L, 0x20 },
 569         { REG_TIMING_DVPVO_H, 0x02 },
 570         { REG_TIMING_DVPVO_L, 0x58 },
 571         { REG_TIMING_HTS_H, 0x05 },
 572         { REG_TIMING_HTS_L, 0x14 },
 573         { REG_TIMING_VTS_H, 0x02 },
 574         { REG_TIMING_VTS_L, 0x68 },
 575         { REG_TIMING_HOFFS_L, 0x08 },
 576         { REG_TIMING_VOFFS_L, 0x02 },
 577         { REG_TIMING_XINC, 0x31 },
 578         { REG_TIMING_YINC, 0x31 },
 579         { 0x3a02, 0x02 },
 580         { 0x3a03, 0x68 },
 581         { 0x3a08, 0x00 },
 582         { 0x3a09, 0x5c },
 583         { 0x3a0a, 0x00 },
 584         { 0x3a0b, 0x4d },
 585         { 0x3a0d, 0x08 },
 586         { 0x3a0e, 0x06 },
 587         { 0x3a14, 0x02 },
 588         { 0x3a15, 0x28 },
 589         { 0x3623, 0x00 },
 590         { 0x3634, 0x76 },
 591         { 0x3701, 0x44 },
 592         { 0x3702, 0x18 },
 593         { 0x3703, 0x24 },
 594         { 0x3704, 0x24 },
 595         { 0x3705, 0x0c },
 596         { REG_TIMING_VERT_FORMAT, 0x81 },
 597         { REG_TIMING_HORIZ_FORMAT, 0x01 },
 598         { 0x370a, 0x52 },
 599         { REG_VFIFO_READ_START_H, 0x00 },
 600         { REG_VFIFO_READ_START_L, 0x80 },
 601         { REG_ISP_CTRL02, 0x00 },
 602         { REG_NULL, 0x00 },
 603 };
 604
 605 /* 640X480 VGA */
 606 static struct sensor_register ov2659_vga[] = {
 607         { REG_TIMING_HS_H, 0x00 },
 608         { REG_TIMING_HS_L, 0x00 },
 609         { REG_TIMING_VS_H, 0x00 },
 610         { REG_TIMING_VS_L, 0x00 },
 611         { REG_TIMING_HW_H, 0x06 },
 612         { REG_TIMING_HW_L, 0x5f },
 613         { REG_TIMING_VH_H, 0x04 },
 614         { REG_TIMING_VH_L, 0xb7 },
 615         { REG_TIMING_DVPHO_H, 0x02 },
 616         { REG_TIMING_DVPHO_L, 0x80 },
 617         { REG_TIMING_DVPVO_H, 0x01 },
 618         { REG_TIMING_DVPVO_L, 0xe0 },
 619         { REG_TIMING_HTS_H, 0x05 },
 620         { REG_TIMING_HTS_L, 0x14 },
 621         { REG_TIMING_VTS_H, 0x02 },
 622         { REG_TIMING_VTS_L, 0x68 },
 623         { REG_TIMING_HOFFS_L, 0x08 },
 624         { REG_TIMING_VOFFS_L, 0x02 },
 625         { REG_TIMING_XINC, 0x31 },
 626         { REG_TIMING_YINC, 0x31 },
 627         { 0x3a02, 0x02 },
 628         { 0x3a03, 0x68 },
 629         { 0x3a08, 0x00 },
 630         { 0x3a09, 0x5c },
 631         { 0x3a0a, 0x00 },
 632         { 0x3a0b, 0x4d },
 633         { 0x3a0d, 0x08 },
 634         { 0x3a0e, 0x06 },
 635         { 0x3a14, 0x02 },
 636         { 0x3a15, 0x28 },
 637         { 0x3623, 0x00 },
 638         { 0x3634, 0x76 },
 639         { 0x3701, 0x44 },
 640         { 0x3702, 0x18 },
 641         { 0x3703, 0x24 },
 642         { 0x3704, 0x24 },
 643         { 0x3705, 0x0c },
 644         { REG_TIMING_VERT_FORMAT, 0x81 },
 645         { REG_TIMING_HORIZ_FORMAT, 0x01 },
 646         { 0x370a, 0x52 },
 647         { REG_VFIFO_READ_START_H, 0x00 },
 648         { REG_VFIFO_READ_START_L, 0xa0 },
 649         { REG_ISP_CTRL02, 0x10 },
 650         { REG_NULL, 0x00 },
 651 };
 652
 653 /* 320X240 QVGA */
 654 static  struct sensor_register ov2659_qvga[] = {
 655         { REG_TIMING_HS_H, 0x00 },
 656         { REG_TIMING_HS_L, 0x00 },
 657         { REG_TIMING_VS_H, 0x00 },
 658         { REG_TIMING_VS_L, 0x00 },
 659         { REG_TIMING_HW_H, 0x06 },
 660         { REG_TIMING_HW_L, 0x5f },
 661         { REG_TIMING_VH_H, 0x04 },
 662         { REG_TIMING_VH_L, 0xb7 },
 663         { REG_TIMING_DVPHO_H, 0x01 },
 664         { REG_TIMING_DVPHO_L, 0x40 },
 665         { REG_TIMING_DVPVO_H, 0x00 },
 666         { REG_TIMING_DVPVO_L, 0xf0 },
 667         { REG_TIMING_HTS_H, 0x05 },
 668         { REG_TIMING_HTS_L, 0x14 },
 669         { REG_TIMING_VTS_H, 0x02 },
 670         { REG_TIMING_VTS_L, 0x68 },
 671         { REG_TIMING_HOFFS_L, 0x08 },
 672         { REG_TIMING_VOFFS_L, 0x02 },
 673         { REG_TIMING_XINC, 0x31 },
 674         { REG_TIMING_YINC, 0x31 },
 675         { 0x3a02, 0x02 },
 676         { 0x3a03, 0x68 },
 677         { 0x3a08, 0x00 },
 678         { 0x3a09, 0x5c },
 679         { 0x3a0a, 0x00 },
 680         { 0x3a0b, 0x4d },
 681         { 0x3a0d, 0x08 },
 682         { 0x3a0e, 0x06 },
 683         { 0x3a14, 0x02 },
 684         { 0x3a15, 0x28 },
 685         { 0x3623, 0x00 },
 686         { 0x3634, 0x76 },
 687         { 0x3701, 0x44 },
 688         { 0x3702, 0x18 },
 689         { 0x3703, 0x24 },
 690         { 0x3704, 0x24 },
 691         { 0x3705, 0x0c },
 692         { REG_TIMING_VERT_FORMAT, 0x81 },
 693         { REG_TIMING_HORIZ_FORMAT, 0x01 },
 694         { 0x370a, 0x52 },
 695         { REG_VFIFO_READ_START_H, 0x00 },
 696         { REG_VFIFO_READ_START_L, 0xa0 },
 697         { REG_ISP_CTRL02, 0x10 },
 698         { REG_NULL, 0x00 },
 699 };
 700
 701 static const struct pll_ctrl_reg ctrl3[] = {
 702         { 1, 0x00 },
 703         { 2, 0x02 },
 704         { 3, 0x03 },
 705         { 4, 0x06 },
 706         { 6, 0x0d },
 707         { 8, 0x0e },
 708         { 12, 0x0f },
 709         { 16, 0x12 },
 710         { 24, 0x13 },
 711         { 32, 0x16 },
 712         { 48, 0x1b },
 713         { 64, 0x1e },
 714         { 96, 0x1f },
 715         { 0, 0x00 },
 716 };
 717
 718 static const struct pll_ctrl_reg ctrl1[] = {
 719         { 2, 0x10 },
 720         { 4, 0x20 },
 721         { 6, 0x30 },
 722         { 8, 0x40 },
 723         { 10, 0x50 },
 724         { 12, 0x60 },
 725         { 14, 0x70 },
 726         { 16, 0x80 },
 727         { 18, 0x90 },
 728         { 20, 0xa0 },
 729         { 22, 0xb0 },
 730         { 24, 0xc0 },
 731         { 26, 0xd0 },
 732         { 28, 0xe0 },
 733         { 30, 0xf0 },
 734         { 0, 0x00 },
 735 };
 736
 737 static const struct ov2659_framesize ov2659_framesizes[] = {
 738         { /* QVGA */
 739                 .width          = 320,
 740                 .height         = 240,
 741                 .regs           = ov2659_qvga,
 742                 .max_exp_lines  = 248,
 743         }, { /* VGA */
 744                 .width          = 640,
 745                 .height         = 480,
 746                 .regs           = ov2659_vga,
 747                 .max_exp_lines  = 498,
 748         }, { /* SVGA */
 749                 .width          = 800,
 750                 .height         = 600,
 751                 .regs           = ov2659_svga,
 752                 .max_exp_lines  = 498,
 753         }, { /* XGA */
 754                 .width          = 1024,
 755                 .height         = 768,
 756                 .regs           = ov2659_xga,
 757                 .max_exp_lines  = 498,
 758         }, { /* 720P */
 759                 .width          = 1280,
 760                 .height         = 720,
 761                 .regs           = ov2659_720p,
 762                 .max_exp_lines  = 498,
 763         }, { /* SXGA */
 764                 .width          = 1280,
 765                 .height         = 1024,
 766                 .regs           = ov2659_sxga,
 767                 .max_exp_lines  = 1048,
 768         }, { /* UXGA */
 769                 .width          = 1600,
 770                 .height         = 1200,
 771                 .regs           = ov2659_uxga,
 772                 .max_exp_lines  = 498,
 773         },
 774 };
 775
 776 /* YUV422 YUYV*/
 777 static struct sensor_register ov2659_format_yuyv[] = {
 778         { REG_FORMAT_CTRL00, 0x30 },
 779         { REG_NULL, 0x0 },
 780 };
 781
 782 /* YUV422 UYVY  */
 783 static struct sensor_register ov2659_format_uyvy[] = {
 784         { REG_FORMAT_CTRL00, 0x32 },
 785         { REG_NULL, 0x0 },
 786 };
 787
 788 /* Raw Bayer BGGR */
 789 static struct sensor_register ov2659_format_bggr[] = {
 790         { REG_FORMAT_CTRL00, 0x00 },
 791         { REG_NULL, 0x0 },
 792 };
 793
 794 /* RGB565 */
 795 static struct sensor_register ov2659_format_rgb565[] = {
 796         { REG_FORMAT_CTRL00, 0x60 },
 797         { REG_NULL, 0x0 },
 798 };
 799
 800 static const struct ov2659_pixfmt ov2659_formats[] = {
 801         {
 802                 .code = MEDIA_BUS_FMT_YUYV8_2X8,
 803                 .format_ctrl_regs = ov2659_format_yuyv,
 804         }, {
 805                 .code = MEDIA_BUS_FMT_UYVY8_2X8,
 806                 .format_ctrl_regs = ov2659_format_uyvy,
 807         }, {
 808                 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
 809                 .format_ctrl_regs = ov2659_format_rgb565,
 810         }, {
 811                 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
 812                 .format_ctrl_regs = ov2659_format_bggr,
 813         },
 814 };
 815
 816 static inline struct ov2659 *to_ov2659(struct v4l2_subdev *sd)
 817 {
 818         return container_of(sd, struct ov2659, sd);
 819 }
 820
 821 /* sensor register write */
 822 static int ov2659_write(struct i2c_client *client, u16 reg, u8 val)
 823 {
 824         struct i2c_msg msg;
 825         u8 buf[3];
 826         int ret;
 827
 828         buf[0] = reg >> 8;
 829         buf[1] = reg & 0xFF;
 830         buf[2] = val;
 831
 832         msg.addr = client->addr;
 833         msg.flags = client->flags;
 834         msg.buf = buf;
 835         msg.len = sizeof(buf);
 836
 837         ret = i2c_transfer(client->adapter, &msg, 1);
 838         if (ret >= 0)
 839                 return 0;
 840
 841         dev_dbg(&client->dev,
 842                 "ov2659 write reg(0x%x val:0x%x) failed !\n", reg, val);
 843
 844         return ret;
 845 }
 846
 847 /* sensor register read */
 848 static int ov2659_read(struct i2c_client *client, u16 reg, u8 *val)
 849 {
 850         struct i2c_msg msg[2];
 851         u8 buf[2];
 852         int ret;
 853
 854         buf[0] = reg >> 8;
 855         buf[1] = reg & 0xFF;
 856
 857         msg[0].addr = client->addr;
 858         msg[0].flags = client->flags;
 859         msg[0].buf = buf;
 860         msg[0].len = sizeof(buf);
 861
 862         msg[1].addr = client->addr;
 863         msg[1].flags = client->flags | I2C_M_RD;
 864         msg[1].buf = buf;
 865         msg[1].len = 1;
 866
 867         ret = i2c_transfer(client->adapter, msg, 2);
 868         if (ret >= 0) {
 869                 *val = buf[0];
 870                 return 0;
 871         }
 872
 873         dev_dbg(&client->dev,
 874                 "ov2659 read reg(0x%x val:0x%x) failed !\n", reg, *val);
 875
 876         return ret;
 877 }
 878
 879 static int ov2659_write_array(struct i2c_client *client,
 880                               const struct sensor_register *regs)
 881 {
 882         int i, ret = 0;
 883
 884         for (i = 0; ret == 0 && regs[i].addr; i++)
 885                 ret = ov2659_write(client, regs[i].addr, regs[i].value);
 886
 887         return ret;
 888 }
 889
 890 static void ov2659_pll_calc_params(struct ov2659 *ov2659)
 891 {
 892         const struct ov2659_platform_data *pdata = ov2659->pdata;
 893         u8 ctrl1_reg = 0, ctrl2_reg = 0, ctrl3_reg = 0;
 894         struct i2c_client *client = ov2659->client;
 895         unsigned int desired = pdata->link_frequency;
 896         u32 prediv, postdiv, mult;
 897         u32 bestdelta = -1;
 898         u32 delta, actual;
 899         int i, j;
 900
 901         for (i = 0; ctrl1[i].div != 0; i++) {
 902                 postdiv = ctrl1[i].div;
 903                 for (j = 0; ctrl3[j].div != 0; j++) {
 904                         prediv = ctrl3[j].div;
 905                         for (mult = 1; mult <= 63; mult++) {
 906                                 actual  = ov2659->xvclk_frequency;
 907                                 actual *= mult;
 908                                 actual /= prediv;
 909                                 actual /= postdiv;
 910                                 delta = actual - desired;
 911                                 delta = abs(delta);
 912
 913                                 if ((delta < bestdelta) || (bestdelta == -1)) {
 914                                         bestdelta = delta;
 915                                         ctrl1_reg = ctrl1[i].reg;
 916                                         ctrl2_reg = mult;
 917                                         ctrl3_reg = ctrl3[j].reg;
 918                                 }
 919                         }
 920                 }
 921         }
 922
 923         ov2659->pll.ctrl1 = ctrl1_reg;
 924         ov2659->pll.ctrl2 = ctrl2_reg;
 925         ov2659->pll.ctrl3 = ctrl3_reg;
 926
 927         dev_dbg(&client->dev,
 928                 "Actual reg config: ctrl1_reg: %02x ctrl2_reg: %02x ctrl3_reg: %02x\n",
 929                 ctrl1_reg, ctrl2_reg, ctrl3_reg);
 930 }
 931
 932 static int ov2659_set_pixel_clock(struct ov2659 *ov2659)
 933 {
 934         struct i2c_client *client = ov2659->client;
 935         struct sensor_register pll_regs[] = {
 936                 {REG_SC_PLL_CTRL1, ov2659->pll.ctrl1},
 937                 {REG_SC_PLL_CTRL2, ov2659->pll.ctrl2},
 938                 {REG_SC_PLL_CTRL3, ov2659->pll.ctrl3},
 939                 {REG_NULL, 0x00},
 940         };
 941
 942         dev_dbg(&client->dev, "%s\n", __func__);
 943
 944         return ov2659_write_array(client, pll_regs);
 945 };
 946
 947 static void ov2659_get_default_format(struct v4l2_mbus_framefmt *format)
 948 {
 949         format->width = ov2659_framesizes[2].width;
 950         format->height = ov2659_framesizes[2].height;
 951         format->colorspace = V4L2_COLORSPACE_SRGB;
 952         format->code = ov2659_formats[0].code;
 953         format->field = V4L2_FIELD_NONE;
 954 }
 955
 956 static void ov2659_set_streaming(struct ov2659 *ov2659, int on)
 957 {
 958         struct i2c_client *client = ov2659->client;
 959         int ret;
 960
 961         on = !!on;
 962
 963         dev_dbg(&client->dev, "%s: on: %d\n", __func__, on);
 964
 965         ret = ov2659_write(client, REG_SOFTWARE_STANDBY, on);
 966         if (ret)
 967                 dev_err(&client->dev, "ov2659 soft standby failed\n");
 968 }
 969
 970 static int ov2659_init(struct v4l2_subdev *sd, u32 val)
 971 {
 972         struct i2c_client *client = v4l2_get_subdevdata(sd);
 973
 974         return ov2659_write_array(client, ov2659_init_regs);
 975 }
 976
 977 /*
 978  * V4L2 subdev video and pad level operations
 979  */
 980
 981 static int ov2659_enum_mbus_code(struct v4l2_subdev *sd,
 982                                  struct v4l2_subdev_pad_config *cfg,
 983                                  struct v4l2_subdev_mbus_code_enum *code)
 984 {
 985         struct i2c_client *client = v4l2_get_subdevdata(sd);
 986
 987         dev_dbg(&client->dev, "%s:\n", __func__);
 988
 989         if (code->index >= ARRAY_SIZE(ov2659_formats))
 990                 return -EINVAL;
 991
 992         code->code = ov2659_formats[code->index].code;
 993
 994         return 0;
 995 }
 996
 997 static int ov2659_enum_frame_sizes(struct v4l2_subdev *sd,
 998                                    struct v4l2_subdev_pad_config *cfg,
 999                                    struct v4l2_subdev_frame_size_enum *fse)
1000 {
1001         struct i2c_client *client = v4l2_get_subdevdata(sd);
1002         int i = ARRAY_SIZE(ov2659_formats);
1003
1004         dev_dbg(&client->dev, "%s:\n", __func__);
1005
1006         if (fse->index >= ARRAY_SIZE(ov2659_framesizes))
1007                 return -EINVAL;
1008
1009         while (--i)
1010                 if (fse->code == ov2659_formats[i].code)
1011                         break;
1012
1013         fse->code = ov2659_formats[i].code;
1014
1015         fse->min_width  = ov2659_framesizes[fse->index].width;
1016         fse->max_width  = fse->min_width;
1017         fse->max_height = ov2659_framesizes[fse->index].height;
1018         fse->min_height = fse->max_height;
1019
1020         return 0;
1021 }
1022
1023 static int ov2659_get_fmt(struct v4l2_subdev *sd,
1024                           struct v4l2_subdev_pad_config *cfg,
1025                           struct v4l2_subdev_format *fmt)
1026 {
1027         struct i2c_client *client = v4l2_get_subdevdata(sd);
1028         struct ov2659 *ov2659 = to_ov2659(sd);
1029
1030         dev_dbg(&client->dev, "ov2659_get_fmt\n");
1031
1032         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1033 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1034                 struct v4l2_mbus_framefmt *mf;
1035
1036                 mf = v4l2_subdev_get_try_format(sd, cfg, 0);
1037                 mutex_lock(&ov2659->lock);
1038                 fmt->format = *mf;
1039                 mutex_unlock(&ov2659->lock);
1040                 return 0;
1041 #else
1042                 return -EINVAL;
1043 #endif
1044         }
1045
1046         mutex_lock(&ov2659->lock);
1047         fmt->format = ov2659->format;
1048         mutex_unlock(&ov2659->lock);
1049
1050         dev_dbg(&client->dev, "ov2659_get_fmt: %x %dx%d\n",
1051                 ov2659->format.code, ov2659->format.width,
1052                 ov2659->format.height);
1053
1054         return 0;
1055 }
1056
1057 static void __ov2659_try_frame_size(struct v4l2_mbus_framefmt *mf,
1058                                     const struct ov2659_framesize **size)
1059 {
1060         const struct ov2659_framesize *fsize = &ov2659_framesizes[0];
1061         const struct ov2659_framesize *match = NULL;
1062         int i = ARRAY_SIZE(ov2659_framesizes);
1063         unsigned int min_err = UINT_MAX;
1064
1065         while (i--) {
1066                 int err = abs(fsize->width - mf->width)
1067                                 + abs(fsize->height - mf->height);
1068                 if ((err < min_err) && (fsize->regs[0].addr)) {
1069                         min_err = err;
1070                         match = fsize;
1071                 }
1072                 fsize++;
1073         }
1074
1075         if (!match)
1076                 match = &ov2659_framesizes[2];
1077
1078         mf->width  = match->width;
1079         mf->height = match->height;
1080
1081         if (size)
1082                 *size = match;
1083 }
1084
1085 static int ov2659_set_fmt(struct v4l2_subdev *sd,
1086                           struct v4l2_subdev_pad_config *cfg,
1087                           struct v4l2_subdev_format *fmt)
1088 {
1089         struct i2c_client *client = v4l2_get_subdevdata(sd);
1090         int index = ARRAY_SIZE(ov2659_formats);
1091         struct v4l2_mbus_framefmt *mf = &fmt->format;
1092         const struct ov2659_framesize *size = NULL;
1093         struct ov2659 *ov2659 = to_ov2659(sd);
1094         int ret = 0;
1095
1096         dev_dbg(&client->dev, "ov2659_set_fmt\n");
1097
1098         __ov2659_try_frame_size(mf, &size);
1099
1100         while (--index >= 0)
1101                 if (ov2659_formats[index].code == mf->code)
1102                         break;
1103
1104         if (index < 0) {
1105                 index = 0;
1106                 mf->code = ov2659_formats[index].code;
1107         }
1108
1109         mf->colorspace = V4L2_COLORSPACE_SRGB;
1110         mf->field = V4L2_FIELD_NONE;
1111
1112         mutex_lock(&ov2659->lock);
1113
1114         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1115 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1116                 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1117                 *mf = fmt->format;
1118 #endif
1119         } else {
1120                 s64 val;
1121
1122                 if (ov2659->streaming) {
1123                         mutex_unlock(&ov2659->lock);
1124                         return -EBUSY;
1125                 }
1126
1127                 ov2659->frame_size = size;
1128                 ov2659->format = fmt->format;
1129                 ov2659->format_ctrl_regs =
1130                         ov2659_formats[index].format_ctrl_regs;
1131
1132                 if (ov2659->format.code != MEDIA_BUS_FMT_SBGGR8_1X8)
1133                         val = ov2659->pdata->link_frequency / 2;
1134                 else
1135                         val = ov2659->pdata->link_frequency;
1136
1137                 ret = v4l2_ctrl_s_ctrl_int64(ov2659->link_frequency, val);
1138                 if (ret < 0)
1139                         dev_warn(&client->dev,
1140                                  "failed to set link_frequency rate (%d)\n",
1141                                  ret);
1142         }
1143
1144         mutex_unlock(&ov2659->lock);
1145         return ret;
1146 }
1147
1148 static int ov2659_set_frame_size(struct ov2659 *ov2659)
1149 {
1150         struct i2c_client *client = ov2659->client;
1151
1152         dev_dbg(&client->dev, "%s\n", __func__);
1153
1154         return ov2659_write_array(ov2659->client, ov2659->frame_size->regs);
1155 }
1156
1157 static int ov2659_set_format(struct ov2659 *ov2659)
1158 {
1159         struct i2c_client *client = ov2659->client;
1160
1161         dev_dbg(&client->dev, "%s\n", __func__);
1162
1163         return ov2659_write_array(ov2659->client, ov2659->format_ctrl_regs);
1164 }
1165
1166 static int ov2659_s_stream(struct v4l2_subdev *sd, int on)
1167 {
1168         struct i2c_client *client = v4l2_get_subdevdata(sd);
1169         struct ov2659 *ov2659 = to_ov2659(sd);
1170         int ret = 0;
1171
1172         dev_dbg(&client->dev, "%s: on: %d\n", __func__, on);
1173
1174         mutex_lock(&ov2659->lock);
1175
1176         on = !!on;
1177
1178         if (ov2659->streaming == on)
1179                 goto unlock;
1180
1181         if (!on) {
1182                 /* Stop Streaming Sequence */
1183                 ov2659_set_streaming(ov2659, 0);
1184                 ov2659->streaming = on;
1185                 pm_runtime_put(&client->dev);
1186                 goto unlock;
1187         }
1188
1189         ret = pm_runtime_get_sync(&client->dev);
1190         if (ret < 0) {
1191                 pm_runtime_put_noidle(&client->dev);
1192                 goto unlock;
1193         }
1194
1195         ret = ov2659_init(sd, 0);
1196         if (!ret)
1197                 ret = ov2659_set_pixel_clock(ov2659);
1198         if (!ret)
1199                 ret = ov2659_set_frame_size(ov2659);
1200         if (!ret)
1201                 ret = ov2659_set_format(ov2659);
1202         if (!ret) {
1203                 ov2659_set_streaming(ov2659, 1);
1204                 ov2659->streaming = on;
1205         }
1206
1207 unlock:
1208         mutex_unlock(&ov2659->lock);
1209         return ret;
1210 }
1211
1212 static int ov2659_set_test_pattern(struct ov2659 *ov2659, int value)
1213 {
1214         struct i2c_client *client = v4l2_get_subdevdata(&ov2659->sd);
1215         int ret;
1216         u8 val;
1217
1218         ret = ov2659_read(client, REG_PRE_ISP_CTRL00, &val);
1219         if (ret < 0)
1220                 return ret;
1221
1222         switch (value) {
1223         case 0:
1224                 val &= ~TEST_PATTERN_ENABLE;
1225                 break;
1226         case 1:
1227                 val &= VERTICAL_COLOR_BAR_MASK;
1228                 val |= TEST_PATTERN_ENABLE;
1229                 break;
1230         }
1231
1232         return ov2659_write(client, REG_PRE_ISP_CTRL00, val);
1233 }
1234
1235 static int ov2659_s_ctrl(struct v4l2_ctrl *ctrl)
1236 {
1237         struct ov2659 *ov2659 =
1238                         container_of(ctrl->handler, struct ov2659, ctrls);
1239         struct i2c_client *client = ov2659->client;
1240
1241         /* V4L2 controls values will be applied only when power is already up */
1242         if (!pm_runtime_get_if_in_use(&client->dev))
1243                 return 0;
1244
1245         switch (ctrl->id) {
1246         case V4L2_CID_TEST_PATTERN:
1247                 return ov2659_set_test_pattern(ov2659, ctrl->val);
1248         }
1249
1250         pm_runtime_put(&client->dev);
1251         return 0;
1252 }
1253
1254 static const struct v4l2_ctrl_ops ov2659_ctrl_ops = {
1255         .s_ctrl = ov2659_s_ctrl,
1256 };
1257
1258 static const char * const ov2659_test_pattern_menu[] = {
1259         "Disabled",
1260         "Vertical Color Bars",
1261 };
1262
1263 static int ov2659_power_off(struct device *dev)
1264 {
1265         struct i2c_client *client = to_i2c_client(dev);
1266         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1267         struct ov2659 *ov2659 = to_ov2659(sd);
1268
1269         dev_dbg(&client->dev, "%s:\n", __func__);
1270
1271         gpiod_set_value(ov2659->pwdn_gpio, 1);
1272
1273         return 0;
1274 }
1275
1276 static int ov2659_power_on(struct device *dev)
1277 {
1278         struct i2c_client *client = to_i2c_client(dev);
1279         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1280         struct ov2659 *ov2659 = to_ov2659(sd);
1281
1282         dev_dbg(&client->dev, "%s:\n", __func__);
1283
1284         gpiod_set_value(ov2659->pwdn_gpio, 0);
1285
1286         if (ov2659->resetb_gpio) {
1287                 gpiod_set_value(ov2659->resetb_gpio, 1);
1288                 usleep_range(500, 1000);
1289                 gpiod_set_value(ov2659->resetb_gpio, 0);
1290                 usleep_range(3000, 5000);
1291         }
1292
1293         return 0;
1294 }
1295
1296 /* -----------------------------------------------------------------------------
1297  * V4L2 subdev internal operations
1298  */
1299
1300 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1301 static int ov2659_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1302 {
1303         struct i2c_client *client = v4l2_get_subdevdata(sd);
1304         struct v4l2_mbus_framefmt *format =
1305                                 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1306
1307         dev_dbg(&client->dev, "%s:\n", __func__);
1308
1309         ov2659_get_default_format(format);
1310
1311         return 0;
1312 }
1313 #endif
1314
1315 static const struct v4l2_subdev_core_ops ov2659_subdev_core_ops = {
1316         .log_status = v4l2_ctrl_subdev_log_status,
1317         .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1318         .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1319 };
1320
1321 static const struct v4l2_subdev_video_ops ov2659_subdev_video_ops = {
1322         .s_stream = ov2659_s_stream,
1323 };
1324
1325 static const struct v4l2_subdev_pad_ops ov2659_subdev_pad_ops = {
1326         .enum_mbus_code = ov2659_enum_mbus_code,
1327         .enum_frame_size = ov2659_enum_frame_sizes,
1328         .get_fmt = ov2659_get_fmt,
1329         .set_fmt = ov2659_set_fmt,
1330 };
1331
1332 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1333 static const struct v4l2_subdev_ops ov2659_subdev_ops = {
1334         .core  = &ov2659_subdev_core_ops,
1335         .video = &ov2659_subdev_video_ops,
1336         .pad   = &ov2659_subdev_pad_ops,
1337 };
1338
1339 static const struct v4l2_subdev_internal_ops ov2659_subdev_internal_ops = {
1340         .open = ov2659_open,
1341 };
1342 #endif
1343
1344 static int ov2659_detect(struct v4l2_subdev *sd)
1345 {
1346         struct i2c_client *client = v4l2_get_subdevdata(sd);
1347         u8 pid = 0;
1348         u8 ver = 0;
1349         int ret;
1350
1351         dev_dbg(&client->dev, "%s:\n", __func__);
1352
1353         ret = ov2659_write(client, REG_SOFTWARE_RESET, 0x01);
1354         if (ret != 0) {
1355                 dev_err(&client->dev, "Sensor soft reset failed\n");
1356                 return -ENODEV;
1357         }
1358         usleep_range(1000, 2000);
1359
1360         /* Check sensor revision */
1361         ret = ov2659_read(client, REG_SC_CHIP_ID_H, &pid);
1362         if (!ret)
1363                 ret = ov2659_read(client, REG_SC_CHIP_ID_L, &ver);
1364
1365         if (!ret) {
1366                 unsigned short id;
1367
1368                 id = OV265X_ID(pid, ver);
1369                 if (id != OV2659_ID) {
1370                         dev_err(&client->dev,
1371                                 "Sensor detection failed (%04X, %d)\n",
1372                                 id, ret);
1373                         ret = -ENODEV;
1374                 } else {
1375                         dev_info(&client->dev, "Found OV%04X sensor\n", id);
1376                 }
1377         }
1378
1379         return ret;
1380 }
1381
1382 static struct ov2659_platform_data *
1383 ov2659_get_pdata(struct i2c_client *client)
1384 {
1385         struct ov2659_platform_data *pdata;
1386         struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
1387         struct device_node *endpoint;
1388         int ret;
1389
1390         if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
1391                 return client->dev.platform_data;
1392
1393         endpoint = of_graph_get_next_endpoint(client->dev.of_node, NULL);
1394         if (!endpoint)
1395                 return NULL;
1396
1397         ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(endpoint),
1398                                                &bus_cfg);
1399         if (ret) {
1400                 pdata = NULL;
1401                 goto done;
1402         }
1403
1404         pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1405         if (!pdata)
1406                 goto done;
1407
1408         if (!bus_cfg.nr_of_link_frequencies) {
1409                 dev_err(&client->dev,
1410                         "link-frequencies property not found or too many\n");
1411                 pdata = NULL;
1412                 goto done;
1413         }
1414
1415         pdata->link_frequency = bus_cfg.link_frequencies[0];
1416
1417 done:
1418         v4l2_fwnode_endpoint_free(&bus_cfg);
1419         of_node_put(endpoint);
1420         return pdata;
1421 }
1422
1423 static int ov2659_probe(struct i2c_client *client)
1424 {
1425         const struct ov2659_platform_data *pdata = ov2659_get_pdata(client);
1426         struct v4l2_subdev *sd;
1427         struct ov2659 *ov2659;
1428         struct clk *clk;
1429         int ret;
1430
1431         if (!pdata) {
1432                 dev_err(&client->dev, "platform data not specified\n");
1433                 return -EINVAL;
1434         }
1435
1436         ov2659 = devm_kzalloc(&client->dev, sizeof(*ov2659), GFP_KERNEL);
1437         if (!ov2659)
1438                 return -ENOMEM;
1439
1440         ov2659->pdata = pdata;
1441         ov2659->client = client;
1442
1443         clk = devm_clk_get(&client->dev, "xvclk");
1444         if (IS_ERR(clk))
1445                 return PTR_ERR(clk);
1446
1447         ov2659->xvclk_frequency = clk_get_rate(clk);
1448         if (ov2659->xvclk_frequency < 6000000 ||
1449             ov2659->xvclk_frequency > 27000000)
1450                 return -EINVAL;
1451
1452         /* Optional gpio don't fail if not present */
1453         ov2659->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
1454                                                     GPIOD_OUT_LOW);
1455         if (IS_ERR(ov2659->pwdn_gpio))
1456                 return PTR_ERR(ov2659->pwdn_gpio);
1457
1458         /* Optional gpio don't fail if not present */
1459         ov2659->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1460                                                       GPIOD_OUT_HIGH);
1461         if (IS_ERR(ov2659->resetb_gpio))
1462                 return PTR_ERR(ov2659->resetb_gpio);
1463
1464         v4l2_ctrl_handler_init(&ov2659->ctrls, 2);
1465         ov2659->link_frequency =
1466                         v4l2_ctrl_new_std(&ov2659->ctrls, &ov2659_ctrl_ops,
1467                                           V4L2_CID_PIXEL_RATE,
1468                                           pdata->link_frequency / 2,
1469                                           pdata->link_frequency, 1,
1470                                           pdata->link_frequency);
1471         v4l2_ctrl_new_std_menu_items(&ov2659->ctrls, &ov2659_ctrl_ops,
1472                                      V4L2_CID_TEST_PATTERN,
1473                                      ARRAY_SIZE(ov2659_test_pattern_menu) - 1,
1474                                      0, 0, ov2659_test_pattern_menu);
1475         ov2659->sd.ctrl_handler = &ov2659->ctrls;
1476
1477         if (ov2659->ctrls.error) {
1478                 dev_err(&client->dev, "%s: control initialization error %d\n",
1479                         __func__, ov2659->ctrls.error);
1480                 return  ov2659->ctrls.error;
1481         }
1482
1483         sd = &ov2659->sd;
1484         client->flags |= I2C_CLIENT_SCCB;
1485 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1486         v4l2_i2c_subdev_init(sd, client, &ov2659_subdev_ops);
1487
1488         sd->internal_ops = &ov2659_subdev_internal_ops;
1489         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1490                      V4L2_SUBDEV_FL_HAS_EVENTS;
1491 #endif
1492
1493 #if defined(CONFIG_MEDIA_CONTROLLER)
1494         ov2659->pad.flags = MEDIA_PAD_FL_SOURCE;
1495         sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1496         ret = media_entity_pads_init(&sd->entity, 1, &ov2659->pad);
1497         if (ret < 0) {
1498                 v4l2_ctrl_handler_free(&ov2659->ctrls);
1499                 return ret;
1500         }
1501 #endif
1502
1503         mutex_init(&ov2659->lock);
1504
1505         ov2659_get_default_format(&ov2659->format);
1506         ov2659->frame_size = &ov2659_framesizes[2];
1507         ov2659->format_ctrl_regs = ov2659_formats[0].format_ctrl_regs;
1508
1509         ov2659_power_on(&client->dev);
1510
1511         ret = ov2659_detect(sd);
1512         if (ret < 0)
1513                 goto error;
1514
1515         /* Calculate the PLL register value needed */
1516         ov2659_pll_calc_params(ov2659);
1517
1518         ret = v4l2_async_register_subdev(&ov2659->sd);
1519         if (ret)
1520                 goto error;
1521
1522         dev_info(&client->dev, "%s sensor driver registered !!\n", sd->name);
1523
1524         pm_runtime_set_active(&client->dev);
1525         pm_runtime_enable(&client->dev);
1526         pm_runtime_idle(&client->dev);
1527
1528         return 0;
1529
1530 error:
1531         v4l2_ctrl_handler_free(&ov2659->ctrls);
1532         ov2659_power_off(&client->dev);
1533         media_entity_cleanup(&sd->entity);
1534         mutex_destroy(&ov2659->lock);
1535         return ret;
1536 }
1537
1538 static int ov2659_remove(struct i2c_client *client)
1539 {
1540         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1541         struct ov2659 *ov2659 = to_ov2659(sd);
1542
1543         v4l2_ctrl_handler_free(&ov2659->ctrls);
1544         v4l2_async_unregister_subdev(sd);
1545         media_entity_cleanup(&sd->entity);
1546         mutex_destroy(&ov2659->lock);
1547
1548         pm_runtime_disable(&client->dev);
1549         if (!pm_runtime_status_suspended(&client->dev))
1550                 ov2659_power_off(&client->dev);
1551         pm_runtime_set_suspended(&client->dev);
1552
1553         return 0;
1554 }
1555
1556 static const struct dev_pm_ops ov2659_pm_ops = {
1557         SET_RUNTIME_PM_OPS(ov2659_power_off, ov2659_power_on, NULL)
1558 };
1559
1560 static const struct i2c_device_id ov2659_id[] = {
1561         { "ov2659", 0 },
1562         { /* sentinel */ },
1563 };
1564 MODULE_DEVICE_TABLE(i2c, ov2659_id);
1565
1566 #if IS_ENABLED(CONFIG_OF)
1567 static const struct of_device_id ov2659_of_match[] = {
1568         { .compatible = "ovti,ov2659", },
1569         { /* sentinel */ },
1570 };
1571 MODULE_DEVICE_TABLE(of, ov2659_of_match);
1572 #endif
1573
1574 static struct i2c_driver ov2659_i2c_driver = {
1575         .driver = {
1576                 .name   = DRIVER_NAME,
1577                 .pm     = &ov2659_pm_ops,
1578                 .of_match_table = of_match_ptr(ov2659_of_match),
1579         },
1580         .probe_new      = ov2659_probe,
1581         .remove         = ov2659_remove,
1582         .id_table       = ov2659_id,
1583 };
1584
1585 module_i2c_driver(ov2659_i2c_driver);
1586
1587 MODULE_AUTHOR("Benoit Parrot <bparrot@ti.com>");
1588 MODULE_DESCRIPTION("OV2659 CMOS Image Sensor driver");
1589 MODULE_LICENSE("GPL v2");