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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / media / i2c / ov7670.c
blobb42b289faaef4cfdd82b57a4db59316df61d2056
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * A V4L2 driver for OmniVision OV7670 cameras.
4 *
5 * Copyright 2006 One Laptop Per Child Association, Inc. Written
6 * by Jonathan Corbet with substantial inspiration from Mark
7 * McClelland's ovcamchip code.
8 *
9 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
10 */
11 #include <linux/clk.h>
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/slab.h>
15 #include <linux/i2c.h>
16 #include <linux/delay.h>
17 #include <linux/videodev2.h>
18 #include <linux/gpio.h>
19 #include <linux/gpio/consumer.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-event.h>
22 #include <media/v4l2-ctrls.h>
23 #include <media/v4l2-fwnode.h>
24 #include <media/v4l2-mediabus.h>
25 #include <media/v4l2-image-sizes.h>
26 #include <media/i2c/ov7670.h>
27
28 MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
29 MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors");
30 MODULE_LICENSE("GPL");
31
32 static bool debug;
33 module_param(debug, bool, 0644);
34 MODULE_PARM_DESC(debug, "Debug level (0-1)");
35
36 /*
37 * The 7670 sits on i2c with ID 0x42
38 */
39 #define OV7670_I2C_ADDR 0x42
40
41 #define PLL_FACTOR 4
42
43 /* Registers */
44 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
45 #define REG_BLUE 0x01 /* blue gain */
46 #define REG_RED 0x02 /* red gain */
47 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
48 #define REG_COM1 0x04 /* Control 1 */
49 #define COM1_CCIR656 0x40 /* CCIR656 enable */
50 #define REG_BAVE 0x05 /* U/B Average level */
51 #define REG_GbAVE 0x06 /* Y/Gb Average level */
52 #define REG_AECHH 0x07 /* AEC MS 5 bits */
53 #define REG_RAVE 0x08 /* V/R Average level */
54 #define REG_COM2 0x09 /* Control 2 */
55 #define COM2_SSLEEP 0x10 /* Soft sleep mode */
56 #define REG_PID 0x0a /* Product ID MSB */
57 #define REG_VER 0x0b /* Product ID LSB */
58 #define REG_COM3 0x0c /* Control 3 */
59 #define COM3_SWAP 0x40 /* Byte swap */
60 #define COM3_SCALEEN 0x08 /* Enable scaling */
61 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
62 #define REG_COM4 0x0d /* Control 4 */
63 #define REG_COM5 0x0e /* All "reserved" */
64 #define REG_COM6 0x0f /* Control 6 */
65 #define REG_AECH 0x10 /* More bits of AEC value */
66 #define REG_CLKRC 0x11 /* Clocl control */
67 #define CLK_EXT 0x40 /* Use external clock directly */
68 #define CLK_SCALE 0x3f /* Mask for internal clock scale */
69 #define REG_COM7 0x12 /* Control 7 */
70 #define COM7_RESET 0x80 /* Register reset */
71 #define COM7_FMT_MASK 0x38
72 #define COM7_FMT_VGA 0x00
73 #define COM7_FMT_CIF 0x20 /* CIF format */
74 #define COM7_FMT_QVGA 0x10 /* QVGA format */
75 #define COM7_FMT_QCIF 0x08 /* QCIF format */
76 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
77 #define COM7_YUV 0x00 /* YUV */
78 #define COM7_BAYER 0x01 /* Bayer format */
79 #define COM7_PBAYER 0x05 /* "Processed bayer" */
80 #define REG_COM8 0x13 /* Control 8 */
81 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
82 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
83 #define COM8_BFILT 0x20 /* Band filter enable */
84 #define COM8_AGC 0x04 /* Auto gain enable */
85 #define COM8_AWB 0x02 /* White balance enable */
86 #define COM8_AEC 0x01 /* Auto exposure enable */
87 #define REG_COM9 0x14 /* Control 9 - gain ceiling */
88 #define REG_COM10 0x15 /* Control 10 */
89 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
90 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
91 #define COM10_HREF_REV 0x08 /* Reverse HREF */
92 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
93 #define COM10_VS_NEG 0x02 /* VSYNC negative */
94 #define COM10_HS_NEG 0x01 /* HSYNC negative */
95 #define REG_HSTART 0x17 /* Horiz start high bits */
96 #define REG_HSTOP 0x18 /* Horiz stop high bits */
97 #define REG_VSTART 0x19 /* Vert start high bits */
98 #define REG_VSTOP 0x1a /* Vert stop high bits */
99 #define REG_PSHFT 0x1b /* Pixel delay after HREF */
100 #define REG_MIDH 0x1c /* Manuf. ID high */
101 #define REG_MIDL 0x1d /* Manuf. ID low */
102 #define REG_MVFP 0x1e /* Mirror / vflip */
103 #define MVFP_MIRROR 0x20 /* Mirror image */
104 #define MVFP_FLIP 0x10 /* Vertical flip */
105
106 #define REG_AEW 0x24 /* AGC upper limit */
107 #define REG_AEB 0x25 /* AGC lower limit */
108 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
109 #define REG_HSYST 0x30 /* HSYNC rising edge delay */
110 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
111 #define REG_HREF 0x32 /* HREF pieces */
112 #define REG_TSLB 0x3a /* lots of stuff */
113 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
114 #define REG_COM11 0x3b /* Control 11 */
115 #define COM11_NIGHT 0x80 /* NIght mode enable */
116 #define COM11_NMFR 0x60 /* Two bit NM frame rate */
117 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
118 #define COM11_50HZ 0x08 /* Manual 50Hz select */
119 #define COM11_EXP 0x02
120 #define REG_COM12 0x3c /* Control 12 */
121 #define COM12_HREF 0x80 /* HREF always */
122 #define REG_COM13 0x3d /* Control 13 */
123 #define COM13_GAMMA 0x80 /* Gamma enable */
124 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
125 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
126 #define REG_COM14 0x3e /* Control 14 */
127 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
128 #define REG_EDGE 0x3f /* Edge enhancement factor */
129 #define REG_COM15 0x40 /* Control 15 */
130 #define COM15_R10F0 0x00 /* Data range 10 to F0 */
131 #define COM15_R01FE 0x80 /* 01 to FE */
132 #define COM15_R00FF 0xc0 /* 00 to FF */
133 #define COM15_RGB565 0x10 /* RGB565 output */
134 #define COM15_RGB555 0x30 /* RGB555 output */
135 #define REG_COM16 0x41 /* Control 16 */
136 #define COM16_AWBGAIN 0x08 /* AWB gain enable */
137 #define REG_COM17 0x42 /* Control 17 */
138 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
139 #define COM17_CBAR 0x08 /* DSP Color bar */
140
141 /*
142 * This matrix defines how the colors are generated, must be
143 * tweaked to adjust hue and saturation.
144 *
145 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
146 *
147 * They are nine-bit signed quantities, with the sign bit
148 * stored in 0x58. Sign for v-red is bit 0, and up from there.
149 */
150 #define REG_CMATRIX_BASE 0x4f
151 #define CMATRIX_LEN 6
152 #define REG_CMATRIX_SIGN 0x58
153
154
155 #define REG_BRIGHT 0x55 /* Brightness */
156 #define REG_CONTRAS 0x56 /* Contrast control */
157
158 #define REG_GFIX 0x69 /* Fix gain control */
159
160 #define REG_DBLV 0x6b /* PLL control an debugging */
161 #define DBLV_BYPASS 0x0a /* Bypass PLL */
162 #define DBLV_X4 0x4a /* clock x4 */
163 #define DBLV_X6 0x8a /* clock x6 */
164 #define DBLV_X8 0xca /* clock x8 */
165
166 #define REG_SCALING_XSC 0x70 /* Test pattern and horizontal scale factor */
167 #define TEST_PATTTERN_0 0x80
168 #define REG_SCALING_YSC 0x71 /* Test pattern and vertical scale factor */
169 #define TEST_PATTTERN_1 0x80
170
171 #define REG_REG76 0x76 /* OV's name */
172 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
173 #define R76_WHTPCOR 0x40 /* White pixel correction enable */
174
175 #define REG_RGB444 0x8c /* RGB 444 control */
176 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
177 #define R444_RGBX 0x01 /* Empty nibble at end */
178
179 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
180 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
181
182 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
183 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
184 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
185 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
186 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
187 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
188 #define REG_BD60MAX 0xab /* 60hz banding step limit */
189
190 enum ov7670_model {
191 MODEL_OV7670 = 0,
192 MODEL_OV7675,
193 };
194
195 struct ov7670_win_size {
196 int width;
197 int height;
198 unsigned char com7_bit;
199 int hstart; /* Start/stop values for the camera. Note */
200 int hstop; /* that they do not always make complete */
201 int vstart; /* sense to humans, but evidently the sensor */
202 int vstop; /* will do the right thing... */
203 struct regval_list *regs; /* Regs to tweak */
204 };
205
206 struct ov7670_devtype {
207 /* formats supported for each model */
208 struct ov7670_win_size *win_sizes;
209 unsigned int n_win_sizes;
210 /* callbacks for frame rate control */
211 int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
212 void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
213 };
214
215 /*
216 * Information we maintain about a known sensor.
217 */
218 struct ov7670_format_struct; /* coming later */
219 struct ov7670_info {
220 struct v4l2_subdev sd;
221 #if defined(CONFIG_MEDIA_CONTROLLER)
222 struct media_pad pad;
223 #endif
224 struct v4l2_ctrl_handler hdl;
225 struct {
226 /* gain cluster */
227 struct v4l2_ctrl *auto_gain;
228 struct v4l2_ctrl *gain;
229 };
230 struct {
231 /* exposure cluster */
232 struct v4l2_ctrl *auto_exposure;
233 struct v4l2_ctrl *exposure;
234 };
235 struct {
236 /* saturation/hue cluster */
237 struct v4l2_ctrl *saturation;
238 struct v4l2_ctrl *hue;
239 };
240 struct v4l2_mbus_framefmt format;
241 struct ov7670_format_struct *fmt; /* Current format */
242 struct ov7670_win_size *wsize;
243 struct clk *clk;
244 int on;
245 struct gpio_desc *resetb_gpio;
246 struct gpio_desc *pwdn_gpio;
247 unsigned int mbus_config; /* Media bus configuration flags */
248 int min_width; /* Filter out smaller sizes */
249 int min_height; /* Filter out smaller sizes */
250 int clock_speed; /* External clock speed (MHz) */
251 u8 clkrc; /* Clock divider value */
252 bool use_smbus; /* Use smbus I/O instead of I2C */
253 bool pll_bypass;
254 bool pclk_hb_disable;
255 const struct ov7670_devtype *devtype; /* Device specifics */
256 };
257
258 static inline struct ov7670_info *to_state(struct v4l2_subdev *sd)
259 {
260 return container_of(sd, struct ov7670_info, sd);
261 }
262
263 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
264 {
265 return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd;
266 }
267
268
269
270 /*
271 * The default register settings, as obtained from OmniVision. There
272 * is really no making sense of most of these - lots of "reserved" values
273 * and such.
274 *
275 * These settings give VGA YUYV.
276 */
277
278 struct regval_list {
279 unsigned char reg_num;
280 unsigned char value;
281 };
282
283 static struct regval_list ov7670_default_regs[] = {
284 { REG_COM7, COM7_RESET },
285 /*
286 * Clock scale: 3 = 15fps
287 * 2 = 20fps
288 * 1 = 30fps
289 */
290 { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */
291 { REG_TSLB, 0x04 }, /* OV */
292 { REG_COM7, 0 }, /* VGA */
293 /*
294 * Set the hardware window. These values from OV don't entirely
295 * make sense - hstop is less than hstart. But they work...
296 */
297 { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 },
298 { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 },
299 { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a },
300
301 { REG_COM3, 0 }, { REG_COM14, 0 },
302 /* Mystery scaling numbers */
303 { REG_SCALING_XSC, 0x3a },
304 { REG_SCALING_YSC, 0x35 },
305 { 0x72, 0x11 }, { 0x73, 0xf0 },
306 { 0xa2, 0x02 }, { REG_COM10, 0x0 },
307
308 /* Gamma curve values */
309 { 0x7a, 0x20 }, { 0x7b, 0x10 },
310 { 0x7c, 0x1e }, { 0x7d, 0x35 },
311 { 0x7e, 0x5a }, { 0x7f, 0x69 },
312 { 0x80, 0x76 }, { 0x81, 0x80 },
313 { 0x82, 0x88 }, { 0x83, 0x8f },
314 { 0x84, 0x96 }, { 0x85, 0xa3 },
315 { 0x86, 0xaf }, { 0x87, 0xc4 },
316 { 0x88, 0xd7 }, { 0x89, 0xe8 },
317
318 /* AGC and AEC parameters. Note we start by disabling those features,
319 then turn them only after tweaking the values. */
320 { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT },
321 { REG_GAIN, 0 }, { REG_AECH, 0 },
322 { REG_COM4, 0x40 }, /* magic reserved bit */
323 { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
324 { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 },
325 { REG_AEW, 0x95 }, { REG_AEB, 0x33 },
326 { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 },
327 { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */
328 { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 },
329 { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 },
330 { REG_HAECC7, 0x94 },
331 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC },
332
333 /* Almost all of these are magic "reserved" values. */
334 { REG_COM5, 0x61 }, { REG_COM6, 0x4b },
335 { 0x16, 0x02 }, { REG_MVFP, 0x07 },
336 { 0x21, 0x02 }, { 0x22, 0x91 },
337 { 0x29, 0x07 }, { 0x33, 0x0b },
338 { 0x35, 0x0b }, { 0x37, 0x1d },
339 { 0x38, 0x71 }, { 0x39, 0x2a },
340 { REG_COM12, 0x78 }, { 0x4d, 0x40 },
341 { 0x4e, 0x20 }, { REG_GFIX, 0 },
342 { 0x6b, 0x4a }, { 0x74, 0x10 },
343 { 0x8d, 0x4f }, { 0x8e, 0 },
344 { 0x8f, 0 }, { 0x90, 0 },
345 { 0x91, 0 }, { 0x96, 0 },
346 { 0x9a, 0 }, { 0xb0, 0x84 },
347 { 0xb1, 0x0c }, { 0xb2, 0x0e },
348 { 0xb3, 0x82 }, { 0xb8, 0x0a },
349
350 /* More reserved magic, some of which tweaks white balance */
351 { 0x43, 0x0a }, { 0x44, 0xf0 },
352 { 0x45, 0x34 }, { 0x46, 0x58 },
353 { 0x47, 0x28 }, { 0x48, 0x3a },
354 { 0x59, 0x88 }, { 0x5a, 0x88 },
355 { 0x5b, 0x44 }, { 0x5c, 0x67 },
356 { 0x5d, 0x49 }, { 0x5e, 0x0e },
357 { 0x6c, 0x0a }, { 0x6d, 0x55 },
358 { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */
359 { 0x6a, 0x40 }, { REG_BLUE, 0x40 },
360 { REG_RED, 0x60 },
361 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB },
362
363 /* Matrix coefficients */
364 { 0x4f, 0x80 }, { 0x50, 0x80 },
365 { 0x51, 0 }, { 0x52, 0x22 },
366 { 0x53, 0x5e }, { 0x54, 0x80 },
367 { 0x58, 0x9e },
368
369 { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 },
370 { 0x75, 0x05 }, { 0x76, 0xe1 },
371 { 0x4c, 0 }, { 0x77, 0x01 },
372 { REG_COM13, 0xc3 }, { 0x4b, 0x09 },
373 { 0xc9, 0x60 }, { REG_COM16, 0x38 },
374 { 0x56, 0x40 },
375
376 { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO },
377 { 0xa4, 0x88 }, { 0x96, 0 },
378 { 0x97, 0x30 }, { 0x98, 0x20 },
379 { 0x99, 0x30 }, { 0x9a, 0x84 },
380 { 0x9b, 0x29 }, { 0x9c, 0x03 },
381 { 0x9d, 0x4c }, { 0x9e, 0x3f },
382 { 0x78, 0x04 },
383
384 /* Extra-weird stuff. Some sort of multiplexor register */
385 { 0x79, 0x01 }, { 0xc8, 0xf0 },
386 { 0x79, 0x0f }, { 0xc8, 0x00 },
387 { 0x79, 0x10 }, { 0xc8, 0x7e },
388 { 0x79, 0x0a }, { 0xc8, 0x80 },
389 { 0x79, 0x0b }, { 0xc8, 0x01 },
390 { 0x79, 0x0c }, { 0xc8, 0x0f },
391 { 0x79, 0x0d }, { 0xc8, 0x20 },
392 { 0x79, 0x09 }, { 0xc8, 0x80 },
393 { 0x79, 0x02 }, { 0xc8, 0xc0 },
394 { 0x79, 0x03 }, { 0xc8, 0x40 },
395 { 0x79, 0x05 }, { 0xc8, 0x30 },
396 { 0x79, 0x26 },
397
398 { 0xff, 0xff }, /* END MARKER */
399 };
400
401
402 /*
403 * Here we'll try to encapsulate the changes for just the output
404 * video format.
405 *
406 * RGB656 and YUV422 come from OV; RGB444 is homebrewed.
407 *
408 * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why.
409 */
410
411
412 static struct regval_list ov7670_fmt_yuv422[] = {
413 { REG_COM7, 0x0 }, /* Selects YUV mode */
414 { REG_RGB444, 0 }, /* No RGB444 please */
415 { REG_COM1, 0 }, /* CCIR601 */
416 { REG_COM15, COM15_R00FF },
417 { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */
418 { 0x4f, 0x80 }, /* "matrix coefficient 1" */
419 { 0x50, 0x80 }, /* "matrix coefficient 2" */
420 { 0x51, 0 }, /* vb */
421 { 0x52, 0x22 }, /* "matrix coefficient 4" */
422 { 0x53, 0x5e }, /* "matrix coefficient 5" */
423 { 0x54, 0x80 }, /* "matrix coefficient 6" */
424 { REG_COM13, COM13_GAMMA|COM13_UVSAT },
425 { 0xff, 0xff },
426 };
427
428 static struct regval_list ov7670_fmt_rgb565[] = {
429 { REG_COM7, COM7_RGB }, /* Selects RGB mode */
430 { REG_RGB444, 0 }, /* No RGB444 please */
431 { REG_COM1, 0x0 }, /* CCIR601 */
432 { REG_COM15, COM15_RGB565 },
433 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
434 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
435 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
436 { 0x51, 0 }, /* vb */
437 { 0x52, 0x3d }, /* "matrix coefficient 4" */
438 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
439 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
440 { REG_COM13, COM13_GAMMA|COM13_UVSAT },
441 { 0xff, 0xff },
442 };
443
444 static struct regval_list ov7670_fmt_rgb444[] = {
445 { REG_COM7, COM7_RGB }, /* Selects RGB mode */
446 { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */
447 { REG_COM1, 0x0 }, /* CCIR601 */
448 { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */
449 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
450 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
451 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
452 { 0x51, 0 }, /* vb */
453 { 0x52, 0x3d }, /* "matrix coefficient 4" */
454 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
455 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
456 { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */
457 { 0xff, 0xff },
458 };
459
460 static struct regval_list ov7670_fmt_raw[] = {
461 { REG_COM7, COM7_BAYER },
462 { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */
463 { REG_COM16, 0x3d }, /* Edge enhancement, denoise */
464 { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */
465 { 0xff, 0xff },
466 };
467
468
469
470 /*
471 * Low-level register I/O.
472 *
473 * Note that there are two versions of these. On the XO 1, the
474 * i2c controller only does SMBUS, so that's what we use. The
475 * ov7670 is not really an SMBUS device, though, so the communication
476 * is not always entirely reliable.
477 */
478 static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg,
479 unsigned char *value)
480 {
481 struct i2c_client *client = v4l2_get_subdevdata(sd);
482 int ret;
483
484 ret = i2c_smbus_read_byte_data(client, reg);
485 if (ret >= 0) {
486 *value = (unsigned char)ret;
487 ret = 0;
488 }
489 return ret;
490 }
491
492
493 static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg,
494 unsigned char value)
495 {
496 struct i2c_client *client = v4l2_get_subdevdata(sd);
497 int ret = i2c_smbus_write_byte_data(client, reg, value);
498
499 if (reg == REG_COM7 && (value & COM7_RESET))
500 msleep(5); /* Wait for reset to run */
501 return ret;
502 }
503
504 /*
505 * On most platforms, we'd rather do straight i2c I/O.
506 */
507 static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg,
508 unsigned char *value)
509 {
510 struct i2c_client *client = v4l2_get_subdevdata(sd);
511 u8 data = reg;
512 struct i2c_msg msg;
513 int ret;
514
515 /*
516 * Send out the register address...
517 */
518 msg.addr = client->addr;
519 msg.flags = 0;
520 msg.len = 1;
521 msg.buf = &data;
522 ret = i2c_transfer(client->adapter, &msg, 1);
523 if (ret < 0) {
524 printk(KERN_ERR "Error %d on register write\n", ret);
525 return ret;
526 }
527 /*
528 * ...then read back the result.
529 */
530 msg.flags = I2C_M_RD;
531 ret = i2c_transfer(client->adapter, &msg, 1);
532 if (ret >= 0) {
533 *value = data;
534 ret = 0;
535 }
536 return ret;
537 }
538
539
540 static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg,
541 unsigned char value)
542 {
543 struct i2c_client *client = v4l2_get_subdevdata(sd);
544 struct i2c_msg msg;
545 unsigned char data[2] = { reg, value };
546 int ret;
547
548 msg.addr = client->addr;
549 msg.flags = 0;
550 msg.len = 2;
551 msg.buf = data;
552 ret = i2c_transfer(client->adapter, &msg, 1);
553 if (ret > 0)
554 ret = 0;
555 if (reg == REG_COM7 && (value & COM7_RESET))
556 msleep(5); /* Wait for reset to run */
557 return ret;
558 }
559
560 static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg,
561 unsigned char *value)
562 {
563 struct ov7670_info *info = to_state(sd);
564 if (info->use_smbus)
565 return ov7670_read_smbus(sd, reg, value);
566 else
567 return ov7670_read_i2c(sd, reg, value);
568 }
569
570 static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg,
571 unsigned char value)
572 {
573 struct ov7670_info *info = to_state(sd);
574 if (info->use_smbus)
575 return ov7670_write_smbus(sd, reg, value);
576 else
577 return ov7670_write_i2c(sd, reg, value);
578 }
579
580 static int ov7670_update_bits(struct v4l2_subdev *sd, unsigned char reg,
581 unsigned char mask, unsigned char value)
582 {
583 unsigned char orig;
584 int ret;
585
586 ret = ov7670_read(sd, reg, &orig);
587 if (ret)
588 return ret;
589
590 return ov7670_write(sd, reg, (orig & ~mask) | (value & mask));
591 }
592
593 /*
594 * Write a list of register settings; ff/ff stops the process.
595 */
596 static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
597 {
598 while (vals->reg_num != 0xff || vals->value != 0xff) {
599 int ret = ov7670_write(sd, vals->reg_num, vals->value);
600 if (ret < 0)
601 return ret;
602 vals++;
603 }
604 return 0;
605 }
606
607
608 /*
609 * Stuff that knows about the sensor.
610 */
611 static int ov7670_reset(struct v4l2_subdev *sd, u32 val)
612 {
613 ov7670_write(sd, REG_COM7, COM7_RESET);
614 msleep(1);
615 return 0;
616 }
617
618
619 static int ov7670_init(struct v4l2_subdev *sd, u32 val)
620 {
621 return ov7670_write_array(sd, ov7670_default_regs);
622 }
623
624 static int ov7670_detect(struct v4l2_subdev *sd)
625 {
626 unsigned char v;
627 int ret;
628
629 ret = ov7670_init(sd, 0);
630 if (ret < 0)
631 return ret;
632 ret = ov7670_read(sd, REG_MIDH, &v);
633 if (ret < 0)
634 return ret;
635 if (v != 0x7f) /* OV manuf. id. */
636 return -ENODEV;
637 ret = ov7670_read(sd, REG_MIDL, &v);
638 if (ret < 0)
639 return ret;
640 if (v != 0xa2)
641 return -ENODEV;
642 /*
643 * OK, we know we have an OmniVision chip...but which one?
644 */
645 ret = ov7670_read(sd, REG_PID, &v);
646 if (ret < 0)
647 return ret;
648 if (v != 0x76) /* PID + VER = 0x76 / 0x73 */
649 return -ENODEV;
650 ret = ov7670_read(sd, REG_VER, &v);
651 if (ret < 0)
652 return ret;
653 if (v != 0x73) /* PID + VER = 0x76 / 0x73 */
654 return -ENODEV;
655 return 0;
656 }
657
658
659 /*
660 * Store information about the video data format. The color matrix
661 * is deeply tied into the format, so keep the relevant values here.
662 * The magic matrix numbers come from OmniVision.
663 */
664 static struct ov7670_format_struct {
665 u32 mbus_code;
666 enum v4l2_colorspace colorspace;
667 struct regval_list *regs;
668 int cmatrix[CMATRIX_LEN];
669 } ov7670_formats[] = {
670 {
671 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
672 .colorspace = V4L2_COLORSPACE_SRGB,
673 .regs = ov7670_fmt_yuv422,
674 .cmatrix = { 128, -128, 0, -34, -94, 128 },
675 },
676 {
677 .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,
678 .colorspace = V4L2_COLORSPACE_SRGB,
679 .regs = ov7670_fmt_rgb444,
680 .cmatrix = { 179, -179, 0, -61, -176, 228 },
681 },
682 {
683 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
684 .colorspace = V4L2_COLORSPACE_SRGB,
685 .regs = ov7670_fmt_rgb565,
686 .cmatrix = { 179, -179, 0, -61, -176, 228 },
687 },
688 {
689 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
690 .colorspace = V4L2_COLORSPACE_SRGB,
691 .regs = ov7670_fmt_raw,
692 .cmatrix = { 0, 0, 0, 0, 0, 0 },
693 },
694 };
695 #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats)
696
697
698 /*
699 * Then there is the issue of window sizes. Try to capture the info here.
700 */
701
702 /*
703 * QCIF mode is done (by OV) in a very strange way - it actually looks like
704 * VGA with weird scaling options - they do *not* use the canned QCIF mode
705 * which is allegedly provided by the sensor. So here's the weird register
706 * settings.
707 */
708 static struct regval_list ov7670_qcif_regs[] = {
709 { REG_COM3, COM3_SCALEEN|COM3_DCWEN },
710 { REG_COM3, COM3_DCWEN },
711 { REG_COM14, COM14_DCWEN | 0x01},
712 { 0x73, 0xf1 },
713 { 0xa2, 0x52 },
714 { 0x7b, 0x1c },
715 { 0x7c, 0x28 },
716 { 0x7d, 0x3c },
717 { 0x7f, 0x69 },
718 { REG_COM9, 0x38 },
719 { 0xa1, 0x0b },
720 { 0x74, 0x19 },
721 { 0x9a, 0x80 },
722 { 0x43, 0x14 },
723 { REG_COM13, 0xc0 },
724 { 0xff, 0xff },
725 };
726
727 static struct ov7670_win_size ov7670_win_sizes[] = {
728 /* VGA */
729 {
730 .width = VGA_WIDTH,
731 .height = VGA_HEIGHT,
732 .com7_bit = COM7_FMT_VGA,
733 .hstart = 158, /* These values from */
734 .hstop = 14, /* Omnivision */
735 .vstart = 10,
736 .vstop = 490,
737 .regs = NULL,
738 },
739 /* CIF */
740 {
741 .width = CIF_WIDTH,
742 .height = CIF_HEIGHT,
743 .com7_bit = COM7_FMT_CIF,
744 .hstart = 170, /* Empirically determined */
745 .hstop = 90,
746 .vstart = 14,
747 .vstop = 494,
748 .regs = NULL,
749 },
750 /* QVGA */
751 {
752 .width = QVGA_WIDTH,
753 .height = QVGA_HEIGHT,
754 .com7_bit = COM7_FMT_QVGA,
755 .hstart = 168, /* Empirically determined */
756 .hstop = 24,
757 .vstart = 12,
758 .vstop = 492,
759 .regs = NULL,
760 },
761 /* QCIF */
762 {
763 .width = QCIF_WIDTH,
764 .height = QCIF_HEIGHT,
765 .com7_bit = COM7_FMT_VGA, /* see comment above */
766 .hstart = 456, /* Empirically determined */
767 .hstop = 24,
768 .vstart = 14,
769 .vstop = 494,
770 .regs = ov7670_qcif_regs,
771 }
772 };
773
774 static struct ov7670_win_size ov7675_win_sizes[] = {
775 /*
776 * Currently, only VGA is supported. Theoretically it could be possible
777 * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a
778 * base and tweak them empirically could be required.
779 */
780 {
781 .width = VGA_WIDTH,
782 .height = VGA_HEIGHT,
783 .com7_bit = COM7_FMT_VGA,
784 .hstart = 158, /* These values from */
785 .hstop = 14, /* Omnivision */
786 .vstart = 14, /* Empirically determined */
787 .vstop = 494,
788 .regs = NULL,
789 }
790 };
791
792 static void ov7675_get_framerate(struct v4l2_subdev *sd,
793 struct v4l2_fract *tpf)
794 {
795 struct ov7670_info *info = to_state(sd);
796 u32 clkrc = info->clkrc;
797 int pll_factor;
798
799 if (info->pll_bypass)
800 pll_factor = 1;
801 else
802 pll_factor = PLL_FACTOR;
803
804 clkrc++;
805 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
806 clkrc = (clkrc >> 1);
807
808 tpf->numerator = 1;
809 tpf->denominator = (5 * pll_factor * info->clock_speed) /
810 (4 * clkrc);
811 }
812
813 static int ov7675_apply_framerate(struct v4l2_subdev *sd)
814 {
815 struct ov7670_info *info = to_state(sd);
816 int ret;
817
818 ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
819 if (ret < 0)
820 return ret;
821
822 return ov7670_write(sd, REG_DBLV,
823 info->pll_bypass ? DBLV_BYPASS : DBLV_X4);
824 }
825
826 static int ov7675_set_framerate(struct v4l2_subdev *sd,
827 struct v4l2_fract *tpf)
828 {
829 struct ov7670_info *info = to_state(sd);
830 u32 clkrc;
831 int pll_factor;
832
833 /*
834 * The formula is fps = 5/4*pixclk for YUV/RGB and
835 * fps = 5/2*pixclk for RAW.
836 *
837 * pixclk = clock_speed / (clkrc + 1) * PLLfactor
838 *
839 */
840 if (tpf->numerator == 0 || tpf->denominator == 0) {
841 clkrc = 0;
842 } else {
843 pll_factor = info->pll_bypass ? 1 : PLL_FACTOR;
844 clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) /
845 (4 * tpf->denominator);
846 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
847 clkrc = (clkrc << 1);
848 clkrc--;
849 }
850
851 /*
852 * The datasheet claims that clkrc = 0 will divide the input clock by 1
853 * but we've checked with an oscilloscope that it divides by 2 instead.
854 * So, if clkrc = 0 just bypass the divider.
855 */
856 if (clkrc <= 0)
857 clkrc = CLK_EXT;
858 else if (clkrc > CLK_SCALE)
859 clkrc = CLK_SCALE;
860 info->clkrc = clkrc;
861
862 /* Recalculate frame rate */
863 ov7675_get_framerate(sd, tpf);
864
865 /*
866 * If the device is not powered up by the host driver do
867 * not apply any changes to H/W at this time. Instead
868 * the framerate will be restored right after power-up.
869 */
870 if (info->on)
871 return ov7675_apply_framerate(sd);
872
873 return 0;
874 }
875
876 static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd,
877 struct v4l2_fract *tpf)
878 {
879 struct ov7670_info *info = to_state(sd);
880
881 tpf->numerator = 1;
882 tpf->denominator = info->clock_speed;
883 if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1)
884 tpf->denominator /= (info->clkrc & CLK_SCALE);
885 }
886
887 static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd,
888 struct v4l2_fract *tpf)
889 {
890 struct ov7670_info *info = to_state(sd);
891 int div;
892
893 if (tpf->numerator == 0 || tpf->denominator == 0)
894 div = 1; /* Reset to full rate */
895 else
896 div = (tpf->numerator * info->clock_speed) / tpf->denominator;
897 if (div == 0)
898 div = 1;
899 else if (div > CLK_SCALE)
900 div = CLK_SCALE;
901 info->clkrc = (info->clkrc & 0x80) | div;
902 tpf->numerator = 1;
903 tpf->denominator = info->clock_speed / div;
904
905 /*
906 * If the device is not powered up by the host driver do
907 * not apply any changes to H/W at this time. Instead
908 * the framerate will be restored right after power-up.
909 */
910 if (info->on)
911 return ov7670_write(sd, REG_CLKRC, info->clkrc);
912
913 return 0;
914 }
915
916 /*
917 * Store a set of start/stop values into the camera.
918 */
919 static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop,
920 int vstart, int vstop)
921 {
922 int ret;
923 unsigned char v;
924 /*
925 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of
926 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is
927 * a mystery "edge offset" value in the top two bits of href.
928 */
929 ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff);
930 ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff);
931 ret += ov7670_read(sd, REG_HREF, &v);
932 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7);
933 msleep(10);
934 ret += ov7670_write(sd, REG_HREF, v);
935 /*
936 * Vertical: similar arrangement, but only 10 bits.
937 */
938 ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff);
939 ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff);
940 ret += ov7670_read(sd, REG_VREF, &v);
941 v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3);
942 msleep(10);
943 ret += ov7670_write(sd, REG_VREF, v);
944 return ret;
945 }
946
947
948 static int ov7670_enum_mbus_code(struct v4l2_subdev *sd,
949 struct v4l2_subdev_pad_config *cfg,
950 struct v4l2_subdev_mbus_code_enum *code)
951 {
952 if (code->pad || code->index >= N_OV7670_FMTS)
953 return -EINVAL;
954
955 code->code = ov7670_formats[code->index].mbus_code;
956 return 0;
957 }
958
959 static int ov7670_try_fmt_internal(struct v4l2_subdev *sd,
960 struct v4l2_mbus_framefmt *fmt,
961 struct ov7670_format_struct **ret_fmt,
962 struct ov7670_win_size **ret_wsize)
963 {
964 int index, i;
965 struct ov7670_win_size *wsize;
966 struct ov7670_info *info = to_state(sd);
967 unsigned int n_win_sizes = info->devtype->n_win_sizes;
968 unsigned int win_sizes_limit = n_win_sizes;
969
970 for (index = 0; index < N_OV7670_FMTS; index++)
971 if (ov7670_formats[index].mbus_code == fmt->code)
972 break;
973 if (index >= N_OV7670_FMTS) {
974 /* default to first format */
975 index = 0;
976 fmt->code = ov7670_formats[0].mbus_code;
977 }
978 if (ret_fmt != NULL)
979 *ret_fmt = ov7670_formats + index;
980 /*
981 * Fields: the OV devices claim to be progressive.
982 */
983 fmt->field = V4L2_FIELD_NONE;
984
985 /*
986 * Don't consider values that don't match min_height and min_width
987 * constraints.
988 */
989 if (info->min_width || info->min_height)
990 for (i = 0; i < n_win_sizes; i++) {
991 wsize = info->devtype->win_sizes + i;
992
993 if (wsize->width < info->min_width ||
994 wsize->height < info->min_height) {
995 win_sizes_limit = i;
996 break;
997 }
998 }
999 /*
1000 * Round requested image size down to the nearest
1001 * we support, but not below the smallest.
1002 */
1003 for (wsize = info->devtype->win_sizes;
1004 wsize < info->devtype->win_sizes + win_sizes_limit; wsize++)
1005 if (fmt->width >= wsize->width && fmt->height >= wsize->height)
1006 break;
1007 if (wsize >= info->devtype->win_sizes + win_sizes_limit)
1008 wsize--; /* Take the smallest one */
1009 if (ret_wsize != NULL)
1010 *ret_wsize = wsize;
1011 /*
1012 * Note the size we'll actually handle.
1013 */
1014 fmt->width = wsize->width;
1015 fmt->height = wsize->height;
1016 fmt->colorspace = ov7670_formats[index].colorspace;
1017
1018 info->format = *fmt;
1019
1020 return 0;
1021 }
1022
1023 static int ov7670_apply_fmt(struct v4l2_subdev *sd)
1024 {
1025 struct ov7670_info *info = to_state(sd);
1026 struct ov7670_win_size *wsize = info->wsize;
1027 unsigned char com7, com10 = 0;
1028 int ret;
1029
1030 /*
1031 * COM7 is a pain in the ass, it doesn't like to be read then
1032 * quickly written afterward. But we have everything we need
1033 * to set it absolutely here, as long as the format-specific
1034 * register sets list it first.
1035 */
1036 com7 = info->fmt->regs[0].value;
1037 com7 |= wsize->com7_bit;
1038 ret = ov7670_write(sd, REG_COM7, com7);
1039 if (ret)
1040 return ret;
1041
1042 /*
1043 * Configure the media bus through COM10 register
1044 */
1045 if (info->mbus_config & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1046 com10 |= COM10_VS_NEG;
1047 if (info->mbus_config & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1048 com10 |= COM10_HREF_REV;
1049 if (info->pclk_hb_disable)
1050 com10 |= COM10_PCLK_HB;
1051 ret = ov7670_write(sd, REG_COM10, com10);
1052 if (ret)
1053 return ret;
1054
1055 /*
1056 * Now write the rest of the array. Also store start/stops
1057 */
1058 ret = ov7670_write_array(sd, info->fmt->regs + 1);
1059 if (ret)
1060 return ret;
1061
1062 ret = ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart,
1063 wsize->vstop);
1064 if (ret)
1065 return ret;
1066
1067 if (wsize->regs) {
1068 ret = ov7670_write_array(sd, wsize->regs);
1069 if (ret)
1070 return ret;
1071 }
1072
1073 /*
1074 * If we're running RGB565, we must rewrite clkrc after setting
1075 * the other parameters or the image looks poor. If we're *not*
1076 * doing RGB565, we must not rewrite clkrc or the image looks
1077 * *really* poor.
1078 *
1079 * (Update) Now that we retain clkrc state, we should be able
1080 * to write it unconditionally, and that will make the frame
1081 * rate persistent too.
1082 */
1083 ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
1084 if (ret)
1085 return ret;
1086
1087 return 0;
1088 }
1089
1090 /*
1091 * Set a format.
1092 */
1093 static int ov7670_set_fmt(struct v4l2_subdev *sd,
1094 struct v4l2_subdev_pad_config *cfg,
1095 struct v4l2_subdev_format *format)
1096 {
1097 struct ov7670_info *info = to_state(sd);
1098 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1099 struct v4l2_mbus_framefmt *mbus_fmt;
1100 #endif
1101 int ret;
1102
1103 if (format->pad)
1104 return -EINVAL;
1105
1106 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1107 ret = ov7670_try_fmt_internal(sd, &format->format, NULL, NULL);
1108 if (ret)
1109 return ret;
1110 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1111 mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1112 *mbus_fmt = format->format;
1113 #endif
1114 return 0;
1115 }
1116
1117 ret = ov7670_try_fmt_internal(sd, &format->format, &info->fmt, &info->wsize);
1118 if (ret)
1119 return ret;
1120
1121 /*
1122 * If the device is not powered up by the host driver do
1123 * not apply any changes to H/W at this time. Instead
1124 * the frame format will be restored right after power-up.
1125 */
1126 if (info->on)
1127 return ov7670_apply_fmt(sd);
1128
1129 return 0;
1130 }
1131
1132 static int ov7670_get_fmt(struct v4l2_subdev *sd,
1133 struct v4l2_subdev_pad_config *cfg,
1134 struct v4l2_subdev_format *format)
1135 {
1136 struct ov7670_info *info = to_state(sd);
1137 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1138 struct v4l2_mbus_framefmt *mbus_fmt;
1139 #endif
1140
1141 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1142 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1143 mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, 0);
1144 format->format = *mbus_fmt;
1145 return 0;
1146 #else
1147 return -EINVAL;
1148 #endif
1149 } else {
1150 format->format = info->format;
1151 }
1152
1153 return 0;
1154 }
1155
1156 /*
1157 * Implement G/S_PARM. There is a "high quality" mode we could try
1158 * to do someday; for now, we just do the frame rate tweak.
1159 */
1160 static int ov7670_g_frame_interval(struct v4l2_subdev *sd,
1161 struct v4l2_subdev_frame_interval *ival)
1162 {
1163 struct ov7670_info *info = to_state(sd);
1164
1165
1166 info->devtype->get_framerate(sd, &ival->interval);
1167
1168 return 0;
1169 }
1170
1171 static int ov7670_s_frame_interval(struct v4l2_subdev *sd,
1172 struct v4l2_subdev_frame_interval *ival)
1173 {
1174 struct v4l2_fract *tpf = &ival->interval;
1175 struct ov7670_info *info = to_state(sd);
1176
1177
1178 return info->devtype->set_framerate(sd, tpf);
1179 }
1180
1181
1182 /*
1183 * Frame intervals. Since frame rates are controlled with the clock
1184 * divider, we can only do 30/n for integer n values. So no continuous
1185 * or stepwise options. Here we just pick a handful of logical values.
1186 */
1187
1188 static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 };
1189
1190 static int ov7670_enum_frame_interval(struct v4l2_subdev *sd,
1191 struct v4l2_subdev_pad_config *cfg,
1192 struct v4l2_subdev_frame_interval_enum *fie)
1193 {
1194 struct ov7670_info *info = to_state(sd);
1195 unsigned int n_win_sizes = info->devtype->n_win_sizes;
1196 int i;
1197
1198 if (fie->pad)
1199 return -EINVAL;
1200 if (fie->index >= ARRAY_SIZE(ov7670_frame_rates))
1201 return -EINVAL;
1202
1203 /*
1204 * Check if the width/height is valid.
1205 *
1206 * If a minimum width/height was requested, filter out the capture
1207 * windows that fall outside that.
1208 */
1209 for (i = 0; i < n_win_sizes; i++) {
1210 struct ov7670_win_size *win = &info->devtype->win_sizes[i];
1211
1212 if (info->min_width && win->width < info->min_width)
1213 continue;
1214 if (info->min_height && win->height < info->min_height)
1215 continue;
1216 if (fie->width == win->width && fie->height == win->height)
1217 break;
1218 }
1219 if (i == n_win_sizes)
1220 return -EINVAL;
1221 fie->interval.numerator = 1;
1222 fie->interval.denominator = ov7670_frame_rates[fie->index];
1223 return 0;
1224 }
1225
1226 /*
1227 * Frame size enumeration
1228 */
1229 static int ov7670_enum_frame_size(struct v4l2_subdev *sd,
1230 struct v4l2_subdev_pad_config *cfg,
1231 struct v4l2_subdev_frame_size_enum *fse)
1232 {
1233 struct ov7670_info *info = to_state(sd);
1234 int i;
1235 int num_valid = -1;
1236 __u32 index = fse->index;
1237 unsigned int n_win_sizes = info->devtype->n_win_sizes;
1238
1239 if (fse->pad)
1240 return -EINVAL;
1241
1242 /*
1243 * If a minimum width/height was requested, filter out the capture
1244 * windows that fall outside that.
1245 */
1246 for (i = 0; i < n_win_sizes; i++) {
1247 struct ov7670_win_size *win = &info->devtype->win_sizes[i];
1248 if (info->min_width && win->width < info->min_width)
1249 continue;
1250 if (info->min_height && win->height < info->min_height)
1251 continue;
1252 if (index == ++num_valid) {
1253 fse->min_width = fse->max_width = win->width;
1254 fse->min_height = fse->max_height = win->height;
1255 return 0;
1256 }
1257 }
1258
1259 return -EINVAL;
1260 }
1261
1262 /*
1263 * Code for dealing with controls.
1264 */
1265
1266 static int ov7670_store_cmatrix(struct v4l2_subdev *sd,
1267 int matrix[CMATRIX_LEN])
1268 {
1269 int i, ret;
1270 unsigned char signbits = 0;
1271
1272 /*
1273 * Weird crap seems to exist in the upper part of
1274 * the sign bits register, so let's preserve it.
1275 */
1276 ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits);
1277 signbits &= 0xc0;
1278
1279 for (i = 0; i < CMATRIX_LEN; i++) {
1280 unsigned char raw;
1281
1282 if (matrix[i] < 0) {
1283 signbits |= (1 << i);
1284 if (matrix[i] < -255)
1285 raw = 0xff;
1286 else
1287 raw = (-1 * matrix[i]) & 0xff;
1288 }
1289 else {
1290 if (matrix[i] > 255)
1291 raw = 0xff;
1292 else
1293 raw = matrix[i] & 0xff;
1294 }
1295 ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw);
1296 }
1297 ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits);
1298 return ret;
1299 }
1300
1301
1302 /*
1303 * Hue also requires messing with the color matrix. It also requires
1304 * trig functions, which tend not to be well supported in the kernel.
1305 * So here is a simple table of sine values, 0-90 degrees, in steps
1306 * of five degrees. Values are multiplied by 1000.
1307 *
1308 * The following naive approximate trig functions require an argument
1309 * carefully limited to -180 <= theta <= 180.
1310 */
1311 #define SIN_STEP 5
1312 static const int ov7670_sin_table[] = {
1313 0, 87, 173, 258, 342, 422,
1314 499, 573, 642, 707, 766, 819,
1315 866, 906, 939, 965, 984, 996,
1316 1000
1317 };
1318
1319 static int ov7670_sine(int theta)
1320 {
1321 int chs = 1;
1322 int sine;
1323
1324 if (theta < 0) {
1325 theta = -theta;
1326 chs = -1;
1327 }
1328 if (theta <= 90)
1329 sine = ov7670_sin_table[theta/SIN_STEP];
1330 else {
1331 theta -= 90;
1332 sine = 1000 - ov7670_sin_table[theta/SIN_STEP];
1333 }
1334 return sine*chs;
1335 }
1336
1337 static int ov7670_cosine(int theta)
1338 {
1339 theta = 90 - theta;
1340 if (theta > 180)
1341 theta -= 360;
1342 else if (theta < -180)
1343 theta += 360;
1344 return ov7670_sine(theta);
1345 }
1346
1347
1348
1349
1350 static void ov7670_calc_cmatrix(struct ov7670_info *info,
1351 int matrix[CMATRIX_LEN], int sat, int hue)
1352 {
1353 int i;
1354 /*
1355 * Apply the current saturation setting first.
1356 */
1357 for (i = 0; i < CMATRIX_LEN; i++)
1358 matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7;
1359 /*
1360 * Then, if need be, rotate the hue value.
1361 */
1362 if (hue != 0) {
1363 int sinth, costh, tmpmatrix[CMATRIX_LEN];
1364
1365 memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int));
1366 sinth = ov7670_sine(hue);
1367 costh = ov7670_cosine(hue);
1368
1369 matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000;
1370 matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000;
1371 matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000;
1372 matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000;
1373 matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000;
1374 matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000;
1375 }
1376 }
1377
1378
1379
1380 static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue)
1381 {
1382 struct ov7670_info *info = to_state(sd);
1383 int matrix[CMATRIX_LEN];
1384 int ret;
1385
1386 ov7670_calc_cmatrix(info, matrix, sat, hue);
1387 ret = ov7670_store_cmatrix(sd, matrix);
1388 return ret;
1389 }
1390
1391
1392 /*
1393 * Some weird registers seem to store values in a sign/magnitude format!
1394 */
1395
1396 static unsigned char ov7670_abs_to_sm(unsigned char v)
1397 {
1398 if (v > 127)
1399 return v & 0x7f;
1400 return (128 - v) | 0x80;
1401 }
1402
1403 static int ov7670_s_brightness(struct v4l2_subdev *sd, int value)
1404 {
1405 unsigned char com8 = 0, v;
1406 int ret;
1407
1408 ov7670_read(sd, REG_COM8, &com8);
1409 com8 &= ~COM8_AEC;
1410 ov7670_write(sd, REG_COM8, com8);
1411 v = ov7670_abs_to_sm(value);
1412 ret = ov7670_write(sd, REG_BRIGHT, v);
1413 return ret;
1414 }
1415
1416 static int ov7670_s_contrast(struct v4l2_subdev *sd, int value)
1417 {
1418 return ov7670_write(sd, REG_CONTRAS, (unsigned char) value);
1419 }
1420
1421 static int ov7670_s_hflip(struct v4l2_subdev *sd, int value)
1422 {
1423 unsigned char v = 0;
1424 int ret;
1425
1426 ret = ov7670_read(sd, REG_MVFP, &v);
1427 if (value)
1428 v |= MVFP_MIRROR;
1429 else
1430 v &= ~MVFP_MIRROR;
1431 msleep(10); /* FIXME */
1432 ret += ov7670_write(sd, REG_MVFP, v);
1433 return ret;
1434 }
1435
1436 static int ov7670_s_vflip(struct v4l2_subdev *sd, int value)
1437 {
1438 unsigned char v = 0;
1439 int ret;
1440
1441 ret = ov7670_read(sd, REG_MVFP, &v);
1442 if (value)
1443 v |= MVFP_FLIP;
1444 else
1445 v &= ~MVFP_FLIP;
1446 msleep(10); /* FIXME */
1447 ret += ov7670_write(sd, REG_MVFP, v);
1448 return ret;
1449 }
1450
1451 /*
1452 * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes
1453 * the data sheet, the VREF parts should be the most significant, but
1454 * experience shows otherwise. There seems to be little value in
1455 * messing with the VREF bits, so we leave them alone.
1456 */
1457 static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value)
1458 {
1459 int ret;
1460 unsigned char gain;
1461
1462 ret = ov7670_read(sd, REG_GAIN, &gain);
1463 *value = gain;
1464 return ret;
1465 }
1466
1467 static int ov7670_s_gain(struct v4l2_subdev *sd, int value)
1468 {
1469 int ret;
1470 unsigned char com8;
1471
1472 ret = ov7670_write(sd, REG_GAIN, value & 0xff);
1473 /* Have to turn off AGC as well */
1474 if (ret == 0) {
1475 ret = ov7670_read(sd, REG_COM8, &com8);
1476 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC);
1477 }
1478 return ret;
1479 }
1480
1481 /*
1482 * Tweak autogain.
1483 */
1484 static int ov7670_s_autogain(struct v4l2_subdev *sd, int value)
1485 {
1486 int ret;
1487 unsigned char com8;
1488
1489 ret = ov7670_read(sd, REG_COM8, &com8);
1490 if (ret == 0) {
1491 if (value)
1492 com8 |= COM8_AGC;
1493 else
1494 com8 &= ~COM8_AGC;
1495 ret = ov7670_write(sd, REG_COM8, com8);
1496 }
1497 return ret;
1498 }
1499
1500 static int ov7670_s_exp(struct v4l2_subdev *sd, int value)
1501 {
1502 int ret;
1503 unsigned char com1, com8, aech, aechh;
1504
1505 ret = ov7670_read(sd, REG_COM1, &com1) +
1506 ov7670_read(sd, REG_COM8, &com8) +
1507 ov7670_read(sd, REG_AECHH, &aechh);
1508 if (ret)
1509 return ret;
1510
1511 com1 = (com1 & 0xfc) | (value & 0x03);
1512 aech = (value >> 2) & 0xff;
1513 aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f);
1514 ret = ov7670_write(sd, REG_COM1, com1) +
1515 ov7670_write(sd, REG_AECH, aech) +
1516 ov7670_write(sd, REG_AECHH, aechh);
1517 /* Have to turn off AEC as well */
1518 if (ret == 0)
1519 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC);
1520 return ret;
1521 }
1522
1523 /*
1524 * Tweak autoexposure.
1525 */
1526 static int ov7670_s_autoexp(struct v4l2_subdev *sd,
1527 enum v4l2_exposure_auto_type value)
1528 {
1529 int ret;
1530 unsigned char com8;
1531
1532 ret = ov7670_read(sd, REG_COM8, &com8);
1533 if (ret == 0) {
1534 if (value == V4L2_EXPOSURE_AUTO)
1535 com8 |= COM8_AEC;
1536 else
1537 com8 &= ~COM8_AEC;
1538 ret = ov7670_write(sd, REG_COM8, com8);
1539 }
1540 return ret;
1541 }
1542
1543 static const char * const ov7670_test_pattern_menu[] = {
1544 "No test output",
1545 "Shifting \"1\"",
1546 "8-bar color bar",
1547 "Fade to gray color bar",
1548 };
1549
1550 static int ov7670_s_test_pattern(struct v4l2_subdev *sd, int value)
1551 {
1552 int ret;
1553
1554 ret = ov7670_update_bits(sd, REG_SCALING_XSC, TEST_PATTTERN_0,
1555 value & BIT(0) ? TEST_PATTTERN_0 : 0);
1556 if (ret)
1557 return ret;
1558
1559 return ov7670_update_bits(sd, REG_SCALING_YSC, TEST_PATTTERN_1,
1560 value & BIT(1) ? TEST_PATTTERN_1 : 0);
1561 }
1562
1563 static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1564 {
1565 struct v4l2_subdev *sd = to_sd(ctrl);
1566 struct ov7670_info *info = to_state(sd);
1567
1568 switch (ctrl->id) {
1569 case V4L2_CID_AUTOGAIN:
1570 return ov7670_g_gain(sd, &info->gain->val);
1571 }
1572 return -EINVAL;
1573 }
1574
1575 static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl)
1576 {
1577 struct v4l2_subdev *sd = to_sd(ctrl);
1578 struct ov7670_info *info = to_state(sd);
1579
1580 switch (ctrl->id) {
1581 case V4L2_CID_BRIGHTNESS:
1582 return ov7670_s_brightness(sd, ctrl->val);
1583 case V4L2_CID_CONTRAST:
1584 return ov7670_s_contrast(sd, ctrl->val);
1585 case V4L2_CID_SATURATION:
1586 return ov7670_s_sat_hue(sd,
1587 info->saturation->val, info->hue->val);
1588 case V4L2_CID_VFLIP:
1589 return ov7670_s_vflip(sd, ctrl->val);
1590 case V4L2_CID_HFLIP:
1591 return ov7670_s_hflip(sd, ctrl->val);
1592 case V4L2_CID_AUTOGAIN:
1593 /* Only set manual gain if auto gain is not explicitly
1594 turned on. */
1595 if (!ctrl->val) {
1596 /* ov7670_s_gain turns off auto gain */
1597 return ov7670_s_gain(sd, info->gain->val);
1598 }
1599 return ov7670_s_autogain(sd, ctrl->val);
1600 case V4L2_CID_EXPOSURE_AUTO:
1601 /* Only set manual exposure if auto exposure is not explicitly
1602 turned on. */
1603 if (ctrl->val == V4L2_EXPOSURE_MANUAL) {
1604 /* ov7670_s_exp turns off auto exposure */
1605 return ov7670_s_exp(sd, info->exposure->val);
1606 }
1607 return ov7670_s_autoexp(sd, ctrl->val);
1608 case V4L2_CID_TEST_PATTERN:
1609 return ov7670_s_test_pattern(sd, ctrl->val);
1610 }
1611 return -EINVAL;
1612 }
1613
1614 static const struct v4l2_ctrl_ops ov7670_ctrl_ops = {
1615 .s_ctrl = ov7670_s_ctrl,
1616 .g_volatile_ctrl = ov7670_g_volatile_ctrl,
1617 };
1618
1619 #ifdef CONFIG_VIDEO_ADV_DEBUG
1620 static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1621 {
1622 unsigned char val = 0;
1623 int ret;
1624
1625 ret = ov7670_read(sd, reg->reg & 0xff, &val);
1626 reg->val = val;
1627 reg->size = 1;
1628 return ret;
1629 }
1630
1631 static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
1632 {
1633 ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff);
1634 return 0;
1635 }
1636 #endif
1637
1638 static void ov7670_power_on(struct v4l2_subdev *sd)
1639 {
1640 struct ov7670_info *info = to_state(sd);
1641
1642 if (info->on)
1643 return;
1644
1645 clk_prepare_enable(info->clk);
1646
1647 if (info->pwdn_gpio)
1648 gpiod_set_value(info->pwdn_gpio, 0);
1649 if (info->resetb_gpio) {
1650 gpiod_set_value(info->resetb_gpio, 1);
1651 usleep_range(500, 1000);
1652 gpiod_set_value(info->resetb_gpio, 0);
1653 }
1654 if (info->pwdn_gpio || info->resetb_gpio || info->clk)
1655 usleep_range(3000, 5000);
1656
1657 info->on = true;
1658 }
1659
1660 static void ov7670_power_off(struct v4l2_subdev *sd)
1661 {
1662 struct ov7670_info *info = to_state(sd);
1663
1664 if (!info->on)
1665 return;
1666
1667 clk_disable_unprepare(info->clk);
1668
1669 if (info->pwdn_gpio)
1670 gpiod_set_value(info->pwdn_gpio, 1);
1671
1672 info->on = false;
1673 }
1674
1675 static int ov7670_s_power(struct v4l2_subdev *sd, int on)
1676 {
1677 struct ov7670_info *info = to_state(sd);
1678
1679 if (info->on == on)
1680 return 0;
1681
1682 if (on) {
1683 ov7670_power_on (sd);
1684 ov7670_init(sd, 0);
1685 ov7670_apply_fmt(sd);
1686 ov7675_apply_framerate(sd);
1687 v4l2_ctrl_handler_setup(&info->hdl);
1688 } else {
1689 ov7670_power_off (sd);
1690 }
1691
1692 return 0;
1693 }
1694
1695 static void ov7670_get_default_format(struct v4l2_subdev *sd,
1696 struct v4l2_mbus_framefmt *format)
1697 {
1698 struct ov7670_info *info = to_state(sd);
1699
1700 format->width = info->devtype->win_sizes[0].width;
1701 format->height = info->devtype->win_sizes[0].height;
1702 format->colorspace = info->fmt->colorspace;
1703 format->code = info->fmt->mbus_code;
1704 format->field = V4L2_FIELD_NONE;
1705 }
1706
1707 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1708 static int ov7670_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1709 {
1710 struct v4l2_mbus_framefmt *format =
1711 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1712
1713 ov7670_get_default_format(sd, format);
1714
1715 return 0;
1716 }
1717 #endif
1718
1719 /* ----------------------------------------------------------------------- */
1720
1721 static const struct v4l2_subdev_core_ops ov7670_core_ops = {
1722 .reset = ov7670_reset,
1723 .init = ov7670_init,
1724 .s_power = ov7670_s_power,
1725 .log_status = v4l2_ctrl_subdev_log_status,
1726 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1727 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1728 #ifdef CONFIG_VIDEO_ADV_DEBUG
1729 .g_register = ov7670_g_register,
1730 .s_register = ov7670_s_register,
1731 #endif
1732 };
1733
1734 static const struct v4l2_subdev_video_ops ov7670_video_ops = {
1735 .s_frame_interval = ov7670_s_frame_interval,
1736 .g_frame_interval = ov7670_g_frame_interval,
1737 };
1738
1739 static const struct v4l2_subdev_pad_ops ov7670_pad_ops = {
1740 .enum_frame_interval = ov7670_enum_frame_interval,
1741 .enum_frame_size = ov7670_enum_frame_size,
1742 .enum_mbus_code = ov7670_enum_mbus_code,
1743 .get_fmt = ov7670_get_fmt,
1744 .set_fmt = ov7670_set_fmt,
1745 };
1746
1747 static const struct v4l2_subdev_ops ov7670_ops = {
1748 .core = &ov7670_core_ops,
1749 .video = &ov7670_video_ops,
1750 .pad = &ov7670_pad_ops,
1751 };
1752
1753 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1754 static const struct v4l2_subdev_internal_ops ov7670_subdev_internal_ops = {
1755 .open = ov7670_open,
1756 };
1757 #endif
1758
1759 /* ----------------------------------------------------------------------- */
1760
1761 static const struct ov7670_devtype ov7670_devdata[] = {
1762 [MODEL_OV7670] = {
1763 .win_sizes = ov7670_win_sizes,
1764 .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes),
1765 .set_framerate = ov7670_set_framerate_legacy,
1766 .get_framerate = ov7670_get_framerate_legacy,
1767 },
1768 [MODEL_OV7675] = {
1769 .win_sizes = ov7675_win_sizes,
1770 .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes),
1771 .set_framerate = ov7675_set_framerate,
1772 .get_framerate = ov7675_get_framerate,
1773 },
1774 };
1775
1776 static int ov7670_init_gpio(struct i2c_client *client, struct ov7670_info *info)
1777 {
1778 info->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
1779 GPIOD_OUT_LOW);
1780 if (IS_ERR(info->pwdn_gpio)) {
1781 dev_info(&client->dev, "can't get %s GPIO\n", "powerdown");
1782 return PTR_ERR(info->pwdn_gpio);
1783 }
1784
1785 info->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1786 GPIOD_OUT_LOW);
1787 if (IS_ERR(info->resetb_gpio)) {
1788 dev_info(&client->dev, "can't get %s GPIO\n", "reset");
1789 return PTR_ERR(info->resetb_gpio);
1790 }
1791
1792 usleep_range(3000, 5000);
1793
1794 return 0;
1795 }
1796
1797 /*
1798 * ov7670_parse_dt() - Parse device tree to collect mbus configuration
1799 * properties
1800 */
1801 static int ov7670_parse_dt(struct device *dev,
1802 struct ov7670_info *info)
1803 {
1804 struct fwnode_handle *fwnode = dev_fwnode(dev);
1805 struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
1806 struct fwnode_handle *ep;
1807 int ret;
1808
1809 if (!fwnode)
1810 return -EINVAL;
1811
1812 info->pclk_hb_disable = false;
1813 if (fwnode_property_present(fwnode, "ov7670,pclk-hb-disable"))
1814 info->pclk_hb_disable = true;
1815
1816 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1817 if (!ep)
1818 return -EINVAL;
1819
1820 ret = v4l2_fwnode_endpoint_parse(ep, &bus_cfg);
1821 fwnode_handle_put(ep);
1822 if (ret)
1823 return ret;
1824
1825 if (bus_cfg.bus_type != V4L2_MBUS_PARALLEL) {
1826 dev_err(dev, "Unsupported media bus type\n");
1827 return ret;
1828 }
1829 info->mbus_config = bus_cfg.bus.parallel.flags;
1830
1831 return 0;
1832 }
1833
1834 static int ov7670_probe(struct i2c_client *client,
1835 const struct i2c_device_id *id)
1836 {
1837 struct v4l2_fract tpf;
1838 struct v4l2_subdev *sd;
1839 struct ov7670_info *info;
1840 int ret;
1841
1842 info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
1843 if (info == NULL)
1844 return -ENOMEM;
1845 sd = &info->sd;
1846 v4l2_i2c_subdev_init(sd, client, &ov7670_ops);
1847
1848 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1849 sd->internal_ops = &ov7670_subdev_internal_ops;
1850 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1851 #endif
1852
1853 info->clock_speed = 30; /* default: a guess */
1854
1855 if (dev_fwnode(&client->dev)) {
1856 ret = ov7670_parse_dt(&client->dev, info);
1857 if (ret)
1858 return ret;
1859
1860 } else if (client->dev.platform_data) {
1861 struct ov7670_config *config = client->dev.platform_data;
1862
1863 /*
1864 * Must apply configuration before initializing device, because it
1865 * selects I/O method.
1866 */
1867 info->min_width = config->min_width;
1868 info->min_height = config->min_height;
1869 info->use_smbus = config->use_smbus;
1870
1871 if (config->clock_speed)
1872 info->clock_speed = config->clock_speed;
1873
1874 if (config->pll_bypass)
1875 info->pll_bypass = true;
1876
1877 if (config->pclk_hb_disable)
1878 info->pclk_hb_disable = true;
1879 }
1880
1881 info->clk = devm_clk_get(&client->dev, "xclk"); /* optional */
1882 if (IS_ERR(info->clk)) {
1883 ret = PTR_ERR(info->clk);
1884 if (ret == -ENOENT)
1885 info->clk = NULL;
1886 else
1887 return ret;
1888 }
1889
1890 ret = ov7670_init_gpio(client, info);
1891 if (ret)
1892 return ret;
1893
1894 ov7670_power_on(sd);
1895
1896 if (info->clk) {
1897 info->clock_speed = clk_get_rate(info->clk) / 1000000;
1898 if (info->clock_speed < 10 || info->clock_speed > 48) {
1899 ret = -EINVAL;
1900 goto power_off;
1901 }
1902 }
1903
1904 /* Make sure it's an ov7670 */
1905 ret = ov7670_detect(sd);
1906 if (ret) {
1907 v4l_dbg(1, debug, client,
1908 "chip found @ 0x%x (%s) is not an ov7670 chip.\n",
1909 client->addr << 1, client->adapter->name);
1910 goto power_off;
1911 }
1912 v4l_info(client, "chip found @ 0x%02x (%s)\n",
1913 client->addr << 1, client->adapter->name);
1914
1915 info->devtype = &ov7670_devdata[id->driver_data];
1916 info->fmt = &ov7670_formats[0];
1917 info->wsize = &info->devtype->win_sizes[0];
1918
1919 ov7670_get_default_format(sd, &info->format);
1920
1921 info->clkrc = 0;
1922
1923 /* Set default frame rate to 30 fps */
1924 tpf.numerator = 1;
1925 tpf.denominator = 30;
1926 info->devtype->set_framerate(sd, &tpf);
1927
1928 v4l2_ctrl_handler_init(&info->hdl, 10);
1929 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1930 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1931 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1932 V4L2_CID_CONTRAST, 0, 127, 1, 64);
1933 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1934 V4L2_CID_VFLIP, 0, 1, 1, 0);
1935 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1936 V4L2_CID_HFLIP, 0, 1, 1, 0);
1937 info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1938 V4L2_CID_SATURATION, 0, 256, 1, 128);
1939 info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1940 V4L2_CID_HUE, -180, 180, 5, 0);
1941 info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1942 V4L2_CID_GAIN, 0, 255, 1, 128);
1943 info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1944 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1945 info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1946 V4L2_CID_EXPOSURE, 0, 65535, 1, 500);
1947 info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops,
1948 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
1949 V4L2_EXPOSURE_AUTO);
1950 v4l2_ctrl_new_std_menu_items(&info->hdl, &ov7670_ctrl_ops,
1951 V4L2_CID_TEST_PATTERN,
1952 ARRAY_SIZE(ov7670_test_pattern_menu) - 1, 0, 0,
1953 ov7670_test_pattern_menu);
1954 sd->ctrl_handler = &info->hdl;
1955 if (info->hdl.error) {
1956 ret = info->hdl.error;
1957
1958 goto hdl_free;
1959 }
1960 /*
1961 * We have checked empirically that hw allows to read back the gain
1962 * value chosen by auto gain but that's not the case for auto exposure.
1963 */
1964 v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true);
1965 v4l2_ctrl_auto_cluster(2, &info->auto_exposure,
1966 V4L2_EXPOSURE_MANUAL, false);
1967 v4l2_ctrl_cluster(2, &info->saturation);
1968
1969 #if defined(CONFIG_MEDIA_CONTROLLER)
1970 info->pad.flags = MEDIA_PAD_FL_SOURCE;
1971 info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1972 ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
1973 if (ret < 0)
1974 goto hdl_free;
1975 #endif
1976
1977 v4l2_ctrl_handler_setup(&info->hdl);
1978
1979 ret = v4l2_async_register_subdev(&info->sd);
1980 if (ret < 0)
1981 goto entity_cleanup;
1982
1983 ov7670_power_off(sd);
1984 return 0;
1985
1986 entity_cleanup:
1987 media_entity_cleanup(&info->sd.entity);
1988 hdl_free:
1989 v4l2_ctrl_handler_free(&info->hdl);
1990 power_off:
1991 ov7670_power_off(sd);
1992 return ret;
1993 }
1994
1995 static int ov7670_remove(struct i2c_client *client)
1996 {
1997 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1998 struct ov7670_info *info = to_state(sd);
1999
2000 v4l2_async_unregister_subdev(sd);
2001 v4l2_ctrl_handler_free(&info->hdl);
2002 media_entity_cleanup(&info->sd.entity);
2003 ov7670_power_off(sd);
2004 return 0;
2005 }
2006
2007 static const struct i2c_device_id ov7670_id[] = {
2008 { "ov7670", MODEL_OV7670 },
2009 { "ov7675", MODEL_OV7675 },
2010 { }
2011 };
2012 MODULE_DEVICE_TABLE(i2c, ov7670_id);
2013
2014 #if IS_ENABLED(CONFIG_OF)
2015 static const struct of_device_id ov7670_of_match[] = {
2016 { .compatible = "ovti,ov7670", },
2017 { /* sentinel */ },
2018 };
2019 MODULE_DEVICE_TABLE(of, ov7670_of_match);
2020 #endif
2021
2022 static struct i2c_driver ov7670_driver = {
2023 .driver = {
2024 .name = "ov7670",
2025 .of_match_table = of_match_ptr(ov7670_of_match),
2026 },
2027 .probe = ov7670_probe,
2028 .remove = ov7670_remove,
2029 .id_table = ov7670_id,
2030 };
2031
2032 module_i2c_driver(ov7670_driver);
Linux with added FPC-III support