gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / media / platform / rcar_drif.c
blob3d2451ac347d71c851833b3b0a87d04564ed8115
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * R-Car Gen3 Digital Radio Interface (DRIF) driver
5 * Copyright (C) 2017 Renesas Electronics Corporation
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
14 * The R-Car DRIF is a receive only MSIOF like controller with an
15 * external master device driving the SCK. It receives data into a FIFO,
16 * then this driver uses the SYS-DMAC engine to move the data from
17 * the device to memory.
19 * Each DRIF channel DRIFx (as per datasheet) contains two internal
20 * channels DRIFx0 & DRIFx1 within itself with each having its own resources
21 * like module clk, register set, irq and dma. These internal channels share
22 * common CLK & SYNC from master. The two data pins D0 & D1 shall be
23 * considered to represent the two internal channels. This internal split
24 * is not visible to the master device.
26 * Depending on the master device, a DRIF channel can use
27 * (1) both internal channels (D0 & D1) to receive data in parallel (or)
28 * (2) one internal channel (D0 or D1) to receive data
30 * The primary design goal of this controller is to act as a Digital Radio
31 * Interface that receives digital samples from a tuner device. Hence the
32 * driver exposes the device as a V4L2 SDR device. In order to qualify as
33 * a V4L2 SDR device, it should possess a tuner interface as mandated by the
34 * framework. This driver expects a tuner driver (sub-device) to bind
35 * asynchronously with this device and the combined drivers shall expose
36 * a V4L2 compliant SDR device. The DRIF driver is independent of the
37 * tuner vendor.
39 * The DRIF h/w can support I2S mode and Frame start synchronization pulse mode.
40 * This driver is tested for I2S mode only because of the availability of
41 * suitable master devices. Hence, not all configurable options of DRIF h/w
42 * like lsb/msb first, syncdl, dtdl etc. are exposed via DT and I2S defaults
43 * are used. These can be exposed later if needed after testing.
45 #include <linux/bitops.h>
46 #include <linux/clk.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/dmaengine.h>
49 #include <linux/ioctl.h>
50 #include <linux/iopoll.h>
51 #include <linux/module.h>
52 #include <linux/of_graph.h>
53 #include <linux/of_device.h>
54 #include <linux/platform_device.h>
55 #include <linux/sched.h>
56 #include <media/v4l2-async.h>
57 #include <media/v4l2-ctrls.h>
58 #include <media/v4l2-device.h>
59 #include <media/v4l2-event.h>
60 #include <media/v4l2-fh.h>
61 #include <media/v4l2-ioctl.h>
62 #include <media/videobuf2-v4l2.h>
63 #include <media/videobuf2-vmalloc.h>
65 /* DRIF register offsets */
66 #define RCAR_DRIF_SITMDR1 0x00
67 #define RCAR_DRIF_SITMDR2 0x04
68 #define RCAR_DRIF_SITMDR3 0x08
69 #define RCAR_DRIF_SIRMDR1 0x10
70 #define RCAR_DRIF_SIRMDR2 0x14
71 #define RCAR_DRIF_SIRMDR3 0x18
72 #define RCAR_DRIF_SICTR 0x28
73 #define RCAR_DRIF_SIFCTR 0x30
74 #define RCAR_DRIF_SISTR 0x40
75 #define RCAR_DRIF_SIIER 0x44
76 #define RCAR_DRIF_SIRFDR 0x60
78 #define RCAR_DRIF_RFOVF BIT(3) /* Receive FIFO overflow */
79 #define RCAR_DRIF_RFUDF BIT(4) /* Receive FIFO underflow */
80 #define RCAR_DRIF_RFSERR BIT(5) /* Receive frame sync error */
81 #define RCAR_DRIF_REOF BIT(7) /* Frame reception end */
82 #define RCAR_DRIF_RDREQ BIT(12) /* Receive data xfer req */
83 #define RCAR_DRIF_RFFUL BIT(13) /* Receive FIFO full */
85 /* SIRMDR1 */
86 #define RCAR_DRIF_SIRMDR1_SYNCMD_FRAME (0 << 28)
87 #define RCAR_DRIF_SIRMDR1_SYNCMD_LR (3 << 28)
89 #define RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH (0 << 25)
90 #define RCAR_DRIF_SIRMDR1_SYNCAC_POL_LOW (1 << 25)
92 #define RCAR_DRIF_SIRMDR1_MSB_FIRST (0 << 24)
93 #define RCAR_DRIF_SIRMDR1_LSB_FIRST (1 << 24)
95 #define RCAR_DRIF_SIRMDR1_DTDL_0 (0 << 20)
96 #define RCAR_DRIF_SIRMDR1_DTDL_1 (1 << 20)
97 #define RCAR_DRIF_SIRMDR1_DTDL_2 (2 << 20)
98 #define RCAR_DRIF_SIRMDR1_DTDL_0PT5 (5 << 20)
99 #define RCAR_DRIF_SIRMDR1_DTDL_1PT5 (6 << 20)
101 #define RCAR_DRIF_SIRMDR1_SYNCDL_0 (0 << 20)
102 #define RCAR_DRIF_SIRMDR1_SYNCDL_1 (1 << 20)
103 #define RCAR_DRIF_SIRMDR1_SYNCDL_2 (2 << 20)
104 #define RCAR_DRIF_SIRMDR1_SYNCDL_3 (3 << 20)
105 #define RCAR_DRIF_SIRMDR1_SYNCDL_0PT5 (5 << 20)
106 #define RCAR_DRIF_SIRMDR1_SYNCDL_1PT5 (6 << 20)
108 #define RCAR_DRIF_MDR_GRPCNT(n) (((n) - 1) << 30)
109 #define RCAR_DRIF_MDR_BITLEN(n) (((n) - 1) << 24)
110 #define RCAR_DRIF_MDR_WDCNT(n) (((n) - 1) << 16)
112 /* Hidden Transmit register that controls CLK & SYNC */
113 #define RCAR_DRIF_SITMDR1_PCON BIT(30)
115 #define RCAR_DRIF_SICTR_RX_RISING_EDGE BIT(26)
116 #define RCAR_DRIF_SICTR_RX_EN BIT(8)
117 #define RCAR_DRIF_SICTR_RESET BIT(0)
119 /* Constants */
120 #define RCAR_DRIF_NUM_HWBUFS 32
121 #define RCAR_DRIF_MAX_DEVS 4
122 #define RCAR_DRIF_DEFAULT_NUM_HWBUFS 16
123 #define RCAR_DRIF_DEFAULT_HWBUF_SIZE (4 * PAGE_SIZE)
124 #define RCAR_DRIF_MAX_CHANNEL 2
125 #define RCAR_SDR_BUFFER_SIZE SZ_64K
127 /* Internal buffer status flags */
128 #define RCAR_DRIF_BUF_DONE BIT(0) /* DMA completed */
129 #define RCAR_DRIF_BUF_OVERFLOW BIT(1) /* Overflow detected */
131 #define to_rcar_drif_buf_pair(sdr, ch_num, idx) \
132 (&((sdr)->ch[!(ch_num)]->buf[(idx)]))
134 #define for_each_rcar_drif_channel(ch, ch_mask) \
135 for_each_set_bit(ch, ch_mask, RCAR_DRIF_MAX_CHANNEL)
137 /* Debug */
138 #define rdrif_dbg(sdr, fmt, arg...) \
139 dev_dbg(sdr->v4l2_dev.dev, fmt, ## arg)
141 #define rdrif_err(sdr, fmt, arg...) \
142 dev_err(sdr->v4l2_dev.dev, fmt, ## arg)
144 /* Stream formats */
145 struct rcar_drif_format {
146 u32 pixelformat;
147 u32 buffersize;
148 u32 bitlen;
149 u32 wdcnt;
150 u32 num_ch;
153 /* Format descriptions for capture */
154 static const struct rcar_drif_format formats[] = {
156 .pixelformat = V4L2_SDR_FMT_PCU16BE,
157 .buffersize = RCAR_SDR_BUFFER_SIZE,
158 .bitlen = 16,
159 .wdcnt = 1,
160 .num_ch = 2,
163 .pixelformat = V4L2_SDR_FMT_PCU18BE,
164 .buffersize = RCAR_SDR_BUFFER_SIZE,
165 .bitlen = 18,
166 .wdcnt = 1,
167 .num_ch = 2,
170 .pixelformat = V4L2_SDR_FMT_PCU20BE,
171 .buffersize = RCAR_SDR_BUFFER_SIZE,
172 .bitlen = 20,
173 .wdcnt = 1,
174 .num_ch = 2,
178 /* Buffer for a received frame from one or both internal channels */
179 struct rcar_drif_frame_buf {
180 /* Common v4l buffer stuff -- must be first */
181 struct vb2_v4l2_buffer vb;
182 struct list_head list;
185 /* OF graph endpoint's V4L2 async data */
186 struct rcar_drif_graph_ep {
187 struct v4l2_subdev *subdev; /* Async matched subdev */
188 struct v4l2_async_subdev asd; /* Async sub-device descriptor */
191 /* DMA buffer */
192 struct rcar_drif_hwbuf {
193 void *addr; /* CPU-side address */
194 unsigned int status; /* Buffer status flags */
197 /* Internal channel */
198 struct rcar_drif {
199 struct rcar_drif_sdr *sdr; /* Group device */
200 struct platform_device *pdev; /* Channel's pdev */
201 void __iomem *base; /* Base register address */
202 resource_size_t start; /* I/O resource offset */
203 struct dma_chan *dmach; /* Reserved DMA channel */
204 struct clk *clk; /* Module clock */
205 struct rcar_drif_hwbuf buf[RCAR_DRIF_NUM_HWBUFS]; /* H/W bufs */
206 dma_addr_t dma_handle; /* Handle for all bufs */
207 unsigned int num; /* Channel number */
208 bool acting_sdr; /* Channel acting as SDR device */
211 /* DRIF V4L2 SDR */
212 struct rcar_drif_sdr {
213 struct device *dev; /* Platform device */
214 struct video_device *vdev; /* V4L2 SDR device */
215 struct v4l2_device v4l2_dev; /* V4L2 device */
217 /* Videobuf2 queue and queued buffers list */
218 struct vb2_queue vb_queue;
219 struct list_head queued_bufs;
220 spinlock_t queued_bufs_lock; /* Protects queued_bufs */
221 spinlock_t dma_lock; /* To serialize DMA cb of channels */
223 struct mutex v4l2_mutex; /* To serialize ioctls */
224 struct mutex vb_queue_mutex; /* To serialize streaming ioctls */
225 struct v4l2_ctrl_handler ctrl_hdl; /* SDR control handler */
226 struct v4l2_async_notifier notifier; /* For subdev (tuner) */
227 struct rcar_drif_graph_ep ep; /* Endpoint V4L2 async data */
229 /* Current V4L2 SDR format ptr */
230 const struct rcar_drif_format *fmt;
232 /* Device tree SYNC properties */
233 u32 mdr1;
235 /* Internals */
236 struct rcar_drif *ch[RCAR_DRIF_MAX_CHANNEL]; /* DRIFx0,1 */
237 unsigned long hw_ch_mask; /* Enabled channels per DT */
238 unsigned long cur_ch_mask; /* Used channels for an SDR FMT */
239 u32 num_hw_ch; /* Num of DT enabled channels */
240 u32 num_cur_ch; /* Num of used channels */
241 u32 hwbuf_size; /* Each DMA buffer size */
242 u32 produced; /* Buffers produced by sdr dev */
245 /* Register access functions */
246 static void rcar_drif_write(struct rcar_drif *ch, u32 offset, u32 data)
248 writel(data, ch->base + offset);
251 static u32 rcar_drif_read(struct rcar_drif *ch, u32 offset)
253 return readl(ch->base + offset);
256 /* Release DMA channels */
257 static void rcar_drif_release_dmachannels(struct rcar_drif_sdr *sdr)
259 unsigned int i;
261 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask)
262 if (sdr->ch[i]->dmach) {
263 dma_release_channel(sdr->ch[i]->dmach);
264 sdr->ch[i]->dmach = NULL;
268 /* Allocate DMA channels */
269 static int rcar_drif_alloc_dmachannels(struct rcar_drif_sdr *sdr)
271 struct dma_slave_config dma_cfg;
272 unsigned int i;
273 int ret;
275 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
276 struct rcar_drif *ch = sdr->ch[i];
278 ch->dmach = dma_request_chan(&ch->pdev->dev, "rx");
279 if (IS_ERR(ch->dmach)) {
280 ret = PTR_ERR(ch->dmach);
281 if (ret != -EPROBE_DEFER)
282 rdrif_err(sdr,
283 "ch%u: dma channel req failed: %pe\n",
284 i, ch->dmach);
285 ch->dmach = NULL;
286 goto dmach_error;
289 /* Configure slave */
290 memset(&dma_cfg, 0, sizeof(dma_cfg));
291 dma_cfg.src_addr = (phys_addr_t)(ch->start + RCAR_DRIF_SIRFDR);
292 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
293 ret = dmaengine_slave_config(ch->dmach, &dma_cfg);
294 if (ret) {
295 rdrif_err(sdr, "ch%u: dma slave config failed\n", i);
296 goto dmach_error;
299 return 0;
301 dmach_error:
302 rcar_drif_release_dmachannels(sdr);
303 return ret;
306 /* Release queued vb2 buffers */
307 static void rcar_drif_release_queued_bufs(struct rcar_drif_sdr *sdr,
308 enum vb2_buffer_state state)
310 struct rcar_drif_frame_buf *fbuf, *tmp;
311 unsigned long flags;
313 spin_lock_irqsave(&sdr->queued_bufs_lock, flags);
314 list_for_each_entry_safe(fbuf, tmp, &sdr->queued_bufs, list) {
315 list_del(&fbuf->list);
316 vb2_buffer_done(&fbuf->vb.vb2_buf, state);
318 spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
321 /* Set MDR defaults */
322 static inline void rcar_drif_set_mdr1(struct rcar_drif_sdr *sdr)
324 unsigned int i;
326 /* Set defaults for enabled internal channels */
327 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
328 /* Refer MSIOF section in manual for this register setting */
329 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SITMDR1,
330 RCAR_DRIF_SITMDR1_PCON);
332 /* Setup MDR1 value */
333 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR1, sdr->mdr1);
335 rdrif_dbg(sdr, "ch%u: mdr1 = 0x%08x",
336 i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR1));
340 /* Set DRIF receive format */
341 static int rcar_drif_set_format(struct rcar_drif_sdr *sdr)
343 unsigned int i;
345 rdrif_dbg(sdr, "setfmt: bitlen %u wdcnt %u num_ch %u\n",
346 sdr->fmt->bitlen, sdr->fmt->wdcnt, sdr->fmt->num_ch);
348 /* Sanity check */
349 if (sdr->fmt->num_ch > sdr->num_cur_ch) {
350 rdrif_err(sdr, "fmt num_ch %u cur_ch %u mismatch\n",
351 sdr->fmt->num_ch, sdr->num_cur_ch);
352 return -EINVAL;
355 /* Setup group, bitlen & wdcnt */
356 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
357 u32 mdr;
359 /* Two groups */
360 mdr = RCAR_DRIF_MDR_GRPCNT(2) |
361 RCAR_DRIF_MDR_BITLEN(sdr->fmt->bitlen) |
362 RCAR_DRIF_MDR_WDCNT(sdr->fmt->wdcnt);
363 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR2, mdr);
365 mdr = RCAR_DRIF_MDR_BITLEN(sdr->fmt->bitlen) |
366 RCAR_DRIF_MDR_WDCNT(sdr->fmt->wdcnt);
367 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR3, mdr);
369 rdrif_dbg(sdr, "ch%u: new mdr[2,3] = 0x%08x, 0x%08x\n",
370 i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR2),
371 rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR3));
373 return 0;
376 /* Release DMA buffers */
377 static void rcar_drif_release_buf(struct rcar_drif_sdr *sdr)
379 unsigned int i;
381 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
382 struct rcar_drif *ch = sdr->ch[i];
384 /* First entry contains the dma buf ptr */
385 if (ch->buf[0].addr) {
386 dma_free_coherent(&ch->pdev->dev,
387 sdr->hwbuf_size * RCAR_DRIF_NUM_HWBUFS,
388 ch->buf[0].addr, ch->dma_handle);
389 ch->buf[0].addr = NULL;
394 /* Request DMA buffers */
395 static int rcar_drif_request_buf(struct rcar_drif_sdr *sdr)
397 int ret = -ENOMEM;
398 unsigned int i, j;
399 void *addr;
401 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
402 struct rcar_drif *ch = sdr->ch[i];
404 /* Allocate DMA buffers */
405 addr = dma_alloc_coherent(&ch->pdev->dev,
406 sdr->hwbuf_size * RCAR_DRIF_NUM_HWBUFS,
407 &ch->dma_handle, GFP_KERNEL);
408 if (!addr) {
409 rdrif_err(sdr,
410 "ch%u: dma alloc failed. num hwbufs %u size %u\n",
411 i, RCAR_DRIF_NUM_HWBUFS, sdr->hwbuf_size);
412 goto error;
415 /* Split the chunk and populate bufctxt */
416 for (j = 0; j < RCAR_DRIF_NUM_HWBUFS; j++) {
417 ch->buf[j].addr = addr + (j * sdr->hwbuf_size);
418 ch->buf[j].status = 0;
421 return 0;
422 error:
423 return ret;
426 /* Setup vb_queue minimum buffer requirements */
427 static int rcar_drif_queue_setup(struct vb2_queue *vq,
428 unsigned int *num_buffers, unsigned int *num_planes,
429 unsigned int sizes[], struct device *alloc_devs[])
431 struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq);
433 /* Need at least 16 buffers */
434 if (vq->num_buffers + *num_buffers < 16)
435 *num_buffers = 16 - vq->num_buffers;
437 *num_planes = 1;
438 sizes[0] = PAGE_ALIGN(sdr->fmt->buffersize);
439 rdrif_dbg(sdr, "num_bufs %d sizes[0] %d\n", *num_buffers, sizes[0]);
441 return 0;
444 /* Enqueue buffer */
445 static void rcar_drif_buf_queue(struct vb2_buffer *vb)
447 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
448 struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vb->vb2_queue);
449 struct rcar_drif_frame_buf *fbuf =
450 container_of(vbuf, struct rcar_drif_frame_buf, vb);
451 unsigned long flags;
453 rdrif_dbg(sdr, "buf_queue idx %u\n", vb->index);
454 spin_lock_irqsave(&sdr->queued_bufs_lock, flags);
455 list_add_tail(&fbuf->list, &sdr->queued_bufs);
456 spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
459 /* Get a frame buf from list */
460 static struct rcar_drif_frame_buf *
461 rcar_drif_get_fbuf(struct rcar_drif_sdr *sdr)
463 struct rcar_drif_frame_buf *fbuf;
464 unsigned long flags;
466 spin_lock_irqsave(&sdr->queued_bufs_lock, flags);
467 fbuf = list_first_entry_or_null(&sdr->queued_bufs, struct
468 rcar_drif_frame_buf, list);
469 if (!fbuf) {
471 * App is late in enqueing buffers. Samples lost & there will
472 * be a gap in sequence number when app recovers
474 rdrif_dbg(sdr, "\napp late: prod %u\n", sdr->produced);
475 spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
476 return NULL;
478 list_del(&fbuf->list);
479 spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
481 return fbuf;
484 /* Helpers to set/clear buf pair status */
485 static inline bool rcar_drif_bufs_done(struct rcar_drif_hwbuf **buf)
487 return (buf[0]->status & buf[1]->status & RCAR_DRIF_BUF_DONE);
490 static inline bool rcar_drif_bufs_overflow(struct rcar_drif_hwbuf **buf)
492 return ((buf[0]->status | buf[1]->status) & RCAR_DRIF_BUF_OVERFLOW);
495 static inline void rcar_drif_bufs_clear(struct rcar_drif_hwbuf **buf,
496 unsigned int bit)
498 unsigned int i;
500 for (i = 0; i < RCAR_DRIF_MAX_CHANNEL; i++)
501 buf[i]->status &= ~bit;
504 /* Channel DMA complete */
505 static void rcar_drif_channel_complete(struct rcar_drif *ch, u32 idx)
507 u32 str;
509 ch->buf[idx].status |= RCAR_DRIF_BUF_DONE;
511 /* Check for DRIF errors */
512 str = rcar_drif_read(ch, RCAR_DRIF_SISTR);
513 if (unlikely(str & RCAR_DRIF_RFOVF)) {
514 /* Writing the same clears it */
515 rcar_drif_write(ch, RCAR_DRIF_SISTR, str);
517 /* Overflow: some samples are lost */
518 ch->buf[idx].status |= RCAR_DRIF_BUF_OVERFLOW;
522 /* DMA callback for each stage */
523 static void rcar_drif_dma_complete(void *dma_async_param)
525 struct rcar_drif *ch = dma_async_param;
526 struct rcar_drif_sdr *sdr = ch->sdr;
527 struct rcar_drif_hwbuf *buf[RCAR_DRIF_MAX_CHANNEL];
528 struct rcar_drif_frame_buf *fbuf;
529 bool overflow = false;
530 u32 idx, produced;
531 unsigned int i;
533 spin_lock(&sdr->dma_lock);
535 /* DMA can be terminated while the callback was waiting on lock */
536 if (!vb2_is_streaming(&sdr->vb_queue)) {
537 spin_unlock(&sdr->dma_lock);
538 return;
541 idx = sdr->produced % RCAR_DRIF_NUM_HWBUFS;
542 rcar_drif_channel_complete(ch, idx);
544 if (sdr->num_cur_ch == RCAR_DRIF_MAX_CHANNEL) {
545 buf[0] = ch->num ? to_rcar_drif_buf_pair(sdr, ch->num, idx) :
546 &ch->buf[idx];
547 buf[1] = ch->num ? &ch->buf[idx] :
548 to_rcar_drif_buf_pair(sdr, ch->num, idx);
550 /* Check if both DMA buffers are done */
551 if (!rcar_drif_bufs_done(buf)) {
552 spin_unlock(&sdr->dma_lock);
553 return;
556 /* Clear buf done status */
557 rcar_drif_bufs_clear(buf, RCAR_DRIF_BUF_DONE);
559 if (rcar_drif_bufs_overflow(buf)) {
560 overflow = true;
561 /* Clear the flag in status */
562 rcar_drif_bufs_clear(buf, RCAR_DRIF_BUF_OVERFLOW);
564 } else {
565 buf[0] = &ch->buf[idx];
566 if (buf[0]->status & RCAR_DRIF_BUF_OVERFLOW) {
567 overflow = true;
568 /* Clear the flag in status */
569 buf[0]->status &= ~RCAR_DRIF_BUF_OVERFLOW;
573 /* Buffer produced for consumption */
574 produced = sdr->produced++;
575 spin_unlock(&sdr->dma_lock);
577 rdrif_dbg(sdr, "ch%u: prod %u\n", ch->num, produced);
579 /* Get fbuf */
580 fbuf = rcar_drif_get_fbuf(sdr);
581 if (!fbuf)
582 return;
584 for (i = 0; i < RCAR_DRIF_MAX_CHANNEL; i++)
585 memcpy(vb2_plane_vaddr(&fbuf->vb.vb2_buf, 0) +
586 i * sdr->hwbuf_size, buf[i]->addr, sdr->hwbuf_size);
588 fbuf->vb.field = V4L2_FIELD_NONE;
589 fbuf->vb.sequence = produced;
590 fbuf->vb.vb2_buf.timestamp = ktime_get_ns();
591 vb2_set_plane_payload(&fbuf->vb.vb2_buf, 0, sdr->fmt->buffersize);
593 /* Set error state on overflow */
594 vb2_buffer_done(&fbuf->vb.vb2_buf,
595 overflow ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
598 static int rcar_drif_qbuf(struct rcar_drif *ch)
600 struct rcar_drif_sdr *sdr = ch->sdr;
601 dma_addr_t addr = ch->dma_handle;
602 struct dma_async_tx_descriptor *rxd;
603 dma_cookie_t cookie;
604 int ret = -EIO;
606 /* Setup cyclic DMA with given buffers */
607 rxd = dmaengine_prep_dma_cyclic(ch->dmach, addr,
608 sdr->hwbuf_size * RCAR_DRIF_NUM_HWBUFS,
609 sdr->hwbuf_size, DMA_DEV_TO_MEM,
610 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
611 if (!rxd) {
612 rdrif_err(sdr, "ch%u: prep dma cyclic failed\n", ch->num);
613 return ret;
616 /* Submit descriptor */
617 rxd->callback = rcar_drif_dma_complete;
618 rxd->callback_param = ch;
619 cookie = dmaengine_submit(rxd);
620 if (dma_submit_error(cookie)) {
621 rdrif_err(sdr, "ch%u: dma submit failed\n", ch->num);
622 return ret;
625 dma_async_issue_pending(ch->dmach);
626 return 0;
629 /* Enable reception */
630 static int rcar_drif_enable_rx(struct rcar_drif_sdr *sdr)
632 unsigned int i;
633 u32 ctr;
634 int ret = -EINVAL;
637 * When both internal channels are enabled, they can be synchronized
638 * only by the master
641 /* Enable receive */
642 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
643 ctr = rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR);
644 ctr |= (RCAR_DRIF_SICTR_RX_RISING_EDGE |
645 RCAR_DRIF_SICTR_RX_EN);
646 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SICTR, ctr);
649 /* Check receive enabled */
650 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
651 ret = readl_poll_timeout(sdr->ch[i]->base + RCAR_DRIF_SICTR,
652 ctr, ctr & RCAR_DRIF_SICTR_RX_EN, 7, 100000);
653 if (ret) {
654 rdrif_err(sdr, "ch%u: rx en failed. ctr 0x%08x\n", i,
655 rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR));
656 break;
659 return ret;
662 /* Disable reception */
663 static void rcar_drif_disable_rx(struct rcar_drif_sdr *sdr)
665 unsigned int i;
666 u32 ctr;
667 int ret;
669 /* Disable receive */
670 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
671 ctr = rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR);
672 ctr &= ~RCAR_DRIF_SICTR_RX_EN;
673 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SICTR, ctr);
676 /* Check receive disabled */
677 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
678 ret = readl_poll_timeout(sdr->ch[i]->base + RCAR_DRIF_SICTR,
679 ctr, !(ctr & RCAR_DRIF_SICTR_RX_EN), 7, 100000);
680 if (ret)
681 dev_warn(&sdr->vdev->dev,
682 "ch%u: failed to disable rx. ctr 0x%08x\n",
683 i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR));
687 /* Stop channel */
688 static void rcar_drif_stop_channel(struct rcar_drif *ch)
690 /* Disable DMA receive interrupt */
691 rcar_drif_write(ch, RCAR_DRIF_SIIER, 0x00000000);
693 /* Terminate all DMA transfers */
694 dmaengine_terminate_sync(ch->dmach);
697 /* Stop receive operation */
698 static void rcar_drif_stop(struct rcar_drif_sdr *sdr)
700 unsigned int i;
702 /* Disable Rx */
703 rcar_drif_disable_rx(sdr);
705 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask)
706 rcar_drif_stop_channel(sdr->ch[i]);
709 /* Start channel */
710 static int rcar_drif_start_channel(struct rcar_drif *ch)
712 struct rcar_drif_sdr *sdr = ch->sdr;
713 u32 ctr, str;
714 int ret;
716 /* Reset receive */
717 rcar_drif_write(ch, RCAR_DRIF_SICTR, RCAR_DRIF_SICTR_RESET);
718 ret = readl_poll_timeout(ch->base + RCAR_DRIF_SICTR, ctr,
719 !(ctr & RCAR_DRIF_SICTR_RESET), 7, 100000);
720 if (ret) {
721 rdrif_err(sdr, "ch%u: failed to reset rx. ctr 0x%08x\n",
722 ch->num, rcar_drif_read(ch, RCAR_DRIF_SICTR));
723 return ret;
726 /* Queue buffers for DMA */
727 ret = rcar_drif_qbuf(ch);
728 if (ret)
729 return ret;
731 /* Clear status register flags */
732 str = RCAR_DRIF_RFFUL | RCAR_DRIF_REOF | RCAR_DRIF_RFSERR |
733 RCAR_DRIF_RFUDF | RCAR_DRIF_RFOVF;
734 rcar_drif_write(ch, RCAR_DRIF_SISTR, str);
736 /* Enable DMA receive interrupt */
737 rcar_drif_write(ch, RCAR_DRIF_SIIER, 0x00009000);
739 return ret;
742 /* Start receive operation */
743 static int rcar_drif_start(struct rcar_drif_sdr *sdr)
745 unsigned long enabled = 0;
746 unsigned int i;
747 int ret;
749 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
750 ret = rcar_drif_start_channel(sdr->ch[i]);
751 if (ret)
752 goto start_error;
753 enabled |= BIT(i);
756 ret = rcar_drif_enable_rx(sdr);
757 if (ret)
758 goto enable_error;
760 sdr->produced = 0;
761 return ret;
763 enable_error:
764 rcar_drif_disable_rx(sdr);
765 start_error:
766 for_each_rcar_drif_channel(i, &enabled)
767 rcar_drif_stop_channel(sdr->ch[i]);
769 return ret;
772 /* Start streaming */
773 static int rcar_drif_start_streaming(struct vb2_queue *vq, unsigned int count)
775 struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq);
776 unsigned long enabled = 0;
777 unsigned int i;
778 int ret;
780 mutex_lock(&sdr->v4l2_mutex);
782 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
783 ret = clk_prepare_enable(sdr->ch[i]->clk);
784 if (ret)
785 goto error;
786 enabled |= BIT(i);
789 /* Set default MDRx settings */
790 rcar_drif_set_mdr1(sdr);
792 /* Set new format */
793 ret = rcar_drif_set_format(sdr);
794 if (ret)
795 goto error;
797 if (sdr->num_cur_ch == RCAR_DRIF_MAX_CHANNEL)
798 sdr->hwbuf_size = sdr->fmt->buffersize / RCAR_DRIF_MAX_CHANNEL;
799 else
800 sdr->hwbuf_size = sdr->fmt->buffersize;
802 rdrif_dbg(sdr, "num hwbufs %u, hwbuf_size %u\n",
803 RCAR_DRIF_NUM_HWBUFS, sdr->hwbuf_size);
805 /* Alloc DMA channel */
806 ret = rcar_drif_alloc_dmachannels(sdr);
807 if (ret)
808 goto error;
810 /* Request buffers */
811 ret = rcar_drif_request_buf(sdr);
812 if (ret)
813 goto error;
815 /* Start Rx */
816 ret = rcar_drif_start(sdr);
817 if (ret)
818 goto error;
820 mutex_unlock(&sdr->v4l2_mutex);
822 return ret;
824 error:
825 rcar_drif_release_queued_bufs(sdr, VB2_BUF_STATE_QUEUED);
826 rcar_drif_release_buf(sdr);
827 rcar_drif_release_dmachannels(sdr);
828 for_each_rcar_drif_channel(i, &enabled)
829 clk_disable_unprepare(sdr->ch[i]->clk);
831 mutex_unlock(&sdr->v4l2_mutex);
833 return ret;
836 /* Stop streaming */
837 static void rcar_drif_stop_streaming(struct vb2_queue *vq)
839 struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq);
840 unsigned int i;
842 mutex_lock(&sdr->v4l2_mutex);
844 /* Stop hardware streaming */
845 rcar_drif_stop(sdr);
847 /* Return all queued buffers to vb2 */
848 rcar_drif_release_queued_bufs(sdr, VB2_BUF_STATE_ERROR);
850 /* Release buf */
851 rcar_drif_release_buf(sdr);
853 /* Release DMA channel resources */
854 rcar_drif_release_dmachannels(sdr);
856 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask)
857 clk_disable_unprepare(sdr->ch[i]->clk);
859 mutex_unlock(&sdr->v4l2_mutex);
862 /* Vb2 ops */
863 static const struct vb2_ops rcar_drif_vb2_ops = {
864 .queue_setup = rcar_drif_queue_setup,
865 .buf_queue = rcar_drif_buf_queue,
866 .start_streaming = rcar_drif_start_streaming,
867 .stop_streaming = rcar_drif_stop_streaming,
868 .wait_prepare = vb2_ops_wait_prepare,
869 .wait_finish = vb2_ops_wait_finish,
872 static int rcar_drif_querycap(struct file *file, void *fh,
873 struct v4l2_capability *cap)
875 struct rcar_drif_sdr *sdr = video_drvdata(file);
877 strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver));
878 strscpy(cap->card, sdr->vdev->name, sizeof(cap->card));
879 snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
880 sdr->vdev->name);
882 return 0;
885 static int rcar_drif_set_default_format(struct rcar_drif_sdr *sdr)
887 unsigned int i;
889 for (i = 0; i < ARRAY_SIZE(formats); i++) {
890 /* Matching fmt based on required channels is set as default */
891 if (sdr->num_hw_ch == formats[i].num_ch) {
892 sdr->fmt = &formats[i];
893 sdr->cur_ch_mask = sdr->hw_ch_mask;
894 sdr->num_cur_ch = sdr->num_hw_ch;
895 dev_dbg(sdr->dev, "default fmt[%u]: mask %lu num %u\n",
896 i, sdr->cur_ch_mask, sdr->num_cur_ch);
897 return 0;
900 return -EINVAL;
903 static int rcar_drif_enum_fmt_sdr_cap(struct file *file, void *priv,
904 struct v4l2_fmtdesc *f)
906 if (f->index >= ARRAY_SIZE(formats))
907 return -EINVAL;
909 f->pixelformat = formats[f->index].pixelformat;
911 return 0;
914 static int rcar_drif_g_fmt_sdr_cap(struct file *file, void *priv,
915 struct v4l2_format *f)
917 struct rcar_drif_sdr *sdr = video_drvdata(file);
919 memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved));
920 f->fmt.sdr.pixelformat = sdr->fmt->pixelformat;
921 f->fmt.sdr.buffersize = sdr->fmt->buffersize;
923 return 0;
926 static int rcar_drif_s_fmt_sdr_cap(struct file *file, void *priv,
927 struct v4l2_format *f)
929 struct rcar_drif_sdr *sdr = video_drvdata(file);
930 struct vb2_queue *q = &sdr->vb_queue;
931 unsigned int i;
933 if (vb2_is_busy(q))
934 return -EBUSY;
936 for (i = 0; i < ARRAY_SIZE(formats); i++) {
937 if (formats[i].pixelformat == f->fmt.sdr.pixelformat)
938 break;
941 if (i == ARRAY_SIZE(formats))
942 i = 0; /* Set the 1st format as default on no match */
944 sdr->fmt = &formats[i];
945 f->fmt.sdr.pixelformat = sdr->fmt->pixelformat;
946 f->fmt.sdr.buffersize = formats[i].buffersize;
947 memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved));
950 * If a format demands one channel only out of two
951 * enabled channels, pick the 0th channel.
953 if (formats[i].num_ch < sdr->num_hw_ch) {
954 sdr->cur_ch_mask = BIT(0);
955 sdr->num_cur_ch = formats[i].num_ch;
956 } else {
957 sdr->cur_ch_mask = sdr->hw_ch_mask;
958 sdr->num_cur_ch = sdr->num_hw_ch;
961 rdrif_dbg(sdr, "cur: idx %u mask %lu num %u\n",
962 i, sdr->cur_ch_mask, sdr->num_cur_ch);
964 return 0;
967 static int rcar_drif_try_fmt_sdr_cap(struct file *file, void *priv,
968 struct v4l2_format *f)
970 unsigned int i;
972 for (i = 0; i < ARRAY_SIZE(formats); i++) {
973 if (formats[i].pixelformat == f->fmt.sdr.pixelformat) {
974 f->fmt.sdr.buffersize = formats[i].buffersize;
975 return 0;
979 f->fmt.sdr.pixelformat = formats[0].pixelformat;
980 f->fmt.sdr.buffersize = formats[0].buffersize;
981 memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved));
983 return 0;
986 /* Tuner subdev ioctls */
987 static int rcar_drif_enum_freq_bands(struct file *file, void *priv,
988 struct v4l2_frequency_band *band)
990 struct rcar_drif_sdr *sdr = video_drvdata(file);
992 return v4l2_subdev_call(sdr->ep.subdev, tuner, enum_freq_bands, band);
995 static int rcar_drif_g_frequency(struct file *file, void *priv,
996 struct v4l2_frequency *f)
998 struct rcar_drif_sdr *sdr = video_drvdata(file);
1000 return v4l2_subdev_call(sdr->ep.subdev, tuner, g_frequency, f);
1003 static int rcar_drif_s_frequency(struct file *file, void *priv,
1004 const struct v4l2_frequency *f)
1006 struct rcar_drif_sdr *sdr = video_drvdata(file);
1008 return v4l2_subdev_call(sdr->ep.subdev, tuner, s_frequency, f);
1011 static int rcar_drif_g_tuner(struct file *file, void *priv,
1012 struct v4l2_tuner *vt)
1014 struct rcar_drif_sdr *sdr = video_drvdata(file);
1016 return v4l2_subdev_call(sdr->ep.subdev, tuner, g_tuner, vt);
1019 static int rcar_drif_s_tuner(struct file *file, void *priv,
1020 const struct v4l2_tuner *vt)
1022 struct rcar_drif_sdr *sdr = video_drvdata(file);
1024 return v4l2_subdev_call(sdr->ep.subdev, tuner, s_tuner, vt);
1027 static const struct v4l2_ioctl_ops rcar_drif_ioctl_ops = {
1028 .vidioc_querycap = rcar_drif_querycap,
1030 .vidioc_enum_fmt_sdr_cap = rcar_drif_enum_fmt_sdr_cap,
1031 .vidioc_g_fmt_sdr_cap = rcar_drif_g_fmt_sdr_cap,
1032 .vidioc_s_fmt_sdr_cap = rcar_drif_s_fmt_sdr_cap,
1033 .vidioc_try_fmt_sdr_cap = rcar_drif_try_fmt_sdr_cap,
1035 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1036 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1037 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1038 .vidioc_querybuf = vb2_ioctl_querybuf,
1039 .vidioc_qbuf = vb2_ioctl_qbuf,
1040 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1042 .vidioc_streamon = vb2_ioctl_streamon,
1043 .vidioc_streamoff = vb2_ioctl_streamoff,
1045 .vidioc_s_frequency = rcar_drif_s_frequency,
1046 .vidioc_g_frequency = rcar_drif_g_frequency,
1047 .vidioc_s_tuner = rcar_drif_s_tuner,
1048 .vidioc_g_tuner = rcar_drif_g_tuner,
1049 .vidioc_enum_freq_bands = rcar_drif_enum_freq_bands,
1050 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1051 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1052 .vidioc_log_status = v4l2_ctrl_log_status,
1055 static const struct v4l2_file_operations rcar_drif_fops = {
1056 .owner = THIS_MODULE,
1057 .open = v4l2_fh_open,
1058 .release = vb2_fop_release,
1059 .read = vb2_fop_read,
1060 .poll = vb2_fop_poll,
1061 .mmap = vb2_fop_mmap,
1062 .unlocked_ioctl = video_ioctl2,
1065 static int rcar_drif_sdr_register(struct rcar_drif_sdr *sdr)
1067 int ret;
1069 /* Init video_device structure */
1070 sdr->vdev = video_device_alloc();
1071 if (!sdr->vdev)
1072 return -ENOMEM;
1074 snprintf(sdr->vdev->name, sizeof(sdr->vdev->name), "R-Car DRIF");
1075 sdr->vdev->fops = &rcar_drif_fops;
1076 sdr->vdev->ioctl_ops = &rcar_drif_ioctl_ops;
1077 sdr->vdev->release = video_device_release;
1078 sdr->vdev->lock = &sdr->v4l2_mutex;
1079 sdr->vdev->queue = &sdr->vb_queue;
1080 sdr->vdev->queue->lock = &sdr->vb_queue_mutex;
1081 sdr->vdev->ctrl_handler = &sdr->ctrl_hdl;
1082 sdr->vdev->v4l2_dev = &sdr->v4l2_dev;
1083 sdr->vdev->device_caps = V4L2_CAP_SDR_CAPTURE | V4L2_CAP_TUNER |
1084 V4L2_CAP_STREAMING | V4L2_CAP_READWRITE;
1085 video_set_drvdata(sdr->vdev, sdr);
1087 /* Register V4L2 SDR device */
1088 ret = video_register_device(sdr->vdev, VFL_TYPE_SDR, -1);
1089 if (ret) {
1090 video_device_release(sdr->vdev);
1091 sdr->vdev = NULL;
1092 dev_err(sdr->dev, "failed video_register_device (%d)\n", ret);
1095 return ret;
1098 static void rcar_drif_sdr_unregister(struct rcar_drif_sdr *sdr)
1100 video_unregister_device(sdr->vdev);
1101 sdr->vdev = NULL;
1104 /* Sub-device bound callback */
1105 static int rcar_drif_notify_bound(struct v4l2_async_notifier *notifier,
1106 struct v4l2_subdev *subdev,
1107 struct v4l2_async_subdev *asd)
1109 struct rcar_drif_sdr *sdr =
1110 container_of(notifier, struct rcar_drif_sdr, notifier);
1112 if (sdr->ep.asd.match.fwnode !=
1113 of_fwnode_handle(subdev->dev->of_node)) {
1114 rdrif_err(sdr, "subdev %s cannot bind\n", subdev->name);
1115 return -EINVAL;
1118 v4l2_set_subdev_hostdata(subdev, sdr);
1119 sdr->ep.subdev = subdev;
1120 rdrif_dbg(sdr, "bound asd %s\n", subdev->name);
1122 return 0;
1125 /* Sub-device unbind callback */
1126 static void rcar_drif_notify_unbind(struct v4l2_async_notifier *notifier,
1127 struct v4l2_subdev *subdev,
1128 struct v4l2_async_subdev *asd)
1130 struct rcar_drif_sdr *sdr =
1131 container_of(notifier, struct rcar_drif_sdr, notifier);
1133 if (sdr->ep.subdev != subdev) {
1134 rdrif_err(sdr, "subdev %s is not bound\n", subdev->name);
1135 return;
1138 /* Free ctrl handler if initialized */
1139 v4l2_ctrl_handler_free(&sdr->ctrl_hdl);
1140 sdr->v4l2_dev.ctrl_handler = NULL;
1141 sdr->ep.subdev = NULL;
1143 rcar_drif_sdr_unregister(sdr);
1144 rdrif_dbg(sdr, "unbind asd %s\n", subdev->name);
1147 /* Sub-device registered notification callback */
1148 static int rcar_drif_notify_complete(struct v4l2_async_notifier *notifier)
1150 struct rcar_drif_sdr *sdr =
1151 container_of(notifier, struct rcar_drif_sdr, notifier);
1152 int ret;
1155 * The subdev tested at this point uses 4 controls. Using 10 as a worst
1156 * case scenario hint. When less controls are needed there will be some
1157 * unused memory and when more controls are needed the framework uses
1158 * hash to manage controls within this number.
1160 ret = v4l2_ctrl_handler_init(&sdr->ctrl_hdl, 10);
1161 if (ret)
1162 return -ENOMEM;
1164 sdr->v4l2_dev.ctrl_handler = &sdr->ctrl_hdl;
1165 ret = v4l2_device_register_subdev_nodes(&sdr->v4l2_dev);
1166 if (ret) {
1167 rdrif_err(sdr, "failed: register subdev nodes ret %d\n", ret);
1168 goto error;
1171 ret = v4l2_ctrl_add_handler(&sdr->ctrl_hdl,
1172 sdr->ep.subdev->ctrl_handler, NULL, true);
1173 if (ret) {
1174 rdrif_err(sdr, "failed: ctrl add hdlr ret %d\n", ret);
1175 goto error;
1178 ret = rcar_drif_sdr_register(sdr);
1179 if (ret)
1180 goto error;
1182 return ret;
1184 error:
1185 v4l2_ctrl_handler_free(&sdr->ctrl_hdl);
1187 return ret;
1190 static const struct v4l2_async_notifier_operations rcar_drif_notify_ops = {
1191 .bound = rcar_drif_notify_bound,
1192 .unbind = rcar_drif_notify_unbind,
1193 .complete = rcar_drif_notify_complete,
1196 /* Read endpoint properties */
1197 static void rcar_drif_get_ep_properties(struct rcar_drif_sdr *sdr,
1198 struct fwnode_handle *fwnode)
1200 u32 val;
1202 /* Set the I2S defaults for SIRMDR1*/
1203 sdr->mdr1 = RCAR_DRIF_SIRMDR1_SYNCMD_LR | RCAR_DRIF_SIRMDR1_MSB_FIRST |
1204 RCAR_DRIF_SIRMDR1_DTDL_1 | RCAR_DRIF_SIRMDR1_SYNCDL_0;
1206 /* Parse sync polarity from endpoint */
1207 if (!fwnode_property_read_u32(fwnode, "sync-active", &val))
1208 sdr->mdr1 |= val ? RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH :
1209 RCAR_DRIF_SIRMDR1_SYNCAC_POL_LOW;
1210 else
1211 sdr->mdr1 |= RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH; /* default */
1213 dev_dbg(sdr->dev, "mdr1 0x%08x\n", sdr->mdr1);
1216 /* Parse sub-devs (tuner) to find a matching device */
1217 static int rcar_drif_parse_subdevs(struct rcar_drif_sdr *sdr)
1219 struct v4l2_async_notifier *notifier = &sdr->notifier;
1220 struct fwnode_handle *fwnode, *ep;
1221 int ret;
1223 v4l2_async_notifier_init(notifier);
1225 ep = fwnode_graph_get_next_endpoint(of_fwnode_handle(sdr->dev->of_node),
1226 NULL);
1227 if (!ep)
1228 return 0;
1230 fwnode = fwnode_graph_get_remote_port_parent(ep);
1231 if (!fwnode) {
1232 dev_warn(sdr->dev, "bad remote port parent\n");
1233 fwnode_handle_put(ep);
1234 return -EINVAL;
1237 sdr->ep.asd.match.fwnode = fwnode;
1238 sdr->ep.asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
1239 ret = v4l2_async_notifier_add_subdev(notifier, &sdr->ep.asd);
1240 if (ret) {
1241 fwnode_handle_put(fwnode);
1242 return ret;
1245 /* Get the endpoint properties */
1246 rcar_drif_get_ep_properties(sdr, ep);
1248 fwnode_handle_put(fwnode);
1249 fwnode_handle_put(ep);
1251 return 0;
1254 /* Check if the given device is the primary bond */
1255 static bool rcar_drif_primary_bond(struct platform_device *pdev)
1257 return of_property_read_bool(pdev->dev.of_node, "renesas,primary-bond");
1260 /* Check if both devices of the bond are enabled */
1261 static struct device_node *rcar_drif_bond_enabled(struct platform_device *p)
1263 struct device_node *np;
1265 np = of_parse_phandle(p->dev.of_node, "renesas,bonding", 0);
1266 if (np && of_device_is_available(np))
1267 return np;
1269 return NULL;
1272 /* Check if the bonded device is probed */
1273 static int rcar_drif_bond_available(struct rcar_drif_sdr *sdr,
1274 struct device_node *np)
1276 struct platform_device *pdev;
1277 struct rcar_drif *ch;
1278 int ret = 0;
1280 pdev = of_find_device_by_node(np);
1281 if (!pdev) {
1282 dev_err(sdr->dev, "failed to get bonded device from node\n");
1283 return -ENODEV;
1286 device_lock(&pdev->dev);
1287 ch = platform_get_drvdata(pdev);
1288 if (ch) {
1289 /* Update sdr data in the bonded device */
1290 ch->sdr = sdr;
1292 /* Update sdr with bonded device data */
1293 sdr->ch[ch->num] = ch;
1294 sdr->hw_ch_mask |= BIT(ch->num);
1295 } else {
1296 /* Defer */
1297 dev_info(sdr->dev, "defer probe\n");
1298 ret = -EPROBE_DEFER;
1300 device_unlock(&pdev->dev);
1302 put_device(&pdev->dev);
1304 return ret;
1307 /* V4L2 SDR device probe */
1308 static int rcar_drif_sdr_probe(struct rcar_drif_sdr *sdr)
1310 int ret;
1312 /* Validate any supported format for enabled channels */
1313 ret = rcar_drif_set_default_format(sdr);
1314 if (ret) {
1315 dev_err(sdr->dev, "failed to set default format\n");
1316 return ret;
1319 /* Set defaults */
1320 sdr->hwbuf_size = RCAR_DRIF_DEFAULT_HWBUF_SIZE;
1322 mutex_init(&sdr->v4l2_mutex);
1323 mutex_init(&sdr->vb_queue_mutex);
1324 spin_lock_init(&sdr->queued_bufs_lock);
1325 spin_lock_init(&sdr->dma_lock);
1326 INIT_LIST_HEAD(&sdr->queued_bufs);
1328 /* Init videobuf2 queue structure */
1329 sdr->vb_queue.type = V4L2_BUF_TYPE_SDR_CAPTURE;
1330 sdr->vb_queue.io_modes = VB2_READ | VB2_MMAP | VB2_DMABUF;
1331 sdr->vb_queue.drv_priv = sdr;
1332 sdr->vb_queue.buf_struct_size = sizeof(struct rcar_drif_frame_buf);
1333 sdr->vb_queue.ops = &rcar_drif_vb2_ops;
1334 sdr->vb_queue.mem_ops = &vb2_vmalloc_memops;
1335 sdr->vb_queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1337 /* Init videobuf2 queue */
1338 ret = vb2_queue_init(&sdr->vb_queue);
1339 if (ret) {
1340 dev_err(sdr->dev, "failed: vb2_queue_init ret %d\n", ret);
1341 return ret;
1344 /* Register the v4l2_device */
1345 ret = v4l2_device_register(sdr->dev, &sdr->v4l2_dev);
1346 if (ret) {
1347 dev_err(sdr->dev, "failed: v4l2_device_register ret %d\n", ret);
1348 return ret;
1352 * Parse subdevs after v4l2_device_register because if the subdev
1353 * is already probed, bound and complete will be called immediately
1355 ret = rcar_drif_parse_subdevs(sdr);
1356 if (ret)
1357 goto error;
1359 sdr->notifier.ops = &rcar_drif_notify_ops;
1361 /* Register notifier */
1362 ret = v4l2_async_notifier_register(&sdr->v4l2_dev, &sdr->notifier);
1363 if (ret < 0) {
1364 dev_err(sdr->dev, "failed: notifier register ret %d\n", ret);
1365 goto cleanup;
1368 return ret;
1370 cleanup:
1371 v4l2_async_notifier_cleanup(&sdr->notifier);
1372 error:
1373 v4l2_device_unregister(&sdr->v4l2_dev);
1375 return ret;
1378 /* V4L2 SDR device remove */
1379 static void rcar_drif_sdr_remove(struct rcar_drif_sdr *sdr)
1381 v4l2_async_notifier_unregister(&sdr->notifier);
1382 v4l2_async_notifier_cleanup(&sdr->notifier);
1383 v4l2_device_unregister(&sdr->v4l2_dev);
1386 /* DRIF channel probe */
1387 static int rcar_drif_probe(struct platform_device *pdev)
1389 struct rcar_drif_sdr *sdr;
1390 struct device_node *np;
1391 struct rcar_drif *ch;
1392 struct resource *res;
1393 int ret;
1395 /* Reserve memory for enabled channel */
1396 ch = devm_kzalloc(&pdev->dev, sizeof(*ch), GFP_KERNEL);
1397 if (!ch)
1398 return -ENOMEM;
1400 ch->pdev = pdev;
1402 /* Module clock */
1403 ch->clk = devm_clk_get(&pdev->dev, "fck");
1404 if (IS_ERR(ch->clk)) {
1405 ret = PTR_ERR(ch->clk);
1406 dev_err(&pdev->dev, "clk get failed (%d)\n", ret);
1407 return ret;
1410 /* Register map */
1411 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1412 ch->base = devm_ioremap_resource(&pdev->dev, res);
1413 if (IS_ERR(ch->base))
1414 return PTR_ERR(ch->base);
1416 ch->start = res->start;
1417 platform_set_drvdata(pdev, ch);
1419 /* Check if both channels of the bond are enabled */
1420 np = rcar_drif_bond_enabled(pdev);
1421 if (np) {
1422 /* Check if current channel acting as primary-bond */
1423 if (!rcar_drif_primary_bond(pdev)) {
1424 ch->num = 1; /* Primary bond is channel 0 always */
1425 of_node_put(np);
1426 return 0;
1430 /* Reserve memory for SDR structure */
1431 sdr = devm_kzalloc(&pdev->dev, sizeof(*sdr), GFP_KERNEL);
1432 if (!sdr) {
1433 of_node_put(np);
1434 return -ENOMEM;
1436 ch->sdr = sdr;
1437 sdr->dev = &pdev->dev;
1439 /* Establish links between SDR and channel(s) */
1440 sdr->ch[ch->num] = ch;
1441 sdr->hw_ch_mask = BIT(ch->num);
1442 if (np) {
1443 /* Check if bonded device is ready */
1444 ret = rcar_drif_bond_available(sdr, np);
1445 of_node_put(np);
1446 if (ret)
1447 return ret;
1449 sdr->num_hw_ch = hweight_long(sdr->hw_ch_mask);
1451 return rcar_drif_sdr_probe(sdr);
1454 /* DRIF channel remove */
1455 static int rcar_drif_remove(struct platform_device *pdev)
1457 struct rcar_drif *ch = platform_get_drvdata(pdev);
1458 struct rcar_drif_sdr *sdr = ch->sdr;
1460 /* Channel 0 will be the SDR instance */
1461 if (ch->num)
1462 return 0;
1464 /* SDR instance */
1465 rcar_drif_sdr_remove(sdr);
1467 return 0;
1470 /* FIXME: Implement suspend/resume support */
1471 static int __maybe_unused rcar_drif_suspend(struct device *dev)
1473 return 0;
1476 static int __maybe_unused rcar_drif_resume(struct device *dev)
1478 return 0;
1481 static SIMPLE_DEV_PM_OPS(rcar_drif_pm_ops, rcar_drif_suspend,
1482 rcar_drif_resume);
1484 static const struct of_device_id rcar_drif_of_table[] = {
1485 { .compatible = "renesas,rcar-gen3-drif" },
1488 MODULE_DEVICE_TABLE(of, rcar_drif_of_table);
1490 #define RCAR_DRIF_DRV_NAME "rcar_drif"
1491 static struct platform_driver rcar_drif_driver = {
1492 .driver = {
1493 .name = RCAR_DRIF_DRV_NAME,
1494 .of_match_table = of_match_ptr(rcar_drif_of_table),
1495 .pm = &rcar_drif_pm_ops,
1497 .probe = rcar_drif_probe,
1498 .remove = rcar_drif_remove,
1501 module_platform_driver(rcar_drif_driver);
1503 MODULE_DESCRIPTION("Renesas R-Car Gen3 DRIF driver");
1504 MODULE_ALIAS("platform:" RCAR_DRIF_DRV_NAME);
1505 MODULE_LICENSE("GPL");
1506 MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");