drivers/net/ethernet/agere/et131x.h

   1 /* Copyright © 2005 Agere Systems Inc.
   2  * All rights reserved.
   3  *   http://www.agere.com
   4  *
   5  * SOFTWARE LICENSE
   6  *
   7  * This software is provided subject to the following terms and conditions,
   8  * which you should read carefully before using the software.  Using this
   9  * software indicates your acceptance of these terms and conditions.  If you do
  10  * not agree with these terms and conditions, do not use the software.
  11  *
  12  * Copyright © 2005 Agere Systems Inc.
  13  * All rights reserved.
  14  *
  15  * Redistribution and use in source or binary forms, with or without
  16  * modifications, are permitted provided that the following conditions are met:
  17  *
  18  * . Redistributions of source code must retain the above copyright notice, this
  19  *    list of conditions and the following Disclaimer as comments in the code as
  20  *    well as in the documentation and/or other materials provided with the
  21  *    distribution.
  22  *
  23  * . Redistributions in binary form must reproduce the above copyright notice,
  24  *    this list of conditions and the following Disclaimer in the documentation
  25  *    and/or other materials provided with the distribution.
  26  *
  27  * . Neither the name of Agere Systems Inc. nor the names of the contributors
  28  *    may be used to endorse or promote products derived from this software
  29  *    without specific prior written permission.
  30  *
  31  * Disclaimer
  32  *
  33  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
  34  * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
  35  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
  36  * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
  37  * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
  38  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  39  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  40  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  41  * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
  42  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  43  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  44  * DAMAGE.
  45  *
  46  */
  47
  48 #define DRIVER_NAME "et131x"
  49
  50 /* EEPROM registers */
  51
  52 /* LBCIF Register Groups (addressed via 32-bit offsets) */
  53 #define LBCIF_DWORD0_GROUP       0xAC
  54 #define LBCIF_DWORD1_GROUP       0xB0
  55
  56 /* LBCIF Registers (addressed via 8-bit offsets) */
  57 #define LBCIF_ADDRESS_REGISTER   0xAC
  58 #define LBCIF_DATA_REGISTER      0xB0
  59 #define LBCIF_CONTROL_REGISTER   0xB1
  60 #define LBCIF_STATUS_REGISTER    0xB2
  61
  62 /* LBCIF Control Register Bits */
  63 #define LBCIF_CONTROL_SEQUENTIAL_READ   0x01
  64 #define LBCIF_CONTROL_PAGE_WRITE        0x02
  65 #define LBCIF_CONTROL_EEPROM_RELOAD     0x08
  66 #define LBCIF_CONTROL_TWO_BYTE_ADDR     0x20
  67 #define LBCIF_CONTROL_I2C_WRITE         0x40
  68 #define LBCIF_CONTROL_LBCIF_ENABLE      0x80
  69
  70 /* LBCIF Status Register Bits */
  71 #define LBCIF_STATUS_PHY_QUEUE_AVAIL    0x01
  72 #define LBCIF_STATUS_I2C_IDLE           0x02
  73 #define LBCIF_STATUS_ACK_ERROR          0x04
  74 #define LBCIF_STATUS_GENERAL_ERROR      0x08
  75 #define LBCIF_STATUS_CHECKSUM_ERROR     0x40
  76 #define LBCIF_STATUS_EEPROM_PRESENT     0x80
  77
  78 /* START OF GLOBAL REGISTER ADDRESS MAP */
  79 /* 10bit registers
  80  *
  81  * Tx queue start address reg in global address map at address 0x0000
  82  * tx queue end address reg in global address map at address 0x0004
  83  * rx queue start address reg in global address map at address 0x0008
  84  * rx queue end address reg in global address map at address 0x000C
  85  */
  86
  87 /* structure for power management control status reg in global address map
  88  * located at address 0x0010
  89  *      jagcore_rx_rdy  bit 9
  90  *      jagcore_tx_rdy  bit 8
  91  *      phy_lped_en     bit 7
  92  *      phy_sw_coma     bit 6
  93  *      rxclk_gate      bit 5
  94  *      txclk_gate      bit 4
  95  *      sysclk_gate     bit 3
  96  *      jagcore_rx_en   bit 2
  97  *      jagcore_tx_en   bit 1
  98  *      gigephy_en      bit 0
  99  */
 100 #define ET_PM_PHY_SW_COMA               0x40
 101 #define ET_PMCSR_INIT                   0x38
 102
 103 /* Interrupt status reg at address 0x0018
 104  */
 105 #define ET_INTR_TXDMA_ISR       0x00000008
 106 #define ET_INTR_TXDMA_ERR       0x00000010
 107 #define ET_INTR_RXDMA_XFR_DONE  0x00000020
 108 #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
 109 #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
 110 #define ET_INTR_RXDMA_STAT_LOW  0x00000100
 111 #define ET_INTR_RXDMA_ERR       0x00000200
 112 #define ET_INTR_WATCHDOG        0x00004000
 113 #define ET_INTR_WOL             0x00008000
 114 #define ET_INTR_PHY             0x00010000
 115 #define ET_INTR_TXMAC           0x00020000
 116 #define ET_INTR_RXMAC           0x00040000
 117 #define ET_INTR_MAC_STAT        0x00080000
 118 #define ET_INTR_SLV_TIMEOUT     0x00100000
 119
 120 /* Interrupt mask register at address 0x001C
 121  * Interrupt alias clear mask reg at address 0x0020
 122  * Interrupt status alias reg at address 0x0024
 123  *
 124  * Same masks as above
 125  */
 126
 127 /* Software reset reg at address 0x0028
 128  * 0:   txdma_sw_reset
 129  * 1:   rxdma_sw_reset
 130  * 2:   txmac_sw_reset
 131  * 3:   rxmac_sw_reset
 132  * 4:   mac_sw_reset
 133  * 5:   mac_stat_sw_reset
 134  * 6:   mmc_sw_reset
 135  *31:   selfclr_disable
 136  */
 137 #define ET_RESET_ALL    0x007F
 138
 139 /* SLV Timer reg at address 0x002C (low 24 bits)
 140  */
 141
 142 /* MSI Configuration reg at address 0x0030
 143  */
 144 #define ET_MSI_VECTOR   0x0000001F
 145 #define ET_MSI_TC       0x00070000
 146
 147 /* Loopback reg located at address 0x0034
 148  */
 149 #define ET_LOOP_MAC     0x00000001
 150 #define ET_LOOP_DMA     0x00000002
 151
 152 /* GLOBAL Module of JAGCore Address Mapping
 153  * Located at address 0x0000
 154  */
 155 struct global_regs {                            /* Location: */
 156         u32 txq_start_addr;                     /*  0x0000 */
 157         u32 txq_end_addr;                       /*  0x0004 */
 158         u32 rxq_start_addr;                     /*  0x0008 */
 159         u32 rxq_end_addr;                       /*  0x000C */
 160         u32 pm_csr;                             /*  0x0010 */
 161         u32 unused;                             /*  0x0014 */
 162         u32 int_status;                         /*  0x0018 */
 163         u32 int_mask;                           /*  0x001C */
 164         u32 int_alias_clr_en;                   /*  0x0020 */
 165         u32 int_status_alias;                   /*  0x0024 */
 166         u32 sw_reset;                           /*  0x0028 */
 167         u32 slv_timer;                          /*  0x002C */
 168         u32 msi_config;                         /*  0x0030 */
 169         u32 loopback;                           /*  0x0034 */
 170         u32 watchdog_timer;                     /*  0x0038 */
 171 };
 172
 173 /* START OF TXDMA REGISTER ADDRESS MAP */
 174 /* txdma control status reg at address 0x1000
 175  */
 176 #define ET_TXDMA_CSR_HALT       0x00000001
 177 #define ET_TXDMA_DROP_TLP       0x00000002
 178 #define ET_TXDMA_CACHE_THRS     0x000000F0
 179 #define ET_TXDMA_CACHE_SHIFT    4
 180 #define ET_TXDMA_SNGL_EPKT      0x00000100
 181 #define ET_TXDMA_CLASS          0x00001E00
 182
 183 /* structure for txdma packet ring base address hi reg in txdma address map
 184  * located at address 0x1004
 185  * Defined earlier (u32)
 186  */
 187
 188 /* structure for txdma packet ring base address low reg in txdma address map
 189  * located at address 0x1008
 190  * Defined earlier (u32)
 191  */
 192
 193 /* structure for txdma packet ring number of descriptor reg in txdma address
 194  * map.  Located at address 0x100C
 195  *
 196  * 31-10: unused
 197  * 9-0: pr ndes
 198  */
 199 #define ET_DMA12_MASK           0x0FFF  /* 12 bit mask for DMA12W types */
 200 #define ET_DMA12_WRAP           0x1000
 201 #define ET_DMA10_MASK           0x03FF  /* 10 bit mask for DMA10W types */
 202 #define ET_DMA10_WRAP           0x0400
 203 #define ET_DMA4_MASK            0x000F  /* 4 bit mask for DMA4W types */
 204 #define ET_DMA4_WRAP            0x0010
 205
 206 #define INDEX12(x)      ((x) & ET_DMA12_MASK)
 207 #define INDEX10(x)      ((x) & ET_DMA10_MASK)
 208 #define INDEX4(x)       ((x) & ET_DMA4_MASK)
 209
 210 /* 10bit DMA with wrap
 211  * txdma tx queue write address reg in txdma address map at 0x1010
 212  * txdma tx queue write address external reg in txdma address map at 0x1014
 213  * txdma tx queue read address reg in txdma address map at 0x1018
 214  *
 215  * u32
 216  * txdma status writeback address hi reg in txdma address map at0x101C
 217  * txdma status writeback address lo reg in txdma address map at 0x1020
 218  *
 219  * 10bit DMA with wrap
 220  * txdma service request reg in txdma address map at 0x1024
 221  * structure for txdma service complete reg in txdma address map at 0x1028
 222  *
 223  * 4bit DMA with wrap
 224  * txdma tx descriptor cache read index reg in txdma address map at 0x102C
 225  * txdma tx descriptor cache write index reg in txdma address map at 0x1030
 226  *
 227  * txdma error reg in txdma address map at address 0x1034
 228  * 0: PyldResend
 229  * 1: PyldRewind
 230  * 4: DescrResend
 231  * 5: DescrRewind
 232  * 8: WrbkResend
 233  * 9: WrbkRewind
 234  */
 235
 236 /* Tx DMA Module of JAGCore Address Mapping
 237  * Located at address 0x1000
 238  */
 239 struct txdma_regs {                     /* Location: */
 240         u32 csr;                        /*  0x1000 */
 241         u32 pr_base_hi;                 /*  0x1004 */
 242         u32 pr_base_lo;                 /*  0x1008 */
 243         u32 pr_num_des;                 /*  0x100C */
 244         u32 txq_wr_addr;                /*  0x1010 */
 245         u32 txq_wr_addr_ext;            /*  0x1014 */
 246         u32 txq_rd_addr;                /*  0x1018 */
 247         u32 dma_wb_base_hi;             /*  0x101C */
 248         u32 dma_wb_base_lo;             /*  0x1020 */
 249         u32 service_request;            /*  0x1024 */
 250         u32 service_complete;           /*  0x1028 */
 251         u32 cache_rd_index;             /*  0x102C */
 252         u32 cache_wr_index;             /*  0x1030 */
 253         u32 tx_dma_error;               /*  0x1034 */
 254         u32 desc_abort_cnt;             /*  0x1038 */
 255         u32 payload_abort_cnt;          /*  0x103c */
 256         u32 writeback_abort_cnt;        /*  0x1040 */
 257         u32 desc_timeout_cnt;           /*  0x1044 */
 258         u32 payload_timeout_cnt;        /*  0x1048 */
 259         u32 writeback_timeout_cnt;      /*  0x104c */
 260         u32 desc_error_cnt;             /*  0x1050 */
 261         u32 payload_error_cnt;          /*  0x1054 */
 262         u32 writeback_error_cnt;        /*  0x1058 */
 263         u32 dropped_tlp_cnt;            /*  0x105c */
 264         u32 new_service_complete;       /*  0x1060 */
 265         u32 ethernet_packet_cnt;        /*  0x1064 */
 266 };
 267
 268 /* END OF TXDMA REGISTER ADDRESS MAP */
 269
 270 /* START OF RXDMA REGISTER ADDRESS MAP */
 271 /* structure for control status reg in rxdma address map
 272  * Located at address 0x2000
 273  *
 274  * CSR
 275  * 0: halt
 276  * 1-3: tc
 277  * 4: fbr_big_endian
 278  * 5: psr_big_endian
 279  * 6: pkt_big_endian
 280  * 7: dma_big_endian
 281  * 8-9: fbr0_size
 282  * 10: fbr0_enable
 283  * 11-12: fbr1_size
 284  * 13: fbr1_enable
 285  * 14: unused
 286  * 15: pkt_drop_disable
 287  * 16: pkt_done_flush
 288  * 17: halt_status
 289  * 18-31: unused
 290  */
 291 #define ET_RXDMA_CSR_HALT               0x0001
 292 #define ET_RXDMA_CSR_FBR0_SIZE_LO       0x0100
 293 #define ET_RXDMA_CSR_FBR0_SIZE_HI       0x0200
 294 #define ET_RXDMA_CSR_FBR0_ENABLE        0x0400
 295 #define ET_RXDMA_CSR_FBR1_SIZE_LO       0x0800
 296 #define ET_RXDMA_CSR_FBR1_SIZE_HI       0x1000
 297 #define ET_RXDMA_CSR_FBR1_ENABLE        0x2000
 298 #define ET_RXDMA_CSR_HALT_STATUS        0x00020000
 299
 300 /* structure for dma writeback lo reg in rxdma address map
 301  * located at address 0x2004
 302  * Defined earlier (u32)
 303  */
 304
 305 /* structure for dma writeback hi reg in rxdma address map
 306  * located at address 0x2008
 307  * Defined earlier (u32)
 308  */
 309
 310 /* structure for number of packets done reg in rxdma address map
 311  * located at address 0x200C
 312  *
 313  * 31-8: unused
 314  * 7-0: num done
 315  */
 316
 317 /* structure for max packet time reg in rxdma address map
 318  * located at address 0x2010
 319  *
 320  * 31-18: unused
 321  * 17-0: time done
 322  */
 323
 324 /* structure for rx queue read address reg in rxdma address map
 325  * located at address 0x2014
 326  * Defined earlier (u32)
 327  */
 328
 329 /* structure for rx queue read address external reg in rxdma address map
 330  * located at address 0x2018
 331  * Defined earlier (u32)
 332  */
 333
 334 /* structure for rx queue write address reg in rxdma address map
 335  * located at address 0x201C
 336  * Defined earlier (u32)
 337  */
 338
 339 /* structure for packet status ring base address lo reg in rxdma address map
 340  * located at address 0x2020
 341  * Defined earlier (u32)
 342  */
 343
 344 /* structure for packet status ring base address hi reg in rxdma address map
 345  * located at address 0x2024
 346  * Defined earlier (u32)
 347  */
 348
 349 /* structure for packet status ring number of descriptors reg in rxdma address
 350  * map.  Located at address 0x2028
 351  *
 352  * 31-12: unused
 353  * 11-0: psr ndes
 354  */
 355 #define ET_RXDMA_PSR_NUM_DES_MASK       0xFFF
 356
 357 /* structure for packet status ring available offset reg in rxdma address map
 358  * located at address 0x202C
 359  *
 360  * 31-13: unused
 361  * 12: psr avail wrap
 362  * 11-0: psr avail
 363  */
 364
 365 /* structure for packet status ring full offset reg in rxdma address map
 366  * located at address 0x2030
 367  *
 368  * 31-13: unused
 369  * 12: psr full wrap
 370  * 11-0: psr full
 371  */
 372
 373 /* structure for packet status ring access index reg in rxdma address map
 374  * located at address 0x2034
 375  *
 376  * 31-5: unused
 377  * 4-0: psr_ai
 378  */
 379
 380 /* structure for packet status ring minimum descriptors reg in rxdma address
 381  * map.  Located at address 0x2038
 382  *
 383  * 31-12: unused
 384  * 11-0: psr_min
 385  */
 386
 387 /* structure for free buffer ring base lo address reg in rxdma address map
 388  * located at address 0x203C
 389  * Defined earlier (u32)
 390  */
 391
 392 /* structure for free buffer ring base hi address reg in rxdma address map
 393  * located at address 0x2040
 394  * Defined earlier (u32)
 395  */
 396
 397 /* structure for free buffer ring number of descriptors reg in rxdma address
 398  * map.  Located at address 0x2044
 399  *
 400  * 31-10: unused
 401  * 9-0: fbr ndesc
 402  */
 403
 404 /* structure for free buffer ring 0 available offset reg in rxdma address map
 405  * located at address 0x2048
 406  * Defined earlier (u32)
 407  */
 408
 409 /* structure for free buffer ring 0 full offset reg in rxdma address map
 410  * located at address 0x204C
 411  * Defined earlier (u32)
 412  */
 413
 414 /* structure for free buffer cache 0 full offset reg in rxdma address map
 415  * located at address 0x2050
 416  *
 417  * 31-5: unused
 418  * 4-0: fbc rdi
 419  */
 420
 421 /* structure for free buffer ring 0 minimum descriptor reg in rxdma address map
 422  * located at address 0x2054
 423  *
 424  * 31-10: unused
 425  * 9-0: fbr min
 426  */
 427
 428 /* structure for free buffer ring 1 base address lo reg in rxdma address map
 429  * located at address 0x2058 - 0x205C
 430  * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
 431  */
 432
 433 /* structure for free buffer ring 1 number of descriptors reg in rxdma address
 434  * map.  Located at address 0x2060
 435  * Defined earlier (RXDMA_FBR_NUM_DES_t)
 436  */
 437
 438 /* structure for free buffer ring 1 available offset reg in rxdma address map
 439  * located at address 0x2064
 440  * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
 441  */
 442
 443 /* structure for free buffer ring 1 full offset reg in rxdma address map
 444  * located at address 0x2068
 445  * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
 446  */
 447
 448 /* structure for free buffer cache 1 read index reg in rxdma address map
 449  * located at address 0x206C
 450  * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
 451  */
 452
 453 /* structure for free buffer ring 1 minimum descriptor reg in rxdma address map
 454  * located at address 0x2070
 455  * Defined Earlier (RXDMA_FBR_MIN_DES_t)
 456  */
 457
 458 /* Rx DMA Module of JAGCore Address Mapping
 459  * Located at address 0x2000
 460  */
 461 struct rxdma_regs {                                     /* Location: */
 462         u32 csr;                                        /*  0x2000 */
 463         u32 dma_wb_base_lo;                             /*  0x2004 */
 464         u32 dma_wb_base_hi;                             /*  0x2008 */
 465         u32 num_pkt_done;                               /*  0x200C */
 466         u32 max_pkt_time;                               /*  0x2010 */
 467         u32 rxq_rd_addr;                                /*  0x2014 */
 468         u32 rxq_rd_addr_ext;                            /*  0x2018 */
 469         u32 rxq_wr_addr;                                /*  0x201C */
 470         u32 psr_base_lo;                                /*  0x2020 */
 471         u32 psr_base_hi;                                /*  0x2024 */
 472         u32 psr_num_des;                                /*  0x2028 */
 473         u32 psr_avail_offset;                           /*  0x202C */
 474         u32 psr_full_offset;                            /*  0x2030 */
 475         u32 psr_access_index;                           /*  0x2034 */
 476         u32 psr_min_des;                                /*  0x2038 */
 477         u32 fbr0_base_lo;                               /*  0x203C */
 478         u32 fbr0_base_hi;                               /*  0x2040 */
 479         u32 fbr0_num_des;                               /*  0x2044 */
 480         u32 fbr0_avail_offset;                          /*  0x2048 */
 481         u32 fbr0_full_offset;                           /*  0x204C */
 482         u32 fbr0_rd_index;                              /*  0x2050 */
 483         u32 fbr0_min_des;                               /*  0x2054 */
 484         u32 fbr1_base_lo;                               /*  0x2058 */
 485         u32 fbr1_base_hi;                               /*  0x205C */
 486         u32 fbr1_num_des;                               /*  0x2060 */
 487         u32 fbr1_avail_offset;                          /*  0x2064 */
 488         u32 fbr1_full_offset;                           /*  0x2068 */
 489         u32 fbr1_rd_index;                              /*  0x206C */
 490         u32 fbr1_min_des;                               /*  0x2070 */
 491 };
 492
 493 /* END OF RXDMA REGISTER ADDRESS MAP */
 494
 495 /* START OF TXMAC REGISTER ADDRESS MAP */
 496 /* structure for control reg in txmac address map
 497  * located at address 0x3000
 498  *
 499  * bits
 500  * 31-8: unused
 501  * 7: cklseg_disable
 502  * 6: ckbcnt_disable
 503  * 5: cksegnum
 504  * 4: async_disable
 505  * 3: fc_disable
 506  * 2: mcif_disable
 507  * 1: mif_disable
 508  * 0: txmac_en
 509  */
 510 #define ET_TX_CTRL_FC_DISABLE   0x0008
 511 #define ET_TX_CTRL_TXMAC_ENABLE 0x0001
 512
 513 /* structure for shadow pointer reg in txmac address map
 514  * located at address 0x3004
 515  * 31-27: reserved
 516  * 26-16: txq rd ptr
 517  * 15-11: reserved
 518  * 10-0: txq wr ptr
 519  */
 520
 521 /* structure for error count reg in txmac address map
 522  * located at address 0x3008
 523  *
 524  * 31-12: unused
 525  * 11-8: reserved
 526  * 7-4: txq_underrun
 527  * 3-0: fifo_underrun
 528  */
 529
 530 /* structure for max fill reg in txmac address map
 531  * located at address 0x300C
 532  * 31-12: unused
 533  * 11-0: max fill
 534  */
 535
 536 /* structure for cf parameter reg in txmac address map
 537  * located at address 0x3010
 538  * 31-16: cfep
 539  * 15-0: cfpt
 540  */
 541
 542 /* structure for tx test reg in txmac address map
 543  * located at address 0x3014
 544  * 31-17: unused
 545  * 16: reserved
 546  * 15: txtest_en
 547  * 14-11: unused
 548  * 10-0: txq test pointer
 549  */
 550
 551 /* structure for error reg in txmac address map
 552  * located at address 0x3018
 553  *
 554  * 31-9: unused
 555  * 8: fifo_underrun
 556  * 7-6: unused
 557  * 5: ctrl2_err
 558  * 4: txq_underrun
 559  * 3: bcnt_err
 560  * 2: lseg_err
 561  * 1: segnum_err
 562  * 0: seg0_err
 563  */
 564
 565 /* structure for error interrupt reg in txmac address map
 566  * located at address 0x301C
 567  *
 568  * 31-9: unused
 569  * 8: fifo_underrun
 570  * 7-6: unused
 571  * 5: ctrl2_err
 572  * 4: txq_underrun
 573  * 3: bcnt_err
 574  * 2: lseg_err
 575  * 1: segnum_err
 576  * 0: seg0_err
 577  */
 578
 579 /* structure for error interrupt reg in txmac address map
 580  * located at address 0x3020
 581  *
 582  * 31-2: unused
 583  * 1: bp_req
 584  * 0: bp_xonxoff
 585  */
 586
 587 /* Tx MAC Module of JAGCore Address Mapping
 588  */
 589 struct txmac_regs {                     /* Location: */
 590         u32 ctl;                        /*  0x3000 */
 591         u32 shadow_ptr;                 /*  0x3004 */
 592         u32 err_cnt;                    /*  0x3008 */
 593         u32 max_fill;                   /*  0x300C */
 594         u32 cf_param;                   /*  0x3010 */
 595         u32 tx_test;                    /*  0x3014 */
 596         u32 err;                        /*  0x3018 */
 597         u32 err_int;                    /*  0x301C */
 598         u32 bp_ctrl;                    /*  0x3020 */
 599 };
 600
 601 /* END OF TXMAC REGISTER ADDRESS MAP */
 602
 603 /* START OF RXMAC REGISTER ADDRESS MAP */
 604
 605 /* structure for rxmac control reg in rxmac address map
 606  * located at address 0x4000
 607  *
 608  * 31-7: reserved
 609  * 6: rxmac_int_disable
 610  * 5: async_disable
 611  * 4: mif_disable
 612  * 3: wol_disable
 613  * 2: pkt_filter_disable
 614  * 1: mcif_disable
 615  * 0: rxmac_en
 616  */
 617 #define ET_RX_CTRL_WOL_DISABLE  0x0008
 618 #define ET_RX_CTRL_RXMAC_ENABLE 0x0001
 619
 620 /* structure for Wake On Lan Control and CRC 0 reg in rxmac address map
 621  * located at address 0x4004
 622  * 31-16: crc
 623  * 15-12: reserved
 624  * 11: ignore_pp
 625  * 10: ignore_mp
 626  * 9: clr_intr
 627  * 8: ignore_link_chg
 628  * 7: ignore_uni
 629  * 6: ignore_multi
 630  * 5: ignore_broad
 631  * 4-0: valid_crc 4-0
 632  */
 633
 634 /* structure for CRC 1 and CRC 2 reg in rxmac address map
 635  * located at address 0x4008
 636  *
 637  * 31-16: crc2
 638  * 15-0: crc1
 639  */
 640
 641 /* structure for CRC 3 and CRC 4 reg in rxmac address map
 642  * located at address 0x400C
 643  *
 644  * 31-16: crc4
 645  * 15-0: crc3
 646  */
 647
 648 /* structure for Wake On Lan Source Address Lo reg in rxmac address map
 649  * located at address 0x4010
 650  *
 651  * 31-24: sa3
 652  * 23-16: sa4
 653  * 15-8: sa5
 654  * 7-0: sa6
 655  */
 656 #define ET_RX_WOL_LO_SA3_SHIFT 24
 657 #define ET_RX_WOL_LO_SA4_SHIFT 16
 658 #define ET_RX_WOL_LO_SA5_SHIFT 8
 659
 660 /* structure for Wake On Lan Source Address Hi reg in rxmac address map
 661  * located at address 0x4014
 662  *
 663  * 31-16: reserved
 664  * 15-8: sa1
 665  * 7-0: sa2
 666  */
 667 #define ET_RX_WOL_HI_SA1_SHIFT 8
 668
 669 /* structure for Wake On Lan mask reg in rxmac address map
 670  * located at address 0x4018 - 0x4064
 671  * Defined earlier (u32)
 672  */
 673
 674 /* structure for Unicast Packet Filter Address 1 reg in rxmac address map
 675  * located at address 0x4068
 676  *
 677  * 31-24: addr1_3
 678  * 23-16: addr1_4
 679  * 15-8: addr1_5
 680  * 7-0: addr1_6
 681  */
 682 #define ET_RX_UNI_PF_ADDR1_3_SHIFT 24
 683 #define ET_RX_UNI_PF_ADDR1_4_SHIFT 16
 684 #define ET_RX_UNI_PF_ADDR1_5_SHIFT 8
 685
 686 /* structure for Unicast Packet Filter Address 2 reg in rxmac address map
 687  * located at address 0x406C
 688  *
 689  * 31-24: addr2_3
 690  * 23-16: addr2_4
 691  * 15-8: addr2_5
 692  * 7-0: addr2_6
 693  */
 694 #define ET_RX_UNI_PF_ADDR2_3_SHIFT 24
 695 #define ET_RX_UNI_PF_ADDR2_4_SHIFT 16
 696 #define ET_RX_UNI_PF_ADDR2_5_SHIFT 8
 697
 698 /* structure for Unicast Packet Filter Address 1 & 2 reg in rxmac address map
 699  * located at address 0x4070
 700  *
 701  * 31-24: addr2_1
 702  * 23-16: addr2_2
 703  * 15-8: addr1_1
 704  * 7-0: addr1_2
 705  */
 706 #define ET_RX_UNI_PF_ADDR2_1_SHIFT 24
 707 #define ET_RX_UNI_PF_ADDR2_2_SHIFT 16
 708 #define ET_RX_UNI_PF_ADDR1_1_SHIFT 8
 709
 710 /* structure for Multicast Hash reg in rxmac address map
 711  * located at address 0x4074 - 0x4080
 712  * Defined earlier (u32)
 713  */
 714
 715 /* structure for Packet Filter Control reg in rxmac address map
 716  * located at address 0x4084
 717  *
 718  * 31-23: unused
 719  * 22-16: min_pkt_size
 720  * 15-4: unused
 721  * 3: filter_frag_en
 722  * 2: filter_uni_en
 723  * 1: filter_multi_en
 724  * 0: filter_broad_en
 725  */
 726 #define ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT           16
 727 #define ET_RX_PFCTRL_FRAG_FILTER_ENABLE         0x0008
 728 #define ET_RX_PFCTRL_UNICST_FILTER_ENABLE       0x0004
 729 #define ET_RX_PFCTRL_MLTCST_FILTER_ENABLE       0x0002
 730 #define ET_RX_PFCTRL_BRDCST_FILTER_ENABLE       0x0001
 731
 732 /* structure for Memory Controller Interface Control Max Segment reg in rxmac
 733  * address map.  Located at address 0x4088
 734  *
 735  * 31-10: reserved
 736  * 9-2: max_size
 737  * 1: fc_en
 738  * 0: seg_en
 739  */
 740 #define ET_RX_MCIF_CTRL_MAX_SEG_SIZE_SHIFT      2
 741 #define ET_RX_MCIF_CTRL_MAX_SEG_FC_ENABLE       0x0002
 742 #define ET_RX_MCIF_CTRL_MAX_SEG_ENABLE          0x0001
 743
 744 /* structure for Memory Controller Interface Water Mark reg in rxmac address
 745  * map.  Located at address 0x408C
 746  *
 747  * 31-26: unused
 748  * 25-16: mark_hi
 749  * 15-10: unused
 750  * 9-0: mark_lo
 751  */
 752
 753 /* structure for Rx Queue Dialog reg in rxmac address map.
 754  * located at address 0x4090
 755  *
 756  * 31-26: reserved
 757  * 25-16: rd_ptr
 758  * 15-10: reserved
 759  * 9-0: wr_ptr
 760  */
 761
 762 /* structure for space available reg in rxmac address map.
 763  * located at address 0x4094
 764  *
 765  * 31-17: reserved
 766  * 16: space_avail_en
 767  * 15-10: reserved
 768  * 9-0: space_avail
 769  */
 770
 771 /* structure for management interface reg in rxmac address map.
 772  * located at address 0x4098
 773  *
 774  * 31-18: reserved
 775  * 17: drop_pkt_en
 776  * 16-0: drop_pkt_mask
 777  */
 778
 779 /* structure for Error reg in rxmac address map.
 780  * located at address 0x409C
 781  *
 782  * 31-4: unused
 783  * 3: mif
 784  * 2: async
 785  * 1: pkt_filter
 786  * 0: mcif
 787  */
 788
 789 /* Rx MAC Module of JAGCore Address Mapping
 790  */
 791 struct rxmac_regs {                                     /* Location: */
 792         u32 ctrl;                                       /*  0x4000 */
 793         u32 crc0;                                       /*  0x4004 */
 794         u32 crc12;                                      /*  0x4008 */
 795         u32 crc34;                                      /*  0x400C */
 796         u32 sa_lo;                                      /*  0x4010 */
 797         u32 sa_hi;                                      /*  0x4014 */
 798         u32 mask0_word0;                                /*  0x4018 */
 799         u32 mask0_word1;                                /*  0x401C */
 800         u32 mask0_word2;                                /*  0x4020 */
 801         u32 mask0_word3;                                /*  0x4024 */
 802         u32 mask1_word0;                                /*  0x4028 */
 803         u32 mask1_word1;                                /*  0x402C */
 804         u32 mask1_word2;                                /*  0x4030 */
 805         u32 mask1_word3;                                /*  0x4034 */
 806         u32 mask2_word0;                                /*  0x4038 */
 807         u32 mask2_word1;                                /*  0x403C */
 808         u32 mask2_word2;                                /*  0x4040 */
 809         u32 mask2_word3;                                /*  0x4044 */
 810         u32 mask3_word0;                                /*  0x4048 */
 811         u32 mask3_word1;                                /*  0x404C */
 812         u32 mask3_word2;                                /*  0x4050 */
 813         u32 mask3_word3;                                /*  0x4054 */
 814         u32 mask4_word0;                                /*  0x4058 */
 815         u32 mask4_word1;                                /*  0x405C */
 816         u32 mask4_word2;                                /*  0x4060 */
 817         u32 mask4_word3;                                /*  0x4064 */
 818         u32 uni_pf_addr1;                               /*  0x4068 */
 819         u32 uni_pf_addr2;                               /*  0x406C */
 820         u32 uni_pf_addr3;                               /*  0x4070 */
 821         u32 multi_hash1;                                /*  0x4074 */
 822         u32 multi_hash2;                                /*  0x4078 */
 823         u32 multi_hash3;                                /*  0x407C */
 824         u32 multi_hash4;                                /*  0x4080 */
 825         u32 pf_ctrl;                                    /*  0x4084 */
 826         u32 mcif_ctrl_max_seg;                          /*  0x4088 */
 827         u32 mcif_water_mark;                            /*  0x408C */
 828         u32 rxq_diag;                                   /*  0x4090 */
 829         u32 space_avail;                                /*  0x4094 */
 830
 831         u32 mif_ctrl;                                   /*  0x4098 */
 832         u32 err_reg;                                    /*  0x409C */
 833 };
 834
 835 /* END OF RXMAC REGISTER ADDRESS MAP */
 836
 837 /* START OF MAC REGISTER ADDRESS MAP */
 838 /* structure for configuration #1 reg in mac address map.
 839  * located at address 0x5000
 840  *
 841  * 31: soft reset
 842  * 30: sim reset
 843  * 29-20: reserved
 844  * 19: reset rx mc
 845  * 18: reset tx mc
 846  * 17: reset rx func
 847  * 16: reset tx fnc
 848  * 15-9: reserved
 849  * 8: loopback
 850  * 7-6: reserved
 851  * 5: rx flow
 852  * 4: tx flow
 853  * 3: syncd rx en
 854  * 2: rx enable
 855  * 1: syncd tx en
 856  * 0: tx enable
 857  */
 858 #define ET_MAC_CFG1_SOFT_RESET          0x80000000
 859 #define ET_MAC_CFG1_SIM_RESET           0x40000000
 860 #define ET_MAC_CFG1_RESET_RXMC          0x00080000
 861 #define ET_MAC_CFG1_RESET_TXMC          0x00040000
 862 #define ET_MAC_CFG1_RESET_RXFUNC        0x00020000
 863 #define ET_MAC_CFG1_RESET_TXFUNC        0x00010000
 864 #define ET_MAC_CFG1_LOOPBACK            0x00000100
 865 #define ET_MAC_CFG1_RX_FLOW             0x00000020
 866 #define ET_MAC_CFG1_TX_FLOW             0x00000010
 867 #define ET_MAC_CFG1_RX_ENABLE           0x00000004
 868 #define ET_MAC_CFG1_TX_ENABLE           0x00000001
 869 #define ET_MAC_CFG1_WAIT                0x0000000A      /* RX & TX syncd */
 870
 871 /* structure for configuration #2 reg in mac address map.
 872  * located at address 0x5004
 873  * 31-16: reserved
 874  * 15-12: preamble
 875  * 11-10: reserved
 876  * 9-8: if mode
 877  * 7-6: reserved
 878  * 5: huge frame
 879  * 4: length check
 880  * 3: undefined
 881  * 2: pad crc
 882  * 1: crc enable
 883  * 0: full duplex
 884  */
 885 #define ET_MAC_CFG2_PREAMBLE_SHIFT      12
 886 #define ET_MAC_CFG2_IFMODE_MASK         0x0300
 887 #define ET_MAC_CFG2_IFMODE_1000         0x0200
 888 #define ET_MAC_CFG2_IFMODE_100          0x0100
 889 #define ET_MAC_CFG2_IFMODE_HUGE_FRAME   0x0020
 890 #define ET_MAC_CFG2_IFMODE_LEN_CHECK    0x0010
 891 #define ET_MAC_CFG2_IFMODE_PAD_CRC      0x0004
 892 #define ET_MAC_CFG2_IFMODE_CRC_ENABLE   0x0002
 893 #define ET_MAC_CFG2_IFMODE_FULL_DPLX    0x0001
 894
 895 /* structure for Interpacket gap reg in mac address map.
 896  * located at address 0x5008
 897  *
 898  * 31: reserved
 899  * 30-24: non B2B ipg 1
 900  * 23: undefined
 901  * 22-16: non B2B ipg 2
 902  * 15-8: Min ifg enforce
 903  * 7-0: B2B ipg
 904  *
 905  * structure for half duplex reg in mac address map.
 906  * located at address 0x500C
 907  * 31-24: reserved
 908  * 23-20: Alt BEB trunc
 909  * 19: Alt BEB enable
 910  * 18: BP no backoff
 911  * 17: no backoff
 912  * 16: excess defer
 913  * 15-12: re-xmit max
 914  * 11-10: reserved
 915  * 9-0: collision window
 916  */
 917
 918 /* structure for Maximum Frame Length reg in mac address map.
 919  * located at address 0x5010: bits 0-15 hold the length.
 920  */
 921
 922 /* structure for Reserve 1 reg in mac address map.
 923  * located at address 0x5014 - 0x5018
 924  * Defined earlier (u32)
 925  */
 926
 927 /* structure for Test reg in mac address map.
 928  * located at address 0x501C
 929  * test: bits 0-2, rest unused
 930  */
 931
 932 /* structure for MII Management Configuration reg in mac address map.
 933  * located at address 0x5020
 934  *
 935  * 31: reset MII mgmt
 936  * 30-6: unused
 937  * 5: scan auto increment
 938  * 4: preamble suppress
 939  * 3: undefined
 940  * 2-0: mgmt clock reset
 941  */
 942 #define ET_MAC_MIIMGMT_CLK_RST  0x0007
 943
 944 /* structure for MII Management Command reg in mac address map.
 945  * located at address 0x5024
 946  * bit 1: scan cycle
 947  * bit 0: read cycle
 948  */
 949
 950 /* structure for MII Management Address reg in mac address map.
 951  * located at address 0x5028
 952  * 31-13: reserved
 953  * 12-8: phy addr
 954  * 7-5: reserved
 955  * 4-0: register
 956  */
 957 #define ET_MAC_MII_ADDR(phy, reg)       ((phy) << 8 | (reg))
 958
 959 /* structure for MII Management Control reg in mac address map.
 960  * located at address 0x502C
 961  * 31-16: reserved
 962  * 15-0: phy control
 963  */
 964
 965 /* structure for MII Management Status reg in mac address map.
 966  * located at address 0x5030
 967  * 31-16: reserved
 968  * 15-0: phy control
 969  */
 970 #define ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK 0xFFFF
 971
 972 /* structure for MII Management Indicators reg in mac address map.
 973  * located at address 0x5034
 974  * 31-3: reserved
 975  * 2: not valid
 976  * 1: scanning
 977  * 0: busy
 978  */
 979 #define ET_MAC_MGMT_BUSY        0x00000001      /* busy */
 980 #define ET_MAC_MGMT_WAIT        0x00000005      /* busy | not valid */
 981
 982 /* structure for Interface Control reg in mac address map.
 983  * located at address 0x5038
 984  *
 985  * 31: reset if module
 986  * 30-28: reserved
 987  * 27: tbi mode
 988  * 26: ghd mode
 989  * 25: lhd mode
 990  * 24: phy mode
 991  * 23: reset per mii
 992  * 22-17: reserved
 993  * 16: speed
 994  * 15: reset pe100x
 995  * 14-11: reserved
 996  * 10: force quiet
 997  * 9: no cipher
 998  * 8: disable link fail
 999  * 7: reset gpsi
1000  * 6-1: reserved
1001  * 0: enable jabber protection
1002  */
1003 #define ET_MAC_IFCTRL_GHDMODE   (1 << 26)
1004 #define ET_MAC_IFCTRL_PHYMODE   (1 << 24)
1005
1006 /* structure for Interface Status reg in mac address map.
1007  * located at address 0x503C
1008  *
1009  * 31-10: reserved
1010  * 9: excess_defer
1011  * 8: clash
1012  * 7: phy_jabber
1013  * 6: phy_link_ok
1014  * 5: phy_full_duplex
1015  * 4: phy_speed
1016  * 3: pe100x_link_fail
1017  * 2: pe10t_loss_carrier
1018  * 1: pe10t_sqe_error
1019  * 0: pe10t_jabber
1020  */
1021
1022 /* structure for Mac Station Address, Part 1 reg in mac address map.
1023  * located at address 0x5040
1024  *
1025  * 31-24: Octet6
1026  * 23-16: Octet5
1027  * 15-8: Octet4
1028  * 7-0: Octet3
1029  */
1030 #define ET_MAC_STATION_ADDR1_OC6_SHIFT 24
1031 #define ET_MAC_STATION_ADDR1_OC5_SHIFT 16
1032 #define ET_MAC_STATION_ADDR1_OC4_SHIFT 8
1033
1034 /* structure for Mac Station Address, Part 2 reg in mac address map.
1035  * located at address 0x5044
1036  *
1037  * 31-24: Octet2
1038  * 23-16: Octet1
1039  * 15-0: reserved
1040  */
1041 #define ET_MAC_STATION_ADDR2_OC2_SHIFT 24
1042 #define ET_MAC_STATION_ADDR2_OC1_SHIFT 16
1043
1044 /* MAC Module of JAGCore Address Mapping
1045  */
1046 struct mac_regs {                                       /* Location: */
1047         u32 cfg1;                                       /*  0x5000 */
1048         u32 cfg2;                                       /*  0x5004 */
1049         u32 ipg;                                        /*  0x5008 */
1050         u32 hfdp;                                       /*  0x500C */
1051         u32 max_fm_len;                                 /*  0x5010 */
1052         u32 rsv1;                                       /*  0x5014 */
1053         u32 rsv2;                                       /*  0x5018 */
1054         u32 mac_test;                                   /*  0x501C */
1055         u32 mii_mgmt_cfg;                               /*  0x5020 */
1056         u32 mii_mgmt_cmd;                               /*  0x5024 */
1057         u32 mii_mgmt_addr;                              /*  0x5028 */
1058         u32 mii_mgmt_ctrl;                              /*  0x502C */
1059         u32 mii_mgmt_stat;                              /*  0x5030 */
1060         u32 mii_mgmt_indicator;                         /*  0x5034 */
1061         u32 if_ctrl;                                    /*  0x5038 */
1062         u32 if_stat;                                    /*  0x503C */
1063         u32 station_addr_1;                             /*  0x5040 */
1064         u32 station_addr_2;                             /*  0x5044 */
1065 };
1066
1067 /* END OF MAC REGISTER ADDRESS MAP */
1068
1069 /* START OF MAC STAT REGISTER ADDRESS MAP */
1070 /* structure for Carry Register One and it's Mask Register reg located in mac
1071  * stat address map address 0x6130 and 0x6138.
1072  *
1073  * 31: tr64
1074  * 30: tr127
1075  * 29: tr255
1076  * 28: tr511
1077  * 27: tr1k
1078  * 26: trmax
1079  * 25: trmgv
1080  * 24-17: unused
1081  * 16: rbyt
1082  * 15: rpkt
1083  * 14: rfcs
1084  * 13: rmca
1085  * 12: rbca
1086  * 11: rxcf
1087  * 10: rxpf
1088  * 9: rxuo
1089  * 8: raln
1090  * 7: rflr
1091  * 6: rcde
1092  * 5: rcse
1093  * 4: rund
1094  * 3: rovr
1095  * 2: rfrg
1096  * 1: rjbr
1097  * 0: rdrp
1098  */
1099
1100 /* structure for Carry Register Two Mask Register reg in mac stat address map.
1101  * located at address 0x613C
1102  *
1103  * 31-20: unused
1104  * 19: tjbr
1105  * 18: tfcs
1106  * 17: txcf
1107  * 16: tovr
1108  * 15: tund
1109  * 14: trfg
1110  * 13: tbyt
1111  * 12: tpkt
1112  * 11: tmca
1113  * 10: tbca
1114  * 9: txpf
1115  * 8: tdfr
1116  * 7: tedf
1117  * 6: tscl
1118  * 5: tmcl
1119  * 4: tlcl
1120  * 3: txcl
1121  * 2: tncl
1122  * 1: tpfh
1123  * 0: tdrp
1124  */
1125
1126 /* MAC STATS Module of JAGCore Address Mapping
1127  */
1128 struct macstat_regs {                   /* Location: */
1129         u32 pad[32];                    /*  0x6000 - 607C */
1130
1131         /* counters */
1132         u32 txrx_0_64_byte_frames;      /*  0x6080 */
1133         u32 txrx_65_127_byte_frames;    /*  0x6084 */
1134         u32 txrx_128_255_byte_frames;   /*  0x6088 */
1135         u32 txrx_256_511_byte_frames;   /*  0x608C */
1136         u32 txrx_512_1023_byte_frames;  /*  0x6090 */
1137         u32 txrx_1024_1518_byte_frames; /*  0x6094 */
1138         u32 txrx_1519_1522_gvln_frames; /*  0x6098 */
1139         u32 rx_bytes;                   /*  0x609C */
1140         u32 rx_packets;                 /*  0x60A0 */
1141         u32 rx_fcs_errs;                /*  0x60A4 */
1142         u32 rx_multicast_packets;       /*  0x60A8 */
1143         u32 rx_broadcast_packets;       /*  0x60AC */
1144         u32 rx_control_frames;          /*  0x60B0 */
1145         u32 rx_pause_frames;            /*  0x60B4 */
1146         u32 rx_unknown_opcodes;         /*  0x60B8 */
1147         u32 rx_align_errs;              /*  0x60BC */
1148         u32 rx_frame_len_errs;          /*  0x60C0 */
1149         u32 rx_code_errs;               /*  0x60C4 */
1150         u32 rx_carrier_sense_errs;      /*  0x60C8 */
1151         u32 rx_undersize_packets;       /*  0x60CC */
1152         u32 rx_oversize_packets;        /*  0x60D0 */
1153         u32 rx_fragment_packets;        /*  0x60D4 */
1154         u32 rx_jabbers;                 /*  0x60D8 */
1155         u32 rx_drops;                   /*  0x60DC */
1156         u32 tx_bytes;                   /*  0x60E0 */
1157         u32 tx_packets;                 /*  0x60E4 */
1158         u32 tx_multicast_packets;       /*  0x60E8 */
1159         u32 tx_broadcast_packets;       /*  0x60EC */
1160         u32 tx_pause_frames;            /*  0x60F0 */
1161         u32 tx_deferred;                /*  0x60F4 */
1162         u32 tx_excessive_deferred;      /*  0x60F8 */
1163         u32 tx_single_collisions;       /*  0x60FC */
1164         u32 tx_multiple_collisions;     /*  0x6100 */
1165         u32 tx_late_collisions;         /*  0x6104 */
1166         u32 tx_excessive_collisions;    /*  0x6108 */
1167         u32 tx_total_collisions;        /*  0x610C */
1168         u32 tx_pause_honored_frames;    /*  0x6110 */
1169         u32 tx_drops;                   /*  0x6114 */
1170         u32 tx_jabbers;                 /*  0x6118 */
1171         u32 tx_fcs_errs;                /*  0x611C */
1172         u32 tx_control_frames;          /*  0x6120 */
1173         u32 tx_oversize_frames;         /*  0x6124 */
1174         u32 tx_undersize_frames;        /*  0x6128 */
1175         u32 tx_fragments;               /*  0x612C */
1176         u32 carry_reg1;                 /*  0x6130 */
1177         u32 carry_reg2;                 /*  0x6134 */
1178         u32 carry_reg1_mask;            /*  0x6138 */
1179         u32 carry_reg2_mask;            /*  0x613C */
1180 };
1181
1182 /* END OF MAC STAT REGISTER ADDRESS MAP */
1183
1184 /* START OF MMC REGISTER ADDRESS MAP */
1185 /* Main Memory Controller Control reg in mmc address map.
1186  * located at address 0x7000
1187  */
1188 #define ET_MMC_ENABLE           1
1189 #define ET_MMC_ARB_DISABLE      2
1190 #define ET_MMC_RXMAC_DISABLE    4
1191 #define ET_MMC_TXMAC_DISABLE    8
1192 #define ET_MMC_TXDMA_DISABLE    16
1193 #define ET_MMC_RXDMA_DISABLE    32
1194 #define ET_MMC_FORCE_CE         64
1195
1196 /* Main Memory Controller Host Memory Access Address reg in mmc
1197  * address map.  Located at address 0x7004. Top 16 bits hold the address bits
1198  */
1199 #define ET_SRAM_REQ_ACCESS      1
1200 #define ET_SRAM_WR_ACCESS       2
1201 #define ET_SRAM_IS_CTRL         4
1202
1203 /* structure for Main Memory Controller Host Memory Access Data reg in mmc
1204  * address map.  Located at address 0x7008 - 0x7014
1205  * Defined earlier (u32)
1206  */
1207
1208 /* Memory Control Module of JAGCore Address Mapping
1209  */
1210 struct mmc_regs {               /* Location: */
1211         u32 mmc_ctrl;           /*  0x7000 */
1212         u32 sram_access;        /*  0x7004 */
1213         u32 sram_word1;         /*  0x7008 */
1214         u32 sram_word2;         /*  0x700C */
1215         u32 sram_word3;         /*  0x7010 */
1216         u32 sram_word4;         /*  0x7014 */
1217 };
1218
1219 /* END OF MMC REGISTER ADDRESS MAP */
1220
1221 /* JAGCore Address Mapping
1222  */
1223 struct address_map {
1224         struct global_regs global;
1225         /* unused section of global address map */
1226         u8 unused_global[4096 - sizeof(struct global_regs)];
1227         struct txdma_regs txdma;
1228         /* unused section of txdma address map */
1229         u8 unused_txdma[4096 - sizeof(struct txdma_regs)];
1230         struct rxdma_regs rxdma;
1231         /* unused section of rxdma address map */
1232         u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
1233         struct txmac_regs txmac;
1234         /* unused section of txmac address map */
1235         u8 unused_txmac[4096 - sizeof(struct txmac_regs)];
1236         struct rxmac_regs rxmac;
1237         /* unused section of rxmac address map */
1238         u8 unused_rxmac[4096 - sizeof(struct rxmac_regs)];
1239         struct mac_regs mac;
1240         /* unused section of mac address map */
1241         u8 unused_mac[4096 - sizeof(struct mac_regs)];
1242         struct macstat_regs macstat;
1243         /* unused section of mac stat address map */
1244         u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)];
1245         struct mmc_regs mmc;
1246         /* unused section of mmc address map */
1247         u8 unused_mmc[4096 - sizeof(struct mmc_regs)];
1248         /* unused section of address map */
1249         u8 unused_[1015808];
1250         u8 unused_exp_rom[4096];        /* MGS-size TBD */
1251         u8 unused__[524288];    /* unused section of address map */
1252 };
1253
1254 /* Defines for generic MII registers 0x00 -> 0x0F can be found in
1255  * include/linux/mii.h
1256  */
1257 /* some defines for modem registers that seem to be 'reserved' */
1258 #define PHY_INDEX_REG              0x10
1259 #define PHY_DATA_REG               0x11
1260 #define PHY_MPHY_CONTROL_REG       0x12
1261
1262 /* defines for specified registers */
1263 #define PHY_LOOPBACK_CONTROL       0x13 /* TRU_VMI_LOOPBACK_CONTROL_1_REG 19 */
1264                                         /* TRU_VMI_LOOPBACK_CONTROL_2_REG 20 */
1265 #define PHY_REGISTER_MGMT_CONTROL  0x15 /* TRU_VMI_MI_SEQ_CONTROL_REG     21 */
1266 #define PHY_CONFIG                 0x16 /* TRU_VMI_CONFIGURATION_REG      22 */
1267 #define PHY_PHY_CONTROL            0x17 /* TRU_VMI_PHY_CONTROL_REG        23 */
1268 #define PHY_INTERRUPT_MASK         0x18 /* TRU_VMI_INTERRUPT_MASK_REG     24 */
1269 #define PHY_INTERRUPT_STATUS       0x19 /* TRU_VMI_INTERRUPT_STATUS_REG   25 */
1270 #define PHY_PHY_STATUS             0x1A /* TRU_VMI_PHY_STATUS_REG         26 */
1271 #define PHY_LED_1                  0x1B /* TRU_VMI_LED_CONTROL_1_REG      27 */
1272 #define PHY_LED_2                  0x1C /* TRU_VMI_LED_CONTROL_2_REG      28 */
1273                                         /* TRU_VMI_LINK_CONTROL_REG       29 */
1274                                         /* TRU_VMI_TIMING_CONTROL_REG        */
1275
1276 /* MI Register 10: Gigabit basic mode status reg(Reg 0x0A) */
1277 #define ET_1000BT_MSTR_SLV 0x4000
1278
1279 /* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
1280
1281 /* MI Register 19: Loopback Control Reg(0x13)
1282  *      15:     mii_en
1283  *      14:     pcs_en
1284  *      13:     pmd_en
1285  *      12:     all_digital_en
1286  *      11:     replica_en
1287  *      10:     line_driver_en
1288  *      9-0:    reserved
1289  */
1290
1291 /* MI Register 20: Reserved Reg(0x14) */
1292
1293 /* MI Register 21: Management Interface Control Reg(0x15)
1294  *      15-11:  reserved
1295  *      10-4:   mi_error_count
1296  *      3:      reserved
1297  *      2:      ignore_10g_fr
1298  *      1:      reserved
1299  *      0:      preamble_suppress_en
1300  */
1301
1302 /* MI Register 22: PHY Configuration Reg(0x16)
1303  *      15:     crs_tx_en
1304  *      14:     reserved
1305  *      13-12:  tx_fifo_depth
1306  *      11-10:  speed_downshift
1307  *      9:      pbi_detect
1308  *      8:      tbi_rate
1309  *      7:      alternate_np
1310  *      6:      group_mdio_en
1311  *      5:      tx_clock_en
1312  *      4:      sys_clock_en
1313  *      3:      reserved
1314  *      2-0:    mac_if_mode
1315  */
1316 #define ET_PHY_CONFIG_TX_FIFO_DEPTH     0x3000
1317
1318 #define ET_PHY_CONFIG_FIFO_DEPTH_8      0x0000
1319 #define ET_PHY_CONFIG_FIFO_DEPTH_16     0x1000
1320 #define ET_PHY_CONFIG_FIFO_DEPTH_32     0x2000
1321 #define ET_PHY_CONFIG_FIFO_DEPTH_64     0x3000
1322
1323 /* MI Register 23: PHY CONTROL Reg(0x17)
1324  *      15:     reserved
1325  *      14:     tdr_en
1326  *      13:     reserved
1327  *      12-11:  downshift_attempts
1328  *      10-6:   reserved
1329  *      5:      jabber_10baseT
1330  *      4:      sqe_10baseT
1331  *      3:      tp_loopback_10baseT
1332  *      2:      preamble_gen_en
1333  *      1:      reserved
1334  *      0:      force_int
1335  */
1336
1337 /* MI Register 24: Interrupt Mask Reg(0x18)
1338  *      15-10:  reserved
1339  *      9:      mdio_sync_lost
1340  *      8:      autoneg_status
1341  *      7:      hi_bit_err
1342  *      6:      np_rx
1343  *      5:      err_counter_full
1344  *      4:      fifo_over_underflow
1345  *      3:      rx_status
1346  *      2:      link_status
1347  *      1:      automatic_speed
1348  *      0:      int_en
1349  */
1350
1351 /* MI Register 25: Interrupt Status Reg(0x19)
1352  *      15-10:  reserved
1353  *      9:      mdio_sync_lost
1354  *      8:      autoneg_status
1355  *      7:      hi_bit_err
1356  *      6:      np_rx
1357  *      5:      err_counter_full
1358  *      4:      fifo_over_underflow
1359  *      3:      rx_status
1360  *      2:      link_status
1361  *      1:      automatic_speed
1362  *      0:      int_en
1363  */
1364
1365 /* MI Register 26: PHY Status Reg(0x1A)
1366  *      15:     reserved
1367  *      14-13:  autoneg_fault
1368  *      12:     autoneg_status
1369  *      11:     mdi_x_status
1370  *      10:     polarity_status
1371  *      9-8:    speed_status
1372  *      7:      duplex_status
1373  *      6:      link_status
1374  *      5:      tx_status
1375  *      4:      rx_status
1376  *      3:      collision_status
1377  *      2:      autoneg_en
1378  *      1:      pause_en
1379  *      0:      asymmetric_dir
1380  */
1381 #define ET_PHY_AUTONEG_STATUS   0x1000
1382 #define ET_PHY_POLARITY_STATUS  0x0400
1383 #define ET_PHY_SPEED_STATUS     0x0300
1384 #define ET_PHY_DUPLEX_STATUS    0x0080
1385 #define ET_PHY_LSTATUS          0x0040
1386 #define ET_PHY_AUTONEG_ENABLE   0x0020
1387
1388 /* MI Register 27: LED Control Reg 1(0x1B)
1389  *      15-14:  reserved
1390  *      13-12:  led_dup_indicate
1391  *      11-10:  led_10baseT
1392  *      9-8:    led_collision
1393  *      7-4:    reserved
1394  *      3-2:    pulse_dur
1395  *      1:      pulse_stretch1
1396  *      0:      pulse_stretch0
1397  */
1398
1399 /* MI Register 28: LED Control Reg 2(0x1C)
1400  *      15-12:  led_link
1401  *      11-8:   led_tx_rx
1402  *      7-4:    led_100BaseTX
1403  *      3-0:    led_1000BaseT
1404  */
1405 #define ET_LED2_LED_LINK        0xF000
1406 #define ET_LED2_LED_TXRX        0x0F00
1407 #define ET_LED2_LED_100TX       0x00F0
1408 #define ET_LED2_LED_1000T       0x000F
1409
1410 /* defines for LED control reg 2 values */
1411 #define LED_VAL_1000BT                  0x0
1412 #define LED_VAL_100BTX                  0x1
1413 #define LED_VAL_10BT                    0x2
1414 #define LED_VAL_1000BT_100BTX           0x3 /* 1000BT on, 100BTX blink */
1415 #define LED_VAL_LINKON                  0x4
1416 #define LED_VAL_TX                      0x5
1417 #define LED_VAL_RX                      0x6
1418 #define LED_VAL_TXRX                    0x7 /* TX or RX */
1419 #define LED_VAL_DUPLEXFULL              0x8
1420 #define LED_VAL_COLLISION               0x9
1421 #define LED_VAL_LINKON_ACTIVE           0xA /* Link on, activity blink */
1422 #define LED_VAL_LINKON_RECV             0xB /* Link on, receive blink */
1423 #define LED_VAL_DUPLEXFULL_COLLISION    0xC /* Duplex on, collision blink */
1424 #define LED_VAL_BLINK                   0xD
1425 #define LED_VAL_ON                      0xE
1426 #define LED_VAL_OFF                     0xF
1427
1428 #define LED_LINK_SHIFT                  12
1429 #define LED_TXRX_SHIFT                  8
1430 #define LED_100TX_SHIFT                 4
1431
1432 /* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */