drivers/net/ethernet/aurora/nb8800.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _NB8800_H_
   3 #define _NB8800_H_
   4
   5 #include <linux/types.h>
   6 #include <linux/skbuff.h>
   7 #include <linux/phy.h>
   8 #include <linux/clk.h>
   9 #include <linux/bitops.h>
  10
  11 #define RX_DESC_COUNT                   256
  12 #define TX_DESC_COUNT                   256
  13
  14 #define NB8800_DESC_LOW                 4
  15
  16 #define RX_BUF_SIZE                     1552
  17
  18 #define RX_COPYBREAK                    256
  19 #define RX_COPYHDR                      128
  20
  21 #define MAX_MDC_CLOCK                   2500000
  22
  23 /* Stargate Solutions SSN8800 core registers */
  24 #define NB8800_TX_CTL1                  0x000
  25 #define TX_TPD                          BIT(5)
  26 #define TX_APPEND_FCS                   BIT(4)
  27 #define TX_PAD_EN                       BIT(3)
  28 #define TX_RETRY_EN                     BIT(2)
  29 #define TX_EN                           BIT(0)
  30
  31 #define NB8800_TX_CTL2                  0x001
  32
  33 #define NB8800_RX_CTL                   0x004
  34 #define RX_BC_DISABLE                   BIT(7)
  35 #define RX_RUNT                         BIT(6)
  36 #define RX_AF_EN                        BIT(5)
  37 #define RX_PAUSE_EN                     BIT(3)
  38 #define RX_SEND_CRC                     BIT(2)
  39 #define RX_PAD_STRIP                    BIT(1)
  40 #define RX_EN                           BIT(0)
  41
  42 #define NB8800_RANDOM_SEED              0x008
  43 #define NB8800_TX_SDP                   0x14
  44 #define NB8800_TX_TPDP1                 0x18
  45 #define NB8800_TX_TPDP2                 0x19
  46 #define NB8800_SLOT_TIME                0x1c
  47
  48 #define NB8800_MDIO_CMD                 0x020
  49 #define MDIO_CMD_GO                     BIT(31)
  50 #define MDIO_CMD_WR                     BIT(26)
  51 #define MDIO_CMD_ADDR(x)                ((x) << 21)
  52 #define MDIO_CMD_REG(x)                 ((x) << 16)
  53 #define MDIO_CMD_DATA(x)                ((x) <<  0)
  54
  55 #define NB8800_MDIO_STS                 0x024
  56 #define MDIO_STS_ERR                    BIT(31)
  57
  58 #define NB8800_MC_ADDR(i)               (0x028 + (i))
  59 #define NB8800_MC_INIT                  0x02e
  60 #define NB8800_UC_ADDR(i)               (0x03c + (i))
  61
  62 #define NB8800_MAC_MODE                 0x044
  63 #define RGMII_MODE                      BIT(7)
  64 #define HALF_DUPLEX                     BIT(4)
  65 #define BURST_EN                        BIT(3)
  66 #define LOOPBACK_EN                     BIT(2)
  67 #define GMAC_MODE                       BIT(0)
  68
  69 #define NB8800_IC_THRESHOLD             0x050
  70 #define NB8800_PE_THRESHOLD             0x051
  71 #define NB8800_PF_THRESHOLD             0x052
  72 #define NB8800_TX_BUFSIZE               0x054
  73 #define NB8800_FIFO_CTL                 0x056
  74 #define NB8800_PQ1                      0x060
  75 #define NB8800_PQ2                      0x061
  76 #define NB8800_SRC_ADDR(i)              (0x06a + (i))
  77 #define NB8800_STAT_DATA                0x078
  78 #define NB8800_STAT_INDEX               0x07c
  79 #define NB8800_STAT_CLEAR               0x07d
  80
  81 #define NB8800_SLEEP_MODE               0x07e
  82 #define SLEEP_MODE                      BIT(0)
  83
  84 #define NB8800_WAKEUP                   0x07f
  85 #define WAKEUP                          BIT(0)
  86
  87 /* Aurora NB8800 host interface registers */
  88 #define NB8800_TXC_CR                   0x100
  89 #define TCR_LK                          BIT(12)
  90 #define TCR_DS                          BIT(11)
  91 #define TCR_BTS(x)                      (((x) & 0x7) << 8)
  92 #define TCR_DIE                         BIT(7)
  93 #define TCR_TFI(x)                      (((x) & 0x7) << 4)
  94 #define TCR_LE                          BIT(3)
  95 #define TCR_RS                          BIT(2)
  96 #define TCR_DM                          BIT(1)
  97 #define TCR_EN                          BIT(0)
  98
  99 #define NB8800_TXC_SR                   0x104
 100 #define TSR_DE                          BIT(3)
 101 #define TSR_DI                          BIT(2)
 102 #define TSR_TO                          BIT(1)
 103 #define TSR_TI                          BIT(0)
 104
 105 #define NB8800_TX_SAR                   0x108
 106 #define NB8800_TX_DESC_ADDR             0x10c
 107
 108 #define NB8800_TX_REPORT_ADDR           0x110
 109 #define TX_BYTES_TRANSFERRED(x)         (((x) >> 16) & 0xffff)
 110 #define TX_FIRST_DEFERRAL               BIT(7)
 111 #define TX_EARLY_COLLISIONS(x)          (((x) >> 3) & 0xf)
 112 #define TX_LATE_COLLISION               BIT(2)
 113 #define TX_PACKET_DROPPED               BIT(1)
 114 #define TX_FIFO_UNDERRUN                BIT(0)
 115 #define IS_TX_ERROR(r)                  ((r) & 0x07)
 116
 117 #define NB8800_TX_FIFO_SR               0x114
 118 #define NB8800_TX_ITR                   0x118
 119
 120 #define NB8800_RXC_CR                   0x200
 121 #define RCR_FL                          BIT(13)
 122 #define RCR_LK                          BIT(12)
 123 #define RCR_DS                          BIT(11)
 124 #define RCR_BTS(x)                      (((x) & 7) << 8)
 125 #define RCR_DIE                         BIT(7)
 126 #define RCR_RFI(x)                      (((x) & 7) << 4)
 127 #define RCR_LE                          BIT(3)
 128 #define RCR_RS                          BIT(2)
 129 #define RCR_DM                          BIT(1)
 130 #define RCR_EN                          BIT(0)
 131
 132 #define NB8800_RXC_SR                   0x204
 133 #define RSR_DE                          BIT(3)
 134 #define RSR_DI                          BIT(2)
 135 #define RSR_RO                          BIT(1)
 136 #define RSR_RI                          BIT(0)
 137
 138 #define NB8800_RX_SAR                   0x208
 139 #define NB8800_RX_DESC_ADDR             0x20c
 140
 141 #define NB8800_RX_REPORT_ADDR           0x210
 142 #define RX_BYTES_TRANSFERRED(x)         (((x) >> 16) & 0xFFFF)
 143 #define RX_MULTICAST_PKT                BIT(9)
 144 #define RX_BROADCAST_PKT                BIT(8)
 145 #define RX_LENGTH_ERR                   BIT(7)
 146 #define RX_FCS_ERR                      BIT(6)
 147 #define RX_RUNT_PKT                     BIT(5)
 148 #define RX_FIFO_OVERRUN                 BIT(4)
 149 #define RX_LATE_COLLISION               BIT(3)
 150 #define RX_ALIGNMENT_ERROR              BIT(2)
 151 #define RX_ERROR_MASK                   0xfc
 152 #define IS_RX_ERROR(r)                  ((r) & RX_ERROR_MASK)
 153
 154 #define NB8800_RX_FIFO_SR               0x214
 155 #define NB8800_RX_ITR                   0x218
 156
 157 /* Sigma Designs SMP86xx additional registers */
 158 #define NB8800_TANGOX_PAD_MODE          0x400
 159 #define PAD_MODE_MASK                   0x7
 160 #define PAD_MODE_MII                    0x0
 161 #define PAD_MODE_RGMII                  0x1
 162 #define PAD_MODE_GTX_CLK_INV            BIT(3)
 163 #define PAD_MODE_GTX_CLK_DELAY          BIT(4)
 164
 165 #define NB8800_TANGOX_MDIO_CLKDIV       0x420
 166 #define NB8800_TANGOX_RESET             0x424
 167
 168 /* Hardware DMA descriptor */
 169 struct nb8800_dma_desc {
 170         u32                             s_addr; /* start address */
 171         u32                             n_addr; /* next descriptor address */
 172         u32                             r_addr; /* report address */
 173         u32                             config;
 174 } __aligned(8);
 175
 176 #define DESC_ID                         BIT(23)
 177 #define DESC_EOC                        BIT(22)
 178 #define DESC_EOF                        BIT(21)
 179 #define DESC_LK                         BIT(20)
 180 #define DESC_DS                         BIT(19)
 181 #define DESC_BTS(x)                     (((x) & 0x7) << 16)
 182
 183 /* DMA descriptor and associated data for rx.
 184  * Allocated from coherent memory.
 185  */
 186 struct nb8800_rx_desc {
 187         /* DMA descriptor */
 188         struct nb8800_dma_desc          desc;
 189
 190         /* Status report filled in by hardware */
 191         u32                             report;
 192 };
 193
 194 /* Address of buffer on rx ring */
 195 struct nb8800_rx_buf {
 196         struct page                     *page;
 197         unsigned long                   offset;
 198 };
 199
 200 /* DMA descriptors and associated data for tx.
 201  * Allocated from coherent memory.
 202  */
 203 struct nb8800_tx_desc {
 204         /* DMA descriptor.  The second descriptor is used if packet
 205          * data is unaligned.
 206          */
 207         struct nb8800_dma_desc          desc[2];
 208
 209         /* Status report filled in by hardware */
 210         u32                             report;
 211
 212         /* Bounce buffer for initial unaligned part of packet */
 213         u8                              buf[8] __aligned(8);
 214 };
 215
 216 /* Packet in tx queue */
 217 struct nb8800_tx_buf {
 218         /* Currently queued skb */
 219         struct sk_buff                  *skb;
 220
 221         /* DMA address of the first descriptor */
 222         dma_addr_t                      dma_desc;
 223
 224         /* DMA address of packet data */
 225         dma_addr_t                      dma_addr;
 226
 227         /* Length of DMA mapping, less than skb->len if alignment
 228          * buffer is used.
 229          */
 230         unsigned int                    dma_len;
 231
 232         /* Number of packets in chain starting here */
 233         unsigned int                    chain_len;
 234
 235         /* Packet chain ready to be submitted to hardware */
 236         bool                            ready;
 237 };
 238
 239 struct nb8800_priv {
 240         struct napi_struct              napi;
 241
 242         void __iomem                    *base;
 243
 244         /* RX DMA descriptors */
 245         struct nb8800_rx_desc           *rx_descs;
 246
 247         /* RX buffers referenced by DMA descriptors */
 248         struct nb8800_rx_buf            *rx_bufs;
 249
 250         /* Current end of chain */
 251         u32                             rx_eoc;
 252
 253         /* Value for rx interrupt time register in NAPI interrupt mode */
 254         u32                             rx_itr_irq;
 255
 256         /* Value for rx interrupt time register in NAPI poll mode */
 257         u32                             rx_itr_poll;
 258
 259         /* Value for config field of rx DMA descriptors */
 260         u32                             rx_dma_config;
 261
 262         /* TX DMA descriptors */
 263         struct nb8800_tx_desc           *tx_descs;
 264
 265         /* TX packet queue */
 266         struct nb8800_tx_buf            *tx_bufs;
 267
 268         /* Number of free tx queue entries */
 269         atomic_t                        tx_free;
 270
 271         /* First free tx queue entry */
 272         u32                             tx_next;
 273
 274         /* Next buffer to transmit */
 275         u32                             tx_queue;
 276
 277         /* Start of current packet chain */
 278         struct nb8800_tx_buf            *tx_chain;
 279
 280         /* Next buffer to reclaim */
 281         u32                             tx_done;
 282
 283         /* Lock for DMA activation */
 284         spinlock_t                      tx_lock;
 285
 286         struct mii_bus                  *mii_bus;
 287         struct device_node              *phy_node;
 288
 289         /* PHY connection type from DT */
 290         phy_interface_t                 phy_mode;
 291
 292         /* Current link status */
 293         int                             speed;
 294         int                             duplex;
 295         int                             link;
 296
 297         /* Pause settings */
 298         bool                            pause_aneg;
 299         bool                            pause_rx;
 300         bool                            pause_tx;
 301
 302         /* DMA base address of rx descriptors, see rx_descs above */
 303         dma_addr_t                      rx_desc_dma;
 304
 305         /* DMA base address of tx descriptors, see tx_descs above */
 306         dma_addr_t                      tx_desc_dma;
 307
 308         struct clk                      *clk;
 309 };
 310
 311 struct nb8800_ops {
 312         int                             (*init)(struct net_device *dev);
 313         int                             (*reset)(struct net_device *dev);
 314 };
 315
 316 #endif /* _NB8800_H_ */