gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / net / ethernet / broadcom / bcm63xx_enet.h
blob1d3c917eb8300e4d8a6a858764ae3077674966cd
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef BCM63XX_ENET_H_
3 #define BCM63XX_ENET_H_
5 #include <linux/types.h>
6 #include <linux/mii.h>
7 #include <linux/mutex.h>
8 #include <linux/phy.h>
9 #include <linux/platform_device.h>
11 #include <bcm63xx_regs.h>
12 #include <bcm63xx_io.h>
13 #include <bcm63xx_iudma.h>
15 /* default number of descriptor */
16 #define BCMENET_DEF_RX_DESC 64
17 #define BCMENET_DEF_TX_DESC 32
19 /* maximum burst len for dma (4 bytes unit) */
20 #define BCMENET_DMA_MAXBURST 16
21 #define BCMENETSW_DMA_MAXBURST 8
23 /* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value
24 * must be low enough so that a DMA transfer of above burst length can
25 * not overflow the fifo */
26 #define BCMENET_TX_FIFO_TRESH 32
29 * hardware maximum rx/tx packet size including FCS, max mtu is
30 * actually 2047, but if we set max rx size register to 2047 we won't
31 * get overflow information if packet size is 2048 or above
33 #define BCMENET_MAX_MTU 2046
36 * MIB Counters register definitions
38 #define ETH_MIB_TX_GD_OCTETS 0
39 #define ETH_MIB_TX_GD_PKTS 1
40 #define ETH_MIB_TX_ALL_OCTETS 2
41 #define ETH_MIB_TX_ALL_PKTS 3
42 #define ETH_MIB_TX_BRDCAST 4
43 #define ETH_MIB_TX_MULT 5
44 #define ETH_MIB_TX_64 6
45 #define ETH_MIB_TX_65_127 7
46 #define ETH_MIB_TX_128_255 8
47 #define ETH_MIB_TX_256_511 9
48 #define ETH_MIB_TX_512_1023 10
49 #define ETH_MIB_TX_1024_MAX 11
50 #define ETH_MIB_TX_JAB 12
51 #define ETH_MIB_TX_OVR 13
52 #define ETH_MIB_TX_FRAG 14
53 #define ETH_MIB_TX_UNDERRUN 15
54 #define ETH_MIB_TX_COL 16
55 #define ETH_MIB_TX_1_COL 17
56 #define ETH_MIB_TX_M_COL 18
57 #define ETH_MIB_TX_EX_COL 19
58 #define ETH_MIB_TX_LATE 20
59 #define ETH_MIB_TX_DEF 21
60 #define ETH_MIB_TX_CRS 22
61 #define ETH_MIB_TX_PAUSE 23
63 #define ETH_MIB_RX_GD_OCTETS 32
64 #define ETH_MIB_RX_GD_PKTS 33
65 #define ETH_MIB_RX_ALL_OCTETS 34
66 #define ETH_MIB_RX_ALL_PKTS 35
67 #define ETH_MIB_RX_BRDCAST 36
68 #define ETH_MIB_RX_MULT 37
69 #define ETH_MIB_RX_64 38
70 #define ETH_MIB_RX_65_127 39
71 #define ETH_MIB_RX_128_255 40
72 #define ETH_MIB_RX_256_511 41
73 #define ETH_MIB_RX_512_1023 42
74 #define ETH_MIB_RX_1024_MAX 43
75 #define ETH_MIB_RX_JAB 44
76 #define ETH_MIB_RX_OVR 45
77 #define ETH_MIB_RX_FRAG 46
78 #define ETH_MIB_RX_DROP 47
79 #define ETH_MIB_RX_CRC_ALIGN 48
80 #define ETH_MIB_RX_UND 49
81 #define ETH_MIB_RX_CRC 50
82 #define ETH_MIB_RX_ALIGN 51
83 #define ETH_MIB_RX_SYM 52
84 #define ETH_MIB_RX_PAUSE 53
85 #define ETH_MIB_RX_CNTRL 54
89 * SW MIB Counters register definitions
91 #define ETHSW_MIB_TX_ALL_OCT 0
92 #define ETHSW_MIB_TX_DROP_PKTS 2
93 #define ETHSW_MIB_TX_QOS_PKTS 3
94 #define ETHSW_MIB_TX_BRDCAST 4
95 #define ETHSW_MIB_TX_MULT 5
96 #define ETHSW_MIB_TX_UNI 6
97 #define ETHSW_MIB_TX_COL 7
98 #define ETHSW_MIB_TX_1_COL 8
99 #define ETHSW_MIB_TX_M_COL 9
100 #define ETHSW_MIB_TX_DEF 10
101 #define ETHSW_MIB_TX_LATE 11
102 #define ETHSW_MIB_TX_EX_COL 12
103 #define ETHSW_MIB_TX_PAUSE 14
104 #define ETHSW_MIB_TX_QOS_OCT 15
106 #define ETHSW_MIB_RX_ALL_OCT 17
107 #define ETHSW_MIB_RX_UND 19
108 #define ETHSW_MIB_RX_PAUSE 20
109 #define ETHSW_MIB_RX_64 21
110 #define ETHSW_MIB_RX_65_127 22
111 #define ETHSW_MIB_RX_128_255 23
112 #define ETHSW_MIB_RX_256_511 24
113 #define ETHSW_MIB_RX_512_1023 25
114 #define ETHSW_MIB_RX_1024_1522 26
115 #define ETHSW_MIB_RX_OVR 27
116 #define ETHSW_MIB_RX_JAB 28
117 #define ETHSW_MIB_RX_ALIGN 29
118 #define ETHSW_MIB_RX_CRC 30
119 #define ETHSW_MIB_RX_GD_OCT 31
120 #define ETHSW_MIB_RX_DROP 33
121 #define ETHSW_MIB_RX_UNI 34
122 #define ETHSW_MIB_RX_MULT 35
123 #define ETHSW_MIB_RX_BRDCAST 36
124 #define ETHSW_MIB_RX_SA_CHANGE 37
125 #define ETHSW_MIB_RX_FRAG 38
126 #define ETHSW_MIB_RX_OVR_DISC 39
127 #define ETHSW_MIB_RX_SYM 40
128 #define ETHSW_MIB_RX_QOS_PKTS 41
129 #define ETHSW_MIB_RX_QOS_OCT 42
130 #define ETHSW_MIB_RX_1523_2047 44
131 #define ETHSW_MIB_RX_2048_4095 45
132 #define ETHSW_MIB_RX_4096_8191 46
133 #define ETHSW_MIB_RX_8192_9728 47
136 struct bcm_enet_mib_counters {
137 u64 tx_gd_octets;
138 u32 tx_gd_pkts;
139 u32 tx_all_octets;
140 u32 tx_all_pkts;
141 u32 tx_unicast;
142 u32 tx_brdcast;
143 u32 tx_mult;
144 u32 tx_64;
145 u32 tx_65_127;
146 u32 tx_128_255;
147 u32 tx_256_511;
148 u32 tx_512_1023;
149 u32 tx_1024_max;
150 u32 tx_1523_2047;
151 u32 tx_2048_4095;
152 u32 tx_4096_8191;
153 u32 tx_8192_9728;
154 u32 tx_jab;
155 u32 tx_drop;
156 u32 tx_ovr;
157 u32 tx_frag;
158 u32 tx_underrun;
159 u32 tx_col;
160 u32 tx_1_col;
161 u32 tx_m_col;
162 u32 tx_ex_col;
163 u32 tx_late;
164 u32 tx_def;
165 u32 tx_crs;
166 u32 tx_pause;
167 u64 rx_gd_octets;
168 u32 rx_gd_pkts;
169 u32 rx_all_octets;
170 u32 rx_all_pkts;
171 u32 rx_brdcast;
172 u32 rx_unicast;
173 u32 rx_mult;
174 u32 rx_64;
175 u32 rx_65_127;
176 u32 rx_128_255;
177 u32 rx_256_511;
178 u32 rx_512_1023;
179 u32 rx_1024_max;
180 u32 rx_jab;
181 u32 rx_ovr;
182 u32 rx_frag;
183 u32 rx_drop;
184 u32 rx_crc_align;
185 u32 rx_und;
186 u32 rx_crc;
187 u32 rx_align;
188 u32 rx_sym;
189 u32 rx_pause;
190 u32 rx_cntrl;
194 struct bcm_enet_priv {
196 /* base remapped address of device */
197 void __iomem *base;
199 /* mac irq, rx_dma irq, tx_dma irq */
200 int irq;
201 int irq_rx;
202 int irq_tx;
204 /* hw view of rx & tx dma ring */
205 dma_addr_t rx_desc_dma;
206 dma_addr_t tx_desc_dma;
208 /* allocated size (in bytes) for rx & tx dma ring */
209 unsigned int rx_desc_alloc_size;
210 unsigned int tx_desc_alloc_size;
213 struct napi_struct napi;
215 /* dma channel id for rx */
216 int rx_chan;
218 /* number of dma desc in rx ring */
219 int rx_ring_size;
221 /* cpu view of rx dma ring */
222 struct bcm_enet_desc *rx_desc_cpu;
224 /* current number of armed descriptor given to hardware for rx */
225 int rx_desc_count;
227 /* next rx descriptor to fetch from hardware */
228 int rx_curr_desc;
230 /* next dirty rx descriptor to refill */
231 int rx_dirty_desc;
233 /* size of allocated rx skbs */
234 unsigned int rx_skb_size;
236 /* list of skb given to hw for rx */
237 struct sk_buff **rx_skb;
239 /* used when rx skb allocation failed, so we defer rx queue
240 * refill */
241 struct timer_list rx_timeout;
243 /* lock rx_timeout against rx normal operation */
244 spinlock_t rx_lock;
247 /* dma channel id for tx */
248 int tx_chan;
250 /* number of dma desc in tx ring */
251 int tx_ring_size;
253 /* maximum dma burst size */
254 int dma_maxburst;
256 /* cpu view of rx dma ring */
257 struct bcm_enet_desc *tx_desc_cpu;
259 /* number of available descriptor for tx */
260 int tx_desc_count;
262 /* next tx descriptor avaiable */
263 int tx_curr_desc;
265 /* next dirty tx descriptor to reclaim */
266 int tx_dirty_desc;
268 /* list of skb given to hw for tx */
269 struct sk_buff **tx_skb;
271 /* lock used by tx reclaim and xmit */
272 spinlock_t tx_lock;
275 /* set if internal phy is ignored and external mii interface
276 * is selected */
277 int use_external_mii;
279 /* set if a phy is connected, phy address must be known,
280 * probing is not possible */
281 int has_phy;
282 int phy_id;
284 /* set if connected phy has an associated irq */
285 int has_phy_interrupt;
286 int phy_interrupt;
288 /* used when a phy is connected (phylib used) */
289 struct mii_bus *mii_bus;
290 int old_link;
291 int old_duplex;
292 int old_pause;
294 /* used when no phy is connected */
295 int force_speed_100;
296 int force_duplex_full;
298 /* pause parameters */
299 int pause_auto;
300 int pause_rx;
301 int pause_tx;
303 /* stats */
304 struct bcm_enet_mib_counters mib;
306 /* after mib interrupt, mib registers update is done in this
307 * work queue */
308 struct work_struct mib_update_task;
310 /* lock mib update between userspace request and workqueue */
311 struct mutex mib_update_lock;
313 /* mac clock */
314 struct clk *mac_clk;
316 /* phy clock if internal phy is used */
317 struct clk *phy_clk;
319 /* network device reference */
320 struct net_device *net_dev;
322 /* platform device reference */
323 struct platform_device *pdev;
325 /* maximum hardware transmit/receive size */
326 unsigned int hw_mtu;
328 bool enet_is_sw;
330 /* port mapping for switch devices */
331 int num_ports;
332 struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
333 int sw_port_link[ENETSW_MAX_PORT];
335 /* used to poll switch port state */
336 struct timer_list swphy_poll;
337 spinlock_t enetsw_mdio_lock;
339 /* dma channel enable mask */
340 u32 dma_chan_en_mask;
342 /* dma channel interrupt mask */
343 u32 dma_chan_int_mask;
345 /* DMA engine has internal SRAM */
346 bool dma_has_sram;
348 /* dma channel width */
349 unsigned int dma_chan_width;
351 /* dma descriptor shift value */
352 unsigned int dma_desc_shift;
356 #endif /* ! BCM63XX_ENET_H_ */