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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / net / ethernet / intel / e1000e / 82571.c
blob2c1bab377b2a584a3d43c8a39d3899f57f35ace7
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 /* 82571EB Gigabit Ethernet Controller
5 * 82571EB Gigabit Ethernet Controller (Copper)
6 * 82571EB Gigabit Ethernet Controller (Fiber)
7 * 82571EB Dual Port Gigabit Mezzanine Adapter
8 * 82571EB Quad Port Gigabit Mezzanine Adapter
9 * 82571PT Gigabit PT Quad Port Server ExpressModule
10 * 82572EI Gigabit Ethernet Controller (Copper)
11 * 82572EI Gigabit Ethernet Controller (Fiber)
12 * 82572EI Gigabit Ethernet Controller
13 * 82573V Gigabit Ethernet Controller (Copper)
14 * 82573E Gigabit Ethernet Controller (Copper)
15 * 82573L Gigabit Ethernet Controller
16 * 82574L Gigabit Network Connection
17 * 82583V Gigabit Network Connection
18 */
19
20 #include "e1000.h"
21
22 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
23 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
24 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
25 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
26 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
27 u16 words, u16 *data);
28 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
29 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
30 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
31 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
32 static s32 e1000_led_on_82574(struct e1000_hw *hw);
33 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
34 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
35 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
36 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
37 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
38 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);
39 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);
40
41 /**
42 * e1000_init_phy_params_82571 - Init PHY func ptrs.
43 * @hw: pointer to the HW structure
44 **/
45 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
46 {
47 struct e1000_phy_info *phy = &hw->phy;
48 s32 ret_val;
49
50 if (hw->phy.media_type != e1000_media_type_copper) {
51 phy->type = e1000_phy_none;
52 return 0;
53 }
54
55 phy->addr = 1;
56 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
57 phy->reset_delay_us = 100;
58
59 phy->ops.power_up = e1000_power_up_phy_copper;
60 phy->ops.power_down = e1000_power_down_phy_copper_82571;
61
62 switch (hw->mac.type) {
63 case e1000_82571:
64 case e1000_82572:
65 phy->type = e1000_phy_igp_2;
66 break;
67 case e1000_82573:
68 phy->type = e1000_phy_m88;
69 break;
70 case e1000_82574:
71 case e1000_82583:
72 phy->type = e1000_phy_bm;
73 phy->ops.acquire = e1000_get_hw_semaphore_82574;
74 phy->ops.release = e1000_put_hw_semaphore_82574;
75 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
76 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
77 break;
78 default:
79 return -E1000_ERR_PHY;
80 }
81
82 /* This can only be done after all function pointers are setup. */
83 ret_val = e1000_get_phy_id_82571(hw);
84 if (ret_val) {
85 e_dbg("Error getting PHY ID\n");
86 return ret_val;
87 }
88
89 /* Verify phy id */
90 switch (hw->mac.type) {
91 case e1000_82571:
92 case e1000_82572:
93 if (phy->id != IGP01E1000_I_PHY_ID)
94 ret_val = -E1000_ERR_PHY;
95 break;
96 case e1000_82573:
97 if (phy->id != M88E1111_I_PHY_ID)
98 ret_val = -E1000_ERR_PHY;
99 break;
100 case e1000_82574:
101 case e1000_82583:
102 if (phy->id != BME1000_E_PHY_ID_R2)
103 ret_val = -E1000_ERR_PHY;
104 break;
105 default:
106 ret_val = -E1000_ERR_PHY;
107 break;
108 }
109
110 if (ret_val)
111 e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
112
113 return ret_val;
114 }
115
116 /**
117 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
118 * @hw: pointer to the HW structure
119 **/
120 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
121 {
122 struct e1000_nvm_info *nvm = &hw->nvm;
123 u32 eecd = er32(EECD);
124 u16 size;
125
126 nvm->opcode_bits = 8;
127 nvm->delay_usec = 1;
128 switch (nvm->override) {
129 case e1000_nvm_override_spi_large:
130 nvm->page_size = 32;
131 nvm->address_bits = 16;
132 break;
133 case e1000_nvm_override_spi_small:
134 nvm->page_size = 8;
135 nvm->address_bits = 8;
136 break;
137 default:
138 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
139 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
140 break;
141 }
142
143 switch (hw->mac.type) {
144 case e1000_82573:
145 case e1000_82574:
146 case e1000_82583:
147 if (((eecd >> 15) & 0x3) == 0x3) {
148 nvm->type = e1000_nvm_flash_hw;
149 nvm->word_size = 2048;
150 /* Autonomous Flash update bit must be cleared due
151 * to Flash update issue.
152 */
153 eecd &= ~E1000_EECD_AUPDEN;
154 ew32(EECD, eecd);
155 break;
156 }
157 /* Fall Through */
158 default:
159 nvm->type = e1000_nvm_eeprom_spi;
160 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
161 E1000_EECD_SIZE_EX_SHIFT);
162 /* Added to a constant, "size" becomes the left-shift value
163 * for setting word_size.
164 */
165 size += NVM_WORD_SIZE_BASE_SHIFT;
166
167 /* EEPROM access above 16k is unsupported */
168 if (size > 14)
169 size = 14;
170 nvm->word_size = BIT(size);
171 break;
172 }
173
174 /* Function Pointers */
175 switch (hw->mac.type) {
176 case e1000_82574:
177 case e1000_82583:
178 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
179 nvm->ops.release = e1000_put_hw_semaphore_82574;
180 break;
181 default:
182 break;
183 }
184
185 return 0;
186 }
187
188 /**
189 * e1000_init_mac_params_82571 - Init MAC func ptrs.
190 * @hw: pointer to the HW structure
191 **/
192 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
193 {
194 struct e1000_mac_info *mac = &hw->mac;
195 u32 swsm = 0;
196 u32 swsm2 = 0;
197 bool force_clear_smbi = false;
198
199 /* Set media type and media-dependent function pointers */
200 switch (hw->adapter->pdev->device) {
201 case E1000_DEV_ID_82571EB_FIBER:
202 case E1000_DEV_ID_82572EI_FIBER:
203 case E1000_DEV_ID_82571EB_QUAD_FIBER:
204 hw->phy.media_type = e1000_media_type_fiber;
205 mac->ops.setup_physical_interface =
206 e1000_setup_fiber_serdes_link_82571;
207 mac->ops.check_for_link = e1000e_check_for_fiber_link;
208 mac->ops.get_link_up_info =
209 e1000e_get_speed_and_duplex_fiber_serdes;
210 break;
211 case E1000_DEV_ID_82571EB_SERDES:
212 case E1000_DEV_ID_82571EB_SERDES_DUAL:
213 case E1000_DEV_ID_82571EB_SERDES_QUAD:
214 case E1000_DEV_ID_82572EI_SERDES:
215 hw->phy.media_type = e1000_media_type_internal_serdes;
216 mac->ops.setup_physical_interface =
217 e1000_setup_fiber_serdes_link_82571;
218 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
219 mac->ops.get_link_up_info =
220 e1000e_get_speed_and_duplex_fiber_serdes;
221 break;
222 default:
223 hw->phy.media_type = e1000_media_type_copper;
224 mac->ops.setup_physical_interface =
225 e1000_setup_copper_link_82571;
226 mac->ops.check_for_link = e1000e_check_for_copper_link;
227 mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper;
228 break;
229 }
230
231 /* Set mta register count */
232 mac->mta_reg_count = 128;
233 /* Set rar entry count */
234 mac->rar_entry_count = E1000_RAR_ENTRIES;
235 /* Adaptive IFS supported */
236 mac->adaptive_ifs = true;
237
238 /* MAC-specific function pointers */
239 switch (hw->mac.type) {
240 case e1000_82573:
241 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
242 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
243 mac->ops.led_on = e1000e_led_on_generic;
244 mac->ops.blink_led = e1000e_blink_led_generic;
245
246 /* FWSM register */
247 mac->has_fwsm = true;
248 /* ARC supported; valid only if manageability features are
249 * enabled.
250 */
251 mac->arc_subsystem_valid = !!(er32(FWSM) &
252 E1000_FWSM_MODE_MASK);
253 break;
254 case e1000_82574:
255 case e1000_82583:
256 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
257 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
258 mac->ops.led_on = e1000_led_on_82574;
259 break;
260 default:
261 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
262 mac->ops.led_on = e1000e_led_on_generic;
263 mac->ops.blink_led = e1000e_blink_led_generic;
264
265 /* FWSM register */
266 mac->has_fwsm = true;
267 break;
268 }
269
270 /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
271 * first NVM or PHY access. This should be done for single-port
272 * devices, and for one port only on dual-port devices so that
273 * for those devices we can still use the SMBI lock to synchronize
274 * inter-port accesses to the PHY & NVM.
275 */
276 switch (hw->mac.type) {
277 case e1000_82571:
278 case e1000_82572:
279 swsm2 = er32(SWSM2);
280
281 if (!(swsm2 & E1000_SWSM2_LOCK)) {
282 /* Only do this for the first interface on this card */
283 ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK);
284 force_clear_smbi = true;
285 } else {
286 force_clear_smbi = false;
287 }
288 break;
289 default:
290 force_clear_smbi = true;
291 break;
292 }
293
294 if (force_clear_smbi) {
295 /* Make sure SWSM.SMBI is clear */
296 swsm = er32(SWSM);
297 if (swsm & E1000_SWSM_SMBI) {
298 /* This bit should not be set on a first interface, and
299 * indicates that the bootagent or EFI code has
300 * improperly left this bit enabled
301 */
302 e_dbg("Please update your 82571 Bootagent\n");
303 }
304 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
305 }
306
307 /* Initialize device specific counter of SMBI acquisition timeouts. */
308 hw->dev_spec.e82571.smb_counter = 0;
309
310 return 0;
311 }
312
313 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
314 {
315 struct e1000_hw *hw = &adapter->hw;
316 static int global_quad_port_a; /* global port a indication */
317 struct pci_dev *pdev = adapter->pdev;
318 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
319 s32 rc;
320
321 rc = e1000_init_mac_params_82571(hw);
322 if (rc)
323 return rc;
324
325 rc = e1000_init_nvm_params_82571(hw);
326 if (rc)
327 return rc;
328
329 rc = e1000_init_phy_params_82571(hw);
330 if (rc)
331 return rc;
332
333 /* tag quad port adapters first, it's used below */
334 switch (pdev->device) {
335 case E1000_DEV_ID_82571EB_QUAD_COPPER:
336 case E1000_DEV_ID_82571EB_QUAD_FIBER:
337 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
338 case E1000_DEV_ID_82571PT_QUAD_COPPER:
339 adapter->flags |= FLAG_IS_QUAD_PORT;
340 /* mark the first port */
341 if (global_quad_port_a == 0)
342 adapter->flags |= FLAG_IS_QUAD_PORT_A;
343 /* Reset for multiple quad port adapters */
344 global_quad_port_a++;
345 if (global_quad_port_a == 4)
346 global_quad_port_a = 0;
347 break;
348 default:
349 break;
350 }
351
352 switch (adapter->hw.mac.type) {
353 case e1000_82571:
354 /* these dual ports don't have WoL on port B at all */
355 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
356 (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
357 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
358 (is_port_b))
359 adapter->flags &= ~FLAG_HAS_WOL;
360 /* quad ports only support WoL on port A */
361 if (adapter->flags & FLAG_IS_QUAD_PORT &&
362 (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
363 adapter->flags &= ~FLAG_HAS_WOL;
364 /* Does not support WoL on any port */
365 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
366 adapter->flags &= ~FLAG_HAS_WOL;
367 break;
368 case e1000_82573:
369 if (pdev->device == E1000_DEV_ID_82573L) {
370 adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
371 adapter->max_hw_frame_size = DEFAULT_JUMBO;
372 }
373 break;
374 default:
375 break;
376 }
377
378 return 0;
379 }
380
381 /**
382 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
383 * @hw: pointer to the HW structure
384 *
385 * Reads the PHY registers and stores the PHY ID and possibly the PHY
386 * revision in the hardware structure.
387 **/
388 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
389 {
390 struct e1000_phy_info *phy = &hw->phy;
391 s32 ret_val;
392 u16 phy_id = 0;
393
394 switch (hw->mac.type) {
395 case e1000_82571:
396 case e1000_82572:
397 /* The 82571 firmware may still be configuring the PHY.
398 * In this case, we cannot access the PHY until the
399 * configuration is done. So we explicitly set the
400 * PHY ID.
401 */
402 phy->id = IGP01E1000_I_PHY_ID;
403 break;
404 case e1000_82573:
405 return e1000e_get_phy_id(hw);
406 case e1000_82574:
407 case e1000_82583:
408 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
409 if (ret_val)
410 return ret_val;
411
412 phy->id = (u32)(phy_id << 16);
413 usleep_range(20, 40);
414 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
415 if (ret_val)
416 return ret_val;
417
418 phy->id |= (u32)(phy_id);
419 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
420 break;
421 default:
422 return -E1000_ERR_PHY;
423 }
424
425 return 0;
426 }
427
428 /**
429 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
430 * @hw: pointer to the HW structure
431 *
432 * Acquire the HW semaphore to access the PHY or NVM
433 **/
434 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
435 {
436 u32 swsm;
437 s32 sw_timeout = hw->nvm.word_size + 1;
438 s32 fw_timeout = hw->nvm.word_size + 1;
439 s32 i = 0;
440
441 /* If we have timedout 3 times on trying to acquire
442 * the inter-port SMBI semaphore, there is old code
443 * operating on the other port, and it is not
444 * releasing SMBI. Modify the number of times that
445 * we try for the semaphore to interwork with this
446 * older code.
447 */
448 if (hw->dev_spec.e82571.smb_counter > 2)
449 sw_timeout = 1;
450
451 /* Get the SW semaphore */
452 while (i < sw_timeout) {
453 swsm = er32(SWSM);
454 if (!(swsm & E1000_SWSM_SMBI))
455 break;
456
457 usleep_range(50, 100);
458 i++;
459 }
460
461 if (i == sw_timeout) {
462 e_dbg("Driver can't access device - SMBI bit is set.\n");
463 hw->dev_spec.e82571.smb_counter++;
464 }
465 /* Get the FW semaphore. */
466 for (i = 0; i < fw_timeout; i++) {
467 swsm = er32(SWSM);
468 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
469
470 /* Semaphore acquired if bit latched */
471 if (er32(SWSM) & E1000_SWSM_SWESMBI)
472 break;
473
474 usleep_range(50, 100);
475 }
476
477 if (i == fw_timeout) {
478 /* Release semaphores */
479 e1000_put_hw_semaphore_82571(hw);
480 e_dbg("Driver can't access the NVM\n");
481 return -E1000_ERR_NVM;
482 }
483
484 return 0;
485 }
486
487 /**
488 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
489 * @hw: pointer to the HW structure
490 *
491 * Release hardware semaphore used to access the PHY or NVM
492 **/
493 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
494 {
495 u32 swsm;
496
497 swsm = er32(SWSM);
498 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
499 ew32(SWSM, swsm);
500 }
501
502 /**
503 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
504 * @hw: pointer to the HW structure
505 *
506 * Acquire the HW semaphore during reset.
507 *
508 **/
509 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
510 {
511 u32 extcnf_ctrl;
512 s32 i = 0;
513
514 extcnf_ctrl = er32(EXTCNF_CTRL);
515 do {
516 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
517 ew32(EXTCNF_CTRL, extcnf_ctrl);
518 extcnf_ctrl = er32(EXTCNF_CTRL);
519
520 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
521 break;
522
523 usleep_range(2000, 4000);
524 i++;
525 } while (i < MDIO_OWNERSHIP_TIMEOUT);
526
527 if (i == MDIO_OWNERSHIP_TIMEOUT) {
528 /* Release semaphores */
529 e1000_put_hw_semaphore_82573(hw);
530 e_dbg("Driver can't access the PHY\n");
531 return -E1000_ERR_PHY;
532 }
533
534 return 0;
535 }
536
537 /**
538 * e1000_put_hw_semaphore_82573 - Release hardware semaphore
539 * @hw: pointer to the HW structure
540 *
541 * Release hardware semaphore used during reset.
542 *
543 **/
544 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
545 {
546 u32 extcnf_ctrl;
547
548 extcnf_ctrl = er32(EXTCNF_CTRL);
549 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
550 ew32(EXTCNF_CTRL, extcnf_ctrl);
551 }
552
553 static DEFINE_MUTEX(swflag_mutex);
554
555 /**
556 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
557 * @hw: pointer to the HW structure
558 *
559 * Acquire the HW semaphore to access the PHY or NVM.
560 *
561 **/
562 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
563 {
564 s32 ret_val;
565
566 mutex_lock(&swflag_mutex);
567 ret_val = e1000_get_hw_semaphore_82573(hw);
568 if (ret_val)
569 mutex_unlock(&swflag_mutex);
570 return ret_val;
571 }
572
573 /**
574 * e1000_put_hw_semaphore_82574 - Release hardware semaphore
575 * @hw: pointer to the HW structure
576 *
577 * Release hardware semaphore used to access the PHY or NVM
578 *
579 **/
580 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
581 {
582 e1000_put_hw_semaphore_82573(hw);
583 mutex_unlock(&swflag_mutex);
584 }
585
586 /**
587 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
588 * @hw: pointer to the HW structure
589 * @active: true to enable LPLU, false to disable
590 *
591 * Sets the LPLU D0 state according to the active flag.
592 * LPLU will not be activated unless the
593 * device autonegotiation advertisement meets standards of
594 * either 10 or 10/100 or 10/100/1000 at all duplexes.
595 * This is a function pointer entry point only called by
596 * PHY setup routines.
597 **/
598 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
599 {
600 u32 data = er32(POEMB);
601
602 if (active)
603 data |= E1000_PHY_CTRL_D0A_LPLU;
604 else
605 data &= ~E1000_PHY_CTRL_D0A_LPLU;
606
607 ew32(POEMB, data);
608 return 0;
609 }
610
611 /**
612 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
613 * @hw: pointer to the HW structure
614 * @active: boolean used to enable/disable lplu
615 *
616 * The low power link up (lplu) state is set to the power management level D3
617 * when active is true, else clear lplu for D3. LPLU
618 * is used during Dx states where the power conservation is most important.
619 * During driver activity, SmartSpeed should be enabled so performance is
620 * maintained.
621 **/
622 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
623 {
624 u32 data = er32(POEMB);
625
626 if (!active) {
627 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
628 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
629 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
630 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
631 data |= E1000_PHY_CTRL_NOND0A_LPLU;
632 }
633
634 ew32(POEMB, data);
635 return 0;
636 }
637
638 /**
639 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
640 * @hw: pointer to the HW structure
641 *
642 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
643 * Then for non-82573 hardware, set the EEPROM access request bit and wait
644 * for EEPROM access grant bit. If the access grant bit is not set, release
645 * hardware semaphore.
646 **/
647 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
648 {
649 s32 ret_val;
650
651 ret_val = e1000_get_hw_semaphore_82571(hw);
652 if (ret_val)
653 return ret_val;
654
655 switch (hw->mac.type) {
656 case e1000_82573:
657 break;
658 default:
659 ret_val = e1000e_acquire_nvm(hw);
660 break;
661 }
662
663 if (ret_val)
664 e1000_put_hw_semaphore_82571(hw);
665
666 return ret_val;
667 }
668
669 /**
670 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
671 * @hw: pointer to the HW structure
672 *
673 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
674 **/
675 static void e1000_release_nvm_82571(struct e1000_hw *hw)
676 {
677 e1000e_release_nvm(hw);
678 e1000_put_hw_semaphore_82571(hw);
679 }
680
681 /**
682 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
683 * @hw: pointer to the HW structure
684 * @offset: offset within the EEPROM to be written to
685 * @words: number of words to write
686 * @data: 16 bit word(s) to be written to the EEPROM
687 *
688 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
689 *
690 * If e1000e_update_nvm_checksum is not called after this function, the
691 * EEPROM will most likely contain an invalid checksum.
692 **/
693 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
694 u16 *data)
695 {
696 s32 ret_val;
697
698 switch (hw->mac.type) {
699 case e1000_82573:
700 case e1000_82574:
701 case e1000_82583:
702 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
703 break;
704 case e1000_82571:
705 case e1000_82572:
706 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
707 break;
708 default:
709 ret_val = -E1000_ERR_NVM;
710 break;
711 }
712
713 return ret_val;
714 }
715
716 /**
717 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
718 * @hw: pointer to the HW structure
719 *
720 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
721 * up to the checksum. Then calculates the EEPROM checksum and writes the
722 * value to the EEPROM.
723 **/
724 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
725 {
726 u32 eecd;
727 s32 ret_val;
728 u16 i;
729
730 ret_val = e1000e_update_nvm_checksum_generic(hw);
731 if (ret_val)
732 return ret_val;
733
734 /* If our nvm is an EEPROM, then we're done
735 * otherwise, commit the checksum to the flash NVM.
736 */
737 if (hw->nvm.type != e1000_nvm_flash_hw)
738 return 0;
739
740 /* Check for pending operations. */
741 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
742 usleep_range(1000, 2000);
743 if (!(er32(EECD) & E1000_EECD_FLUPD))
744 break;
745 }
746
747 if (i == E1000_FLASH_UPDATES)
748 return -E1000_ERR_NVM;
749
750 /* Reset the firmware if using STM opcode. */
751 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
752 /* The enabling of and the actual reset must be done
753 * in two write cycles.
754 */
755 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
756 e1e_flush();
757 ew32(HICR, E1000_HICR_FW_RESET);
758 }
759
760 /* Commit the write to flash */
761 eecd = er32(EECD) | E1000_EECD_FLUPD;
762 ew32(EECD, eecd);
763
764 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
765 usleep_range(1000, 2000);
766 if (!(er32(EECD) & E1000_EECD_FLUPD))
767 break;
768 }
769
770 if (i == E1000_FLASH_UPDATES)
771 return -E1000_ERR_NVM;
772
773 return 0;
774 }
775
776 /**
777 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
778 * @hw: pointer to the HW structure
779 *
780 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
781 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
782 **/
783 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
784 {
785 if (hw->nvm.type == e1000_nvm_flash_hw)
786 e1000_fix_nvm_checksum_82571(hw);
787
788 return e1000e_validate_nvm_checksum_generic(hw);
789 }
790
791 /**
792 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
793 * @hw: pointer to the HW structure
794 * @offset: offset within the EEPROM to be written to
795 * @words: number of words to write
796 * @data: 16 bit word(s) to be written to the EEPROM
797 *
798 * After checking for invalid values, poll the EEPROM to ensure the previous
799 * command has completed before trying to write the next word. After write
800 * poll for completion.
801 *
802 * If e1000e_update_nvm_checksum is not called after this function, the
803 * EEPROM will most likely contain an invalid checksum.
804 **/
805 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
806 u16 words, u16 *data)
807 {
808 struct e1000_nvm_info *nvm = &hw->nvm;
809 u32 i, eewr = 0;
810 s32 ret_val = 0;
811
812 /* A check for invalid values: offset too large, too many words,
813 * and not enough words.
814 */
815 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
816 (words == 0)) {
817 e_dbg("nvm parameter(s) out of bounds\n");
818 return -E1000_ERR_NVM;
819 }
820
821 for (i = 0; i < words; i++) {
822 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
823 ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
824 E1000_NVM_RW_REG_START);
825
826 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
827 if (ret_val)
828 break;
829
830 ew32(EEWR, eewr);
831
832 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
833 if (ret_val)
834 break;
835 }
836
837 return ret_val;
838 }
839
840 /**
841 * e1000_get_cfg_done_82571 - Poll for configuration done
842 * @hw: pointer to the HW structure
843 *
844 * Reads the management control register for the config done bit to be set.
845 **/
846 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
847 {
848 s32 timeout = PHY_CFG_TIMEOUT;
849
850 while (timeout) {
851 if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)
852 break;
853 usleep_range(1000, 2000);
854 timeout--;
855 }
856 if (!timeout) {
857 e_dbg("MNG configuration cycle has not completed.\n");
858 return -E1000_ERR_RESET;
859 }
860
861 return 0;
862 }
863
864 /**
865 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
866 * @hw: pointer to the HW structure
867 * @active: true to enable LPLU, false to disable
868 *
869 * Sets the LPLU D0 state according to the active flag. When activating LPLU
870 * this function also disables smart speed and vice versa. LPLU will not be
871 * activated unless the device autonegotiation advertisement meets standards
872 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
873 * pointer entry point only called by PHY setup routines.
874 **/
875 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
876 {
877 struct e1000_phy_info *phy = &hw->phy;
878 s32 ret_val;
879 u16 data;
880
881 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
882 if (ret_val)
883 return ret_val;
884
885 if (active) {
886 data |= IGP02E1000_PM_D0_LPLU;
887 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
888 if (ret_val)
889 return ret_val;
890
891 /* When LPLU is enabled, we should disable SmartSpeed */
892 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
893 if (ret_val)
894 return ret_val;
895 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
896 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
897 if (ret_val)
898 return ret_val;
899 } else {
900 data &= ~IGP02E1000_PM_D0_LPLU;
901 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
902 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
903 * during Dx states where the power conservation is most
904 * important. During driver activity we should enable
905 * SmartSpeed, so performance is maintained.
906 */
907 if (phy->smart_speed == e1000_smart_speed_on) {
908 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
909 &data);
910 if (ret_val)
911 return ret_val;
912
913 data |= IGP01E1000_PSCFR_SMART_SPEED;
914 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
915 data);
916 if (ret_val)
917 return ret_val;
918 } else if (phy->smart_speed == e1000_smart_speed_off) {
919 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
920 &data);
921 if (ret_val)
922 return ret_val;
923
924 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
925 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
926 data);
927 if (ret_val)
928 return ret_val;
929 }
930 }
931
932 return 0;
933 }
934
935 /**
936 * e1000_reset_hw_82571 - Reset hardware
937 * @hw: pointer to the HW structure
938 *
939 * This resets the hardware into a known state.
940 **/
941 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
942 {
943 u32 ctrl, ctrl_ext, eecd, tctl;
944 s32 ret_val;
945
946 /* Prevent the PCI-E bus from sticking if there is no TLP connection
947 * on the last TLP read/write transaction when MAC is reset.
948 */
949 ret_val = e1000e_disable_pcie_master(hw);
950 if (ret_val)
951 e_dbg("PCI-E Master disable polling has failed.\n");
952
953 e_dbg("Masking off all interrupts\n");
954 ew32(IMC, 0xffffffff);
955
956 ew32(RCTL, 0);
957 tctl = er32(TCTL);
958 tctl &= ~E1000_TCTL_EN;
959 ew32(TCTL, tctl);
960 e1e_flush();
961
962 usleep_range(10000, 11000);
963
964 /* Must acquire the MDIO ownership before MAC reset.
965 * Ownership defaults to firmware after a reset.
966 */
967 switch (hw->mac.type) {
968 case e1000_82573:
969 ret_val = e1000_get_hw_semaphore_82573(hw);
970 break;
971 case e1000_82574:
972 case e1000_82583:
973 ret_val = e1000_get_hw_semaphore_82574(hw);
974 break;
975 default:
976 break;
977 }
978
979 ctrl = er32(CTRL);
980
981 e_dbg("Issuing a global reset to MAC\n");
982 ew32(CTRL, ctrl | E1000_CTRL_RST);
983
984 /* Must release MDIO ownership and mutex after MAC reset. */
985 switch (hw->mac.type) {
986 case e1000_82573:
987 /* Release mutex only if the hw semaphore is acquired */
988 if (!ret_val)
989 e1000_put_hw_semaphore_82573(hw);
990 break;
991 case e1000_82574:
992 case e1000_82583:
993 /* Release mutex only if the hw semaphore is acquired */
994 if (!ret_val)
995 e1000_put_hw_semaphore_82574(hw);
996 break;
997 default:
998 break;
999 }
1000
1001 if (hw->nvm.type == e1000_nvm_flash_hw) {
1002 usleep_range(10, 20);
1003 ctrl_ext = er32(CTRL_EXT);
1004 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1005 ew32(CTRL_EXT, ctrl_ext);
1006 e1e_flush();
1007 }
1008
1009 ret_val = e1000e_get_auto_rd_done(hw);
1010 if (ret_val)
1011 /* We don't want to continue accessing MAC registers. */
1012 return ret_val;
1013
1014 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1015 * Need to wait for Phy configuration completion before accessing
1016 * NVM and Phy.
1017 */
1018
1019 switch (hw->mac.type) {
1020 case e1000_82571:
1021 case e1000_82572:
1022 /* REQ and GNT bits need to be cleared when using AUTO_RD
1023 * to access the EEPROM.
1024 */
1025 eecd = er32(EECD);
1026 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1027 ew32(EECD, eecd);
1028 break;
1029 case e1000_82573:
1030 case e1000_82574:
1031 case e1000_82583:
1032 msleep(25);
1033 break;
1034 default:
1035 break;
1036 }
1037
1038 /* Clear any pending interrupt events. */
1039 ew32(IMC, 0xffffffff);
1040 er32(ICR);
1041
1042 if (hw->mac.type == e1000_82571) {
1043 /* Install any alternate MAC address into RAR0 */
1044 ret_val = e1000_check_alt_mac_addr_generic(hw);
1045 if (ret_val)
1046 return ret_val;
1047
1048 e1000e_set_laa_state_82571(hw, true);
1049 }
1050
1051 /* Reinitialize the 82571 serdes link state machine */
1052 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1053 hw->mac.serdes_link_state = e1000_serdes_link_down;
1054
1055 return 0;
1056 }
1057
1058 /**
1059 * e1000_init_hw_82571 - Initialize hardware
1060 * @hw: pointer to the HW structure
1061 *
1062 * This inits the hardware readying it for operation.
1063 **/
1064 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1065 {
1066 struct e1000_mac_info *mac = &hw->mac;
1067 u32 reg_data;
1068 s32 ret_val;
1069 u16 i, rar_count = mac->rar_entry_count;
1070
1071 e1000_initialize_hw_bits_82571(hw);
1072
1073 /* Initialize identification LED */
1074 ret_val = mac->ops.id_led_init(hw);
1075 /* An error is not fatal and we should not stop init due to this */
1076 if (ret_val)
1077 e_dbg("Error initializing identification LED\n");
1078
1079 /* Disabling VLAN filtering */
1080 e_dbg("Initializing the IEEE VLAN\n");
1081 mac->ops.clear_vfta(hw);
1082
1083 /* Setup the receive address.
1084 * If, however, a locally administered address was assigned to the
1085 * 82571, we must reserve a RAR for it to work around an issue where
1086 * resetting one port will reload the MAC on the other port.
1087 */
1088 if (e1000e_get_laa_state_82571(hw))
1089 rar_count--;
1090 e1000e_init_rx_addrs(hw, rar_count);
1091
1092 /* Zero out the Multicast HASH table */
1093 e_dbg("Zeroing the MTA\n");
1094 for (i = 0; i < mac->mta_reg_count; i++)
1095 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1096
1097 /* Setup link and flow control */
1098 ret_val = mac->ops.setup_link(hw);
1099
1100 /* Set the transmit descriptor write-back policy */
1101 reg_data = er32(TXDCTL(0));
1102 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1103 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1104 ew32(TXDCTL(0), reg_data);
1105
1106 /* ...for both queues. */
1107 switch (mac->type) {
1108 case e1000_82573:
1109 e1000e_enable_tx_pkt_filtering(hw);
1110 /* fall through */
1111 case e1000_82574:
1112 case e1000_82583:
1113 reg_data = er32(GCR);
1114 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1115 ew32(GCR, reg_data);
1116 break;
1117 default:
1118 reg_data = er32(TXDCTL(1));
1119 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1120 E1000_TXDCTL_FULL_TX_DESC_WB |
1121 E1000_TXDCTL_COUNT_DESC);
1122 ew32(TXDCTL(1), reg_data);
1123 break;
1124 }
1125
1126 /* Clear all of the statistics registers (clear on read). It is
1127 * important that we do this after we have tried to establish link
1128 * because the symbol error count will increment wildly if there
1129 * is no link.
1130 */
1131 e1000_clear_hw_cntrs_82571(hw);
1132
1133 return ret_val;
1134 }
1135
1136 /**
1137 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1138 * @hw: pointer to the HW structure
1139 *
1140 * Initializes required hardware-dependent bits needed for normal operation.
1141 **/
1142 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1143 {
1144 u32 reg;
1145
1146 /* Transmit Descriptor Control 0 */
1147 reg = er32(TXDCTL(0));
1148 reg |= BIT(22);
1149 ew32(TXDCTL(0), reg);
1150
1151 /* Transmit Descriptor Control 1 */
1152 reg = er32(TXDCTL(1));
1153 reg |= BIT(22);
1154 ew32(TXDCTL(1), reg);
1155
1156 /* Transmit Arbitration Control 0 */
1157 reg = er32(TARC(0));
1158 reg &= ~(0xF << 27); /* 30:27 */
1159 switch (hw->mac.type) {
1160 case e1000_82571:
1161 case e1000_82572:
1162 reg |= BIT(23) | BIT(24) | BIT(25) | BIT(26);
1163 break;
1164 case e1000_82574:
1165 case e1000_82583:
1166 reg |= BIT(26);
1167 break;
1168 default:
1169 break;
1170 }
1171 ew32(TARC(0), reg);
1172
1173 /* Transmit Arbitration Control 1 */
1174 reg = er32(TARC(1));
1175 switch (hw->mac.type) {
1176 case e1000_82571:
1177 case e1000_82572:
1178 reg &= ~(BIT(29) | BIT(30));
1179 reg |= BIT(22) | BIT(24) | BIT(25) | BIT(26);
1180 if (er32(TCTL) & E1000_TCTL_MULR)
1181 reg &= ~BIT(28);
1182 else
1183 reg |= BIT(28);
1184 ew32(TARC(1), reg);
1185 break;
1186 default:
1187 break;
1188 }
1189
1190 /* Device Control */
1191 switch (hw->mac.type) {
1192 case e1000_82573:
1193 case e1000_82574:
1194 case e1000_82583:
1195 reg = er32(CTRL);
1196 reg &= ~BIT(29);
1197 ew32(CTRL, reg);
1198 break;
1199 default:
1200 break;
1201 }
1202
1203 /* Extended Device Control */
1204 switch (hw->mac.type) {
1205 case e1000_82573:
1206 case e1000_82574:
1207 case e1000_82583:
1208 reg = er32(CTRL_EXT);
1209 reg &= ~BIT(23);
1210 reg |= BIT(22);
1211 ew32(CTRL_EXT, reg);
1212 break;
1213 default:
1214 break;
1215 }
1216
1217 if (hw->mac.type == e1000_82571) {
1218 reg = er32(PBA_ECC);
1219 reg |= E1000_PBA_ECC_CORR_EN;
1220 ew32(PBA_ECC, reg);
1221 }
1222
1223 /* Workaround for hardware errata.
1224 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1225 */
1226 if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) {
1227 reg = er32(CTRL_EXT);
1228 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1229 ew32(CTRL_EXT, reg);
1230 }
1231
1232 /* Disable IPv6 extension header parsing because some malformed
1233 * IPv6 headers can hang the Rx.
1234 */
1235 if (hw->mac.type <= e1000_82573) {
1236 reg = er32(RFCTL);
1237 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1238 ew32(RFCTL, reg);
1239 }
1240
1241 /* PCI-Ex Control Registers */
1242 switch (hw->mac.type) {
1243 case e1000_82574:
1244 case e1000_82583:
1245 reg = er32(GCR);
1246 reg |= BIT(22);
1247 ew32(GCR, reg);
1248
1249 /* Workaround for hardware errata.
1250 * apply workaround for hardware errata documented in errata
1251 * docs Fixes issue where some error prone or unreliable PCIe
1252 * completions are occurring, particularly with ASPM enabled.
1253 * Without fix, issue can cause Tx timeouts.
1254 */
1255 reg = er32(GCR2);
1256 reg |= 1;
1257 ew32(GCR2, reg);
1258 break;
1259 default:
1260 break;
1261 }
1262 }
1263
1264 /**
1265 * e1000_clear_vfta_82571 - Clear VLAN filter table
1266 * @hw: pointer to the HW structure
1267 *
1268 * Clears the register array which contains the VLAN filter table by
1269 * setting all the values to 0.
1270 **/
1271 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1272 {
1273 u32 offset;
1274 u32 vfta_value = 0;
1275 u32 vfta_offset = 0;
1276 u32 vfta_bit_in_reg = 0;
1277
1278 switch (hw->mac.type) {
1279 case e1000_82573:
1280 case e1000_82574:
1281 case e1000_82583:
1282 if (hw->mng_cookie.vlan_id != 0) {
1283 /* The VFTA is a 4096b bit-field, each identifying
1284 * a single VLAN ID. The following operations
1285 * determine which 32b entry (i.e. offset) into the
1286 * array we want to set the VLAN ID (i.e. bit) of
1287 * the manageability unit.
1288 */
1289 vfta_offset = (hw->mng_cookie.vlan_id >>
1290 E1000_VFTA_ENTRY_SHIFT) &
1291 E1000_VFTA_ENTRY_MASK;
1292 vfta_bit_in_reg =
1293 BIT(hw->mng_cookie.vlan_id &
1294 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1295 }
1296 break;
1297 default:
1298 break;
1299 }
1300 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1301 /* If the offset we want to clear is the same offset of the
1302 * manageability VLAN ID, then clear all bits except that of
1303 * the manageability unit.
1304 */
1305 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1306 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1307 e1e_flush();
1308 }
1309 }
1310
1311 /**
1312 * e1000_check_mng_mode_82574 - Check manageability is enabled
1313 * @hw: pointer to the HW structure
1314 *
1315 * Reads the NVM Initialization Control Word 2 and returns true
1316 * (>0) if any manageability is enabled, else false (0).
1317 **/
1318 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1319 {
1320 u16 data;
1321
1322 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1323 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1324 }
1325
1326 /**
1327 * e1000_led_on_82574 - Turn LED on
1328 * @hw: pointer to the HW structure
1329 *
1330 * Turn LED on.
1331 **/
1332 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1333 {
1334 u32 ctrl;
1335 u32 i;
1336
1337 ctrl = hw->mac.ledctl_mode2;
1338 if (!(E1000_STATUS_LU & er32(STATUS))) {
1339 /* If no link, then turn LED on by setting the invert bit
1340 * for each LED that's "on" (0x0E) in ledctl_mode2.
1341 */
1342 for (i = 0; i < 4; i++)
1343 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1344 E1000_LEDCTL_MODE_LED_ON)
1345 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1346 }
1347 ew32(LEDCTL, ctrl);
1348
1349 return 0;
1350 }
1351
1352 /**
1353 * e1000_check_phy_82574 - check 82574 phy hung state
1354 * @hw: pointer to the HW structure
1355 *
1356 * Returns whether phy is hung or not
1357 **/
1358 bool e1000_check_phy_82574(struct e1000_hw *hw)
1359 {
1360 u16 status_1kbt = 0;
1361 u16 receive_errors = 0;
1362 s32 ret_val;
1363
1364 /* Read PHY Receive Error counter first, if its is max - all F's then
1365 * read the Base1000T status register If both are max then PHY is hung.
1366 */
1367 ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
1368 if (ret_val)
1369 return false;
1370 if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1371 ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
1372 if (ret_val)
1373 return false;
1374 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1375 E1000_IDLE_ERROR_COUNT_MASK)
1376 return true;
1377 }
1378
1379 return false;
1380 }
1381
1382 /**
1383 * e1000_setup_link_82571 - Setup flow control and link settings
1384 * @hw: pointer to the HW structure
1385 *
1386 * Determines which flow control settings to use, then configures flow
1387 * control. Calls the appropriate media-specific link configuration
1388 * function. Assuming the adapter has a valid link partner, a valid link
1389 * should be established. Assumes the hardware has previously been reset
1390 * and the transmitter and receiver are not enabled.
1391 **/
1392 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1393 {
1394 /* 82573 does not have a word in the NVM to determine
1395 * the default flow control setting, so we explicitly
1396 * set it to full.
1397 */
1398 switch (hw->mac.type) {
1399 case e1000_82573:
1400 case e1000_82574:
1401 case e1000_82583:
1402 if (hw->fc.requested_mode == e1000_fc_default)
1403 hw->fc.requested_mode = e1000_fc_full;
1404 break;
1405 default:
1406 break;
1407 }
1408
1409 return e1000e_setup_link_generic(hw);
1410 }
1411
1412 /**
1413 * e1000_setup_copper_link_82571 - Configure copper link settings
1414 * @hw: pointer to the HW structure
1415 *
1416 * Configures the link for auto-neg or forced speed and duplex. Then we check
1417 * for link, once link is established calls to configure collision distance
1418 * and flow control are called.
1419 **/
1420 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1421 {
1422 u32 ctrl;
1423 s32 ret_val;
1424
1425 ctrl = er32(CTRL);
1426 ctrl |= E1000_CTRL_SLU;
1427 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1428 ew32(CTRL, ctrl);
1429
1430 switch (hw->phy.type) {
1431 case e1000_phy_m88:
1432 case e1000_phy_bm:
1433 ret_val = e1000e_copper_link_setup_m88(hw);
1434 break;
1435 case e1000_phy_igp_2:
1436 ret_val = e1000e_copper_link_setup_igp(hw);
1437 break;
1438 default:
1439 return -E1000_ERR_PHY;
1440 }
1441
1442 if (ret_val)
1443 return ret_val;
1444
1445 return e1000e_setup_copper_link(hw);
1446 }
1447
1448 /**
1449 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1450 * @hw: pointer to the HW structure
1451 *
1452 * Configures collision distance and flow control for fiber and serdes links.
1453 * Upon successful setup, poll for link.
1454 **/
1455 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1456 {
1457 switch (hw->mac.type) {
1458 case e1000_82571:
1459 case e1000_82572:
1460 /* If SerDes loopback mode is entered, there is no form
1461 * of reset to take the adapter out of that mode. So we
1462 * have to explicitly take the adapter out of loopback
1463 * mode. This prevents drivers from twiddling their thumbs
1464 * if another tool failed to take it out of loopback mode.
1465 */
1466 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1467 break;
1468 default:
1469 break;
1470 }
1471
1472 return e1000e_setup_fiber_serdes_link(hw);
1473 }
1474
1475 /**
1476 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1477 * @hw: pointer to the HW structure
1478 *
1479 * Reports the link state as up or down.
1480 *
1481 * If autonegotiation is supported by the link partner, the link state is
1482 * determined by the result of autonegotiation. This is the most likely case.
1483 * If autonegotiation is not supported by the link partner, and the link
1484 * has a valid signal, force the link up.
1485 *
1486 * The link state is represented internally here by 4 states:
1487 *
1488 * 1) down
1489 * 2) autoneg_progress
1490 * 3) autoneg_complete (the link successfully autonegotiated)
1491 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1492 *
1493 **/
1494 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1495 {
1496 struct e1000_mac_info *mac = &hw->mac;
1497 u32 rxcw;
1498 u32 ctrl;
1499 u32 status;
1500 u32 txcw;
1501 u32 i;
1502 s32 ret_val = 0;
1503
1504 ctrl = er32(CTRL);
1505 status = er32(STATUS);
1506 er32(RXCW);
1507 /* SYNCH bit and IV bit are sticky */
1508 usleep_range(10, 20);
1509 rxcw = er32(RXCW);
1510
1511 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1512 /* Receiver is synchronized with no invalid bits. */
1513 switch (mac->serdes_link_state) {
1514 case e1000_serdes_link_autoneg_complete:
1515 if (!(status & E1000_STATUS_LU)) {
1516 /* We have lost link, retry autoneg before
1517 * reporting link failure
1518 */
1519 mac->serdes_link_state =
1520 e1000_serdes_link_autoneg_progress;
1521 mac->serdes_has_link = false;
1522 e_dbg("AN_UP -> AN_PROG\n");
1523 } else {
1524 mac->serdes_has_link = true;
1525 }
1526 break;
1527
1528 case e1000_serdes_link_forced_up:
1529 /* If we are receiving /C/ ordered sets, re-enable
1530 * auto-negotiation in the TXCW register and disable
1531 * forced link in the Device Control register in an
1532 * attempt to auto-negotiate with our link partner.
1533 */
1534 if (rxcw & E1000_RXCW_C) {
1535 /* Enable autoneg, and unforce link up */
1536 ew32(TXCW, mac->txcw);
1537 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1538 mac->serdes_link_state =
1539 e1000_serdes_link_autoneg_progress;
1540 mac->serdes_has_link = false;
1541 e_dbg("FORCED_UP -> AN_PROG\n");
1542 } else {
1543 mac->serdes_has_link = true;
1544 }
1545 break;
1546
1547 case e1000_serdes_link_autoneg_progress:
1548 if (rxcw & E1000_RXCW_C) {
1549 /* We received /C/ ordered sets, meaning the
1550 * link partner has autonegotiated, and we can
1551 * trust the Link Up (LU) status bit.
1552 */
1553 if (status & E1000_STATUS_LU) {
1554 mac->serdes_link_state =
1555 e1000_serdes_link_autoneg_complete;
1556 e_dbg("AN_PROG -> AN_UP\n");
1557 mac->serdes_has_link = true;
1558 } else {
1559 /* Autoneg completed, but failed. */
1560 mac->serdes_link_state =
1561 e1000_serdes_link_down;
1562 e_dbg("AN_PROG -> DOWN\n");
1563 }
1564 } else {
1565 /* The link partner did not autoneg.
1566 * Force link up and full duplex, and change
1567 * state to forced.
1568 */
1569 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1570 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1571 ew32(CTRL, ctrl);
1572
1573 /* Configure Flow Control after link up. */
1574 ret_val = e1000e_config_fc_after_link_up(hw);
1575 if (ret_val) {
1576 e_dbg("Error config flow control\n");
1577 break;
1578 }
1579 mac->serdes_link_state =
1580 e1000_serdes_link_forced_up;
1581 mac->serdes_has_link = true;
1582 e_dbg("AN_PROG -> FORCED_UP\n");
1583 }
1584 break;
1585
1586 case e1000_serdes_link_down:
1587 default:
1588 /* The link was down but the receiver has now gained
1589 * valid sync, so lets see if we can bring the link
1590 * up.
1591 */
1592 ew32(TXCW, mac->txcw);
1593 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1594 mac->serdes_link_state =
1595 e1000_serdes_link_autoneg_progress;
1596 mac->serdes_has_link = false;
1597 e_dbg("DOWN -> AN_PROG\n");
1598 break;
1599 }
1600 } else {
1601 if (!(rxcw & E1000_RXCW_SYNCH)) {
1602 mac->serdes_has_link = false;
1603 mac->serdes_link_state = e1000_serdes_link_down;
1604 e_dbg("ANYSTATE -> DOWN\n");
1605 } else {
1606 /* Check several times, if SYNCH bit and CONFIG
1607 * bit both are consistently 1 then simply ignore
1608 * the IV bit and restart Autoneg
1609 */
1610 for (i = 0; i < AN_RETRY_COUNT; i++) {
1611 usleep_range(10, 20);
1612 rxcw = er32(RXCW);
1613 if ((rxcw & E1000_RXCW_SYNCH) &&
1614 (rxcw & E1000_RXCW_C))
1615 continue;
1616
1617 if (rxcw & E1000_RXCW_IV) {
1618 mac->serdes_has_link = false;
1619 mac->serdes_link_state =
1620 e1000_serdes_link_down;
1621 e_dbg("ANYSTATE -> DOWN\n");
1622 break;
1623 }
1624 }
1625
1626 if (i == AN_RETRY_COUNT) {
1627 txcw = er32(TXCW);
1628 txcw |= E1000_TXCW_ANE;
1629 ew32(TXCW, txcw);
1630 mac->serdes_link_state =
1631 e1000_serdes_link_autoneg_progress;
1632 mac->serdes_has_link = false;
1633 e_dbg("ANYSTATE -> AN_PROG\n");
1634 }
1635 }
1636 }
1637
1638 return ret_val;
1639 }
1640
1641 /**
1642 * e1000_valid_led_default_82571 - Verify a valid default LED config
1643 * @hw: pointer to the HW structure
1644 * @data: pointer to the NVM (EEPROM)
1645 *
1646 * Read the EEPROM for the current default LED configuration. If the
1647 * LED configuration is not valid, set to a valid LED configuration.
1648 **/
1649 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1650 {
1651 s32 ret_val;
1652
1653 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1654 if (ret_val) {
1655 e_dbg("NVM Read Error\n");
1656 return ret_val;
1657 }
1658
1659 switch (hw->mac.type) {
1660 case e1000_82573:
1661 case e1000_82574:
1662 case e1000_82583:
1663 if (*data == ID_LED_RESERVED_F746)
1664 *data = ID_LED_DEFAULT_82573;
1665 break;
1666 default:
1667 if (*data == ID_LED_RESERVED_0000 ||
1668 *data == ID_LED_RESERVED_FFFF)
1669 *data = ID_LED_DEFAULT;
1670 break;
1671 }
1672
1673 return 0;
1674 }
1675
1676 /**
1677 * e1000e_get_laa_state_82571 - Get locally administered address state
1678 * @hw: pointer to the HW structure
1679 *
1680 * Retrieve and return the current locally administered address state.
1681 **/
1682 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1683 {
1684 if (hw->mac.type != e1000_82571)
1685 return false;
1686
1687 return hw->dev_spec.e82571.laa_is_present;
1688 }
1689
1690 /**
1691 * e1000e_set_laa_state_82571 - Set locally administered address state
1692 * @hw: pointer to the HW structure
1693 * @state: enable/disable locally administered address
1694 *
1695 * Enable/Disable the current locally administered address state.
1696 **/
1697 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1698 {
1699 if (hw->mac.type != e1000_82571)
1700 return;
1701
1702 hw->dev_spec.e82571.laa_is_present = state;
1703
1704 /* If workaround is activated... */
1705 if (state)
1706 /* Hold a copy of the LAA in RAR[14] This is done so that
1707 * between the time RAR[0] gets clobbered and the time it
1708 * gets fixed, the actual LAA is in one of the RARs and no
1709 * incoming packets directed to this port are dropped.
1710 * Eventually the LAA will be in RAR[0] and RAR[14].
1711 */
1712 hw->mac.ops.rar_set(hw, hw->mac.addr,
1713 hw->mac.rar_entry_count - 1);
1714 }
1715
1716 /**
1717 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1718 * @hw: pointer to the HW structure
1719 *
1720 * Verifies that the EEPROM has completed the update. After updating the
1721 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1722 * the checksum fix is not implemented, we need to set the bit and update
1723 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1724 * we need to return bad checksum.
1725 **/
1726 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1727 {
1728 struct e1000_nvm_info *nvm = &hw->nvm;
1729 s32 ret_val;
1730 u16 data;
1731
1732 if (nvm->type != e1000_nvm_flash_hw)
1733 return 0;
1734
1735 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
1736 * 10h-12h. Checksum may need to be fixed.
1737 */
1738 ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1739 if (ret_val)
1740 return ret_val;
1741
1742 if (!(data & 0x10)) {
1743 /* Read 0x23 and check bit 15. This bit is a 1
1744 * when the checksum has already been fixed. If
1745 * the checksum is still wrong and this bit is a
1746 * 1, we need to return bad checksum. Otherwise,
1747 * we need to set this bit to a 1 and update the
1748 * checksum.
1749 */
1750 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1751 if (ret_val)
1752 return ret_val;
1753
1754 if (!(data & 0x8000)) {
1755 data |= 0x8000;
1756 ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1757 if (ret_val)
1758 return ret_val;
1759 ret_val = e1000e_update_nvm_checksum(hw);
1760 if (ret_val)
1761 return ret_val;
1762 }
1763 }
1764
1765 return 0;
1766 }
1767
1768 /**
1769 * e1000_read_mac_addr_82571 - Read device MAC address
1770 * @hw: pointer to the HW structure
1771 **/
1772 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1773 {
1774 if (hw->mac.type == e1000_82571) {
1775 s32 ret_val;
1776
1777 /* If there's an alternate MAC address place it in RAR0
1778 * so that it will override the Si installed default perm
1779 * address.
1780 */
1781 ret_val = e1000_check_alt_mac_addr_generic(hw);
1782 if (ret_val)
1783 return ret_val;
1784 }
1785
1786 return e1000_read_mac_addr_generic(hw);
1787 }
1788
1789 /**
1790 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1791 * @hw: pointer to the HW structure
1792 *
1793 * In the case of a PHY power down to save power, or to turn off link during a
1794 * driver unload, or wake on lan is not enabled, remove the link.
1795 **/
1796 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1797 {
1798 struct e1000_phy_info *phy = &hw->phy;
1799 struct e1000_mac_info *mac = &hw->mac;
1800
1801 if (!phy->ops.check_reset_block)
1802 return;
1803
1804 /* If the management interface is not enabled, then power down */
1805 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1806 e1000_power_down_phy_copper(hw);
1807 }
1808
1809 /**
1810 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1811 * @hw: pointer to the HW structure
1812 *
1813 * Clears the hardware counters by reading the counter registers.
1814 **/
1815 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1816 {
1817 e1000e_clear_hw_cntrs_base(hw);
1818
1819 er32(PRC64);
1820 er32(PRC127);
1821 er32(PRC255);
1822 er32(PRC511);
1823 er32(PRC1023);
1824 er32(PRC1522);
1825 er32(PTC64);
1826 er32(PTC127);
1827 er32(PTC255);
1828 er32(PTC511);
1829 er32(PTC1023);
1830 er32(PTC1522);
1831
1832 er32(ALGNERRC);
1833 er32(RXERRC);
1834 er32(TNCRS);
1835 er32(CEXTERR);
1836 er32(TSCTC);
1837 er32(TSCTFC);
1838
1839 er32(MGTPRC);
1840 er32(MGTPDC);
1841 er32(MGTPTC);
1842
1843 er32(IAC);
1844 er32(ICRXOC);
1845
1846 er32(ICRXPTC);
1847 er32(ICRXATC);
1848 er32(ICTXPTC);
1849 er32(ICTXATC);
1850 er32(ICTXQEC);
1851 er32(ICTXQMTC);
1852 er32(ICRXDMTC);
1853 }
1854
1855 static const struct e1000_mac_operations e82571_mac_ops = {
1856 /* .check_mng_mode: mac type dependent */
1857 /* .check_for_link: media type dependent */
1858 .id_led_init = e1000e_id_led_init_generic,
1859 .cleanup_led = e1000e_cleanup_led_generic,
1860 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571,
1861 .get_bus_info = e1000e_get_bus_info_pcie,
1862 .set_lan_id = e1000_set_lan_id_multi_port_pcie,
1863 /* .get_link_up_info: media type dependent */
1864 /* .led_on: mac type dependent */
1865 .led_off = e1000e_led_off_generic,
1866 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1867 .write_vfta = e1000_write_vfta_generic,
1868 .clear_vfta = e1000_clear_vfta_82571,
1869 .reset_hw = e1000_reset_hw_82571,
1870 .init_hw = e1000_init_hw_82571,
1871 .setup_link = e1000_setup_link_82571,
1872 /* .setup_physical_interface: media type dependent */
1873 .setup_led = e1000e_setup_led_generic,
1874 .config_collision_dist = e1000e_config_collision_dist_generic,
1875 .read_mac_addr = e1000_read_mac_addr_82571,
1876 .rar_set = e1000e_rar_set_generic,
1877 .rar_get_count = e1000e_rar_get_count_generic,
1878 };
1879
1880 static const struct e1000_phy_operations e82_phy_ops_igp = {
1881 .acquire = e1000_get_hw_semaphore_82571,
1882 .check_polarity = e1000_check_polarity_igp,
1883 .check_reset_block = e1000e_check_reset_block_generic,
1884 .commit = NULL,
1885 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp,
1886 .get_cfg_done = e1000_get_cfg_done_82571,
1887 .get_cable_length = e1000e_get_cable_length_igp_2,
1888 .get_info = e1000e_get_phy_info_igp,
1889 .read_reg = e1000e_read_phy_reg_igp,
1890 .release = e1000_put_hw_semaphore_82571,
1891 .reset = e1000e_phy_hw_reset_generic,
1892 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1893 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1894 .write_reg = e1000e_write_phy_reg_igp,
1895 .cfg_on_link_up = NULL,
1896 };
1897
1898 static const struct e1000_phy_operations e82_phy_ops_m88 = {
1899 .acquire = e1000_get_hw_semaphore_82571,
1900 .check_polarity = e1000_check_polarity_m88,
1901 .check_reset_block = e1000e_check_reset_block_generic,
1902 .commit = e1000e_phy_sw_reset,
1903 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1904 .get_cfg_done = e1000e_get_cfg_done_generic,
1905 .get_cable_length = e1000e_get_cable_length_m88,
1906 .get_info = e1000e_get_phy_info_m88,
1907 .read_reg = e1000e_read_phy_reg_m88,
1908 .release = e1000_put_hw_semaphore_82571,
1909 .reset = e1000e_phy_hw_reset_generic,
1910 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1911 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1912 .write_reg = e1000e_write_phy_reg_m88,
1913 .cfg_on_link_up = NULL,
1914 };
1915
1916 static const struct e1000_phy_operations e82_phy_ops_bm = {
1917 .acquire = e1000_get_hw_semaphore_82571,
1918 .check_polarity = e1000_check_polarity_m88,
1919 .check_reset_block = e1000e_check_reset_block_generic,
1920 .commit = e1000e_phy_sw_reset,
1921 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1922 .get_cfg_done = e1000e_get_cfg_done_generic,
1923 .get_cable_length = e1000e_get_cable_length_m88,
1924 .get_info = e1000e_get_phy_info_m88,
1925 .read_reg = e1000e_read_phy_reg_bm2,
1926 .release = e1000_put_hw_semaphore_82571,
1927 .reset = e1000e_phy_hw_reset_generic,
1928 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1929 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1930 .write_reg = e1000e_write_phy_reg_bm2,
1931 .cfg_on_link_up = NULL,
1932 };
1933
1934 static const struct e1000_nvm_operations e82571_nvm_ops = {
1935 .acquire = e1000_acquire_nvm_82571,
1936 .read = e1000e_read_nvm_eerd,
1937 .release = e1000_release_nvm_82571,
1938 .reload = e1000e_reload_nvm_generic,
1939 .update = e1000_update_nvm_checksum_82571,
1940 .valid_led_default = e1000_valid_led_default_82571,
1941 .validate = e1000_validate_nvm_checksum_82571,
1942 .write = e1000_write_nvm_82571,
1943 };
1944
1945 const struct e1000_info e1000_82571_info = {
1946 .mac = e1000_82571,
1947 .flags = FLAG_HAS_HW_VLAN_FILTER
1948 | FLAG_HAS_JUMBO_FRAMES
1949 | FLAG_HAS_WOL
1950 | FLAG_APME_IN_CTRL3
1951 | FLAG_HAS_CTRLEXT_ON_LOAD
1952 | FLAG_HAS_SMART_POWER_DOWN
1953 | FLAG_RESET_OVERWRITES_LAA /* errata */
1954 | FLAG_TARC_SPEED_MODE_BIT /* errata */
1955 | FLAG_APME_CHECK_PORT_B,
1956 .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
1957 | FLAG2_DMA_BURST,
1958 .pba = 38,
1959 .max_hw_frame_size = DEFAULT_JUMBO,
1960 .get_variants = e1000_get_variants_82571,
1961 .mac_ops = &e82571_mac_ops,
1962 .phy_ops = &e82_phy_ops_igp,
1963 .nvm_ops = &e82571_nvm_ops,
1964 };
1965
1966 const struct e1000_info e1000_82572_info = {
1967 .mac = e1000_82572,
1968 .flags = FLAG_HAS_HW_VLAN_FILTER
1969 | FLAG_HAS_JUMBO_FRAMES
1970 | FLAG_HAS_WOL
1971 | FLAG_APME_IN_CTRL3
1972 | FLAG_HAS_CTRLEXT_ON_LOAD
1973 | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1974 .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
1975 | FLAG2_DMA_BURST,
1976 .pba = 38,
1977 .max_hw_frame_size = DEFAULT_JUMBO,
1978 .get_variants = e1000_get_variants_82571,
1979 .mac_ops = &e82571_mac_ops,
1980 .phy_ops = &e82_phy_ops_igp,
1981 .nvm_ops = &e82571_nvm_ops,
1982 };
1983
1984 const struct e1000_info e1000_82573_info = {
1985 .mac = e1000_82573,
1986 .flags = FLAG_HAS_HW_VLAN_FILTER
1987 | FLAG_HAS_WOL
1988 | FLAG_APME_IN_CTRL3
1989 | FLAG_HAS_SMART_POWER_DOWN
1990 | FLAG_HAS_AMT
1991 | FLAG_HAS_SWSM_ON_LOAD,
1992 .flags2 = FLAG2_DISABLE_ASPM_L1
1993 | FLAG2_DISABLE_ASPM_L0S,
1994 .pba = 20,
1995 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
1996 .get_variants = e1000_get_variants_82571,
1997 .mac_ops = &e82571_mac_ops,
1998 .phy_ops = &e82_phy_ops_m88,
1999 .nvm_ops = &e82571_nvm_ops,
2000 };
2001
2002 const struct e1000_info e1000_82574_info = {
2003 .mac = e1000_82574,
2004 .flags = FLAG_HAS_HW_VLAN_FILTER
2005 | FLAG_HAS_MSIX
2006 | FLAG_HAS_JUMBO_FRAMES
2007 | FLAG_HAS_WOL
2008 | FLAG_HAS_HW_TIMESTAMP
2009 | FLAG_APME_IN_CTRL3
2010 | FLAG_HAS_SMART_POWER_DOWN
2011 | FLAG_HAS_AMT
2012 | FLAG_HAS_CTRLEXT_ON_LOAD,
2013 .flags2 = FLAG2_CHECK_PHY_HANG
2014 | FLAG2_DISABLE_ASPM_L0S
2015 | FLAG2_DISABLE_ASPM_L1
2016 | FLAG2_NO_DISABLE_RX
2017 | FLAG2_DMA_BURST
2018 | FLAG2_CHECK_SYSTIM_OVERFLOW,
2019 .pba = 32,
2020 .max_hw_frame_size = DEFAULT_JUMBO,
2021 .get_variants = e1000_get_variants_82571,
2022 .mac_ops = &e82571_mac_ops,
2023 .phy_ops = &e82_phy_ops_bm,
2024 .nvm_ops = &e82571_nvm_ops,
2025 };
2026
2027 const struct e1000_info e1000_82583_info = {
2028 .mac = e1000_82583,
2029 .flags = FLAG_HAS_HW_VLAN_FILTER
2030 | FLAG_HAS_WOL
2031 | FLAG_HAS_HW_TIMESTAMP
2032 | FLAG_APME_IN_CTRL3
2033 | FLAG_HAS_SMART_POWER_DOWN
2034 | FLAG_HAS_AMT
2035 | FLAG_HAS_JUMBO_FRAMES
2036 | FLAG_HAS_CTRLEXT_ON_LOAD,
2037 .flags2 = FLAG2_DISABLE_ASPM_L0S
2038 | FLAG2_DISABLE_ASPM_L1
2039 | FLAG2_NO_DISABLE_RX
2040 | FLAG2_CHECK_SYSTIM_OVERFLOW,
2041 .pba = 32,
2042 .max_hw_frame_size = DEFAULT_JUMBO,
2043 .get_variants = e1000_get_variants_82571,
2044 .mac_ops = &e82571_mac_ops,
2045 .phy_ops = &e82_phy_ops_bm,
2046 .nvm_ops = &e82571_nvm_ops,
2047 };
Linux with added FPC-III support