drivers/net/ethernet/intel/ice/ice_flow.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c) 2019, Intel Corporation. */
   3
   4 #ifndef _ICE_FLOW_H_
   5 #define _ICE_FLOW_H_
   6
   7 #define ICE_FLOW_ENTRY_HANDLE_INVAL     0
   8 #define ICE_FLOW_FLD_OFF_INVAL          0xffff
   9
  10 /* Generate flow hash field from flow field type(s) */
  11 #define ICE_FLOW_HASH_IPV4      \
  12         (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
  13          BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
  14 #define ICE_FLOW_HASH_IPV6      \
  15         (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
  16          BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA))
  17 #define ICE_FLOW_HASH_TCP_PORT  \
  18         (BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT) | \
  19          BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))
  20 #define ICE_FLOW_HASH_UDP_PORT  \
  21         (BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT) | \
  22          BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))
  23 #define ICE_FLOW_HASH_SCTP_PORT \
  24         (BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT) | \
  25          BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_DST_PORT))
  26
  27 #define ICE_HASH_INVALID        0
  28 #define ICE_HASH_TCP_IPV4       (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_TCP_PORT)
  29 #define ICE_HASH_TCP_IPV6       (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_TCP_PORT)
  30 #define ICE_HASH_UDP_IPV4       (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_UDP_PORT)
  31 #define ICE_HASH_UDP_IPV6       (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_UDP_PORT)
  32
  33 /* Protocol header fields within a packet segment. A segment consists of one or
  34  * more protocol headers that make up a logical group of protocol headers. Each
  35  * logical group of protocol headers encapsulates or is encapsulated using/by
  36  * tunneling or encapsulation protocols for network virtualization such as GRE,
  37  * VxLAN, etc.
  38  */
  39 enum ice_flow_seg_hdr {
  40         ICE_FLOW_SEG_HDR_NONE           = 0x00000000,
  41         ICE_FLOW_SEG_HDR_IPV4           = 0x00000004,
  42         ICE_FLOW_SEG_HDR_IPV6           = 0x00000008,
  43         ICE_FLOW_SEG_HDR_TCP            = 0x00000040,
  44         ICE_FLOW_SEG_HDR_UDP            = 0x00000080,
  45         ICE_FLOW_SEG_HDR_SCTP           = 0x00000100,
  46 };
  47
  48 enum ice_flow_field {
  49         /* L3 */
  50         ICE_FLOW_FIELD_IDX_IPV4_SA,
  51         ICE_FLOW_FIELD_IDX_IPV4_DA,
  52         ICE_FLOW_FIELD_IDX_IPV6_SA,
  53         ICE_FLOW_FIELD_IDX_IPV6_DA,
  54         /* L4 */
  55         ICE_FLOW_FIELD_IDX_TCP_SRC_PORT,
  56         ICE_FLOW_FIELD_IDX_TCP_DST_PORT,
  57         ICE_FLOW_FIELD_IDX_UDP_SRC_PORT,
  58         ICE_FLOW_FIELD_IDX_UDP_DST_PORT,
  59         ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT,
  60         ICE_FLOW_FIELD_IDX_SCTP_DST_PORT,
  61         /* The total number of enums must not exceed 64 */
  62         ICE_FLOW_FIELD_IDX_MAX
  63 };
  64
  65 /* Flow headers and fields for AVF support */
  66 enum ice_flow_avf_hdr_field {
  67         /* Values 0 - 28 are reserved for future use */
  68         ICE_AVF_FLOW_FIELD_INVALID              = 0,
  69         ICE_AVF_FLOW_FIELD_UNICAST_IPV4_UDP     = 29,
  70         ICE_AVF_FLOW_FIELD_MULTICAST_IPV4_UDP,
  71         ICE_AVF_FLOW_FIELD_IPV4_UDP,
  72         ICE_AVF_FLOW_FIELD_IPV4_TCP_SYN_NO_ACK,
  73         ICE_AVF_FLOW_FIELD_IPV4_TCP,
  74         ICE_AVF_FLOW_FIELD_IPV4_SCTP,
  75         ICE_AVF_FLOW_FIELD_IPV4_OTHER,
  76         ICE_AVF_FLOW_FIELD_FRAG_IPV4,
  77         /* Values 37-38 are reserved */
  78         ICE_AVF_FLOW_FIELD_UNICAST_IPV6_UDP     = 39,
  79         ICE_AVF_FLOW_FIELD_MULTICAST_IPV6_UDP,
  80         ICE_AVF_FLOW_FIELD_IPV6_UDP,
  81         ICE_AVF_FLOW_FIELD_IPV6_TCP_SYN_NO_ACK,
  82         ICE_AVF_FLOW_FIELD_IPV6_TCP,
  83         ICE_AVF_FLOW_FIELD_IPV6_SCTP,
  84         ICE_AVF_FLOW_FIELD_IPV6_OTHER,
  85         ICE_AVF_FLOW_FIELD_FRAG_IPV6,
  86         ICE_AVF_FLOW_FIELD_RSVD47,
  87         ICE_AVF_FLOW_FIELD_FCOE_OX,
  88         ICE_AVF_FLOW_FIELD_FCOE_RX,
  89         ICE_AVF_FLOW_FIELD_FCOE_OTHER,
  90         /* Values 51-62 are reserved */
  91         ICE_AVF_FLOW_FIELD_L2_PAYLOAD           = 63,
  92         ICE_AVF_FLOW_FIELD_MAX
  93 };
  94
  95 /* Supported RSS offloads  This macro is defined to support
  96  * VIRTCHNL_OP_GET_RSS_HENA_CAPS ops. PF driver sends the RSS hardware
  97  * capabilities to the caller of this ops.
  98  */
  99 #define ICE_DEFAULT_RSS_HENA ( \
 100         BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_UDP) | \
 101         BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_SCTP) | \
 102         BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_TCP) | \
 103         BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_OTHER) | \
 104         BIT_ULL(ICE_AVF_FLOW_FIELD_FRAG_IPV4) | \
 105         BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_UDP) | \
 106         BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_TCP) | \
 107         BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_SCTP) | \
 108         BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_OTHER) | \
 109         BIT_ULL(ICE_AVF_FLOW_FIELD_FRAG_IPV6) | \
 110         BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_TCP_SYN_NO_ACK) | \
 111         BIT_ULL(ICE_AVF_FLOW_FIELD_UNICAST_IPV4_UDP) | \
 112         BIT_ULL(ICE_AVF_FLOW_FIELD_MULTICAST_IPV4_UDP) | \
 113         BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_TCP_SYN_NO_ACK) | \
 114         BIT_ULL(ICE_AVF_FLOW_FIELD_UNICAST_IPV6_UDP) | \
 115         BIT_ULL(ICE_AVF_FLOW_FIELD_MULTICAST_IPV6_UDP))
 116
 117 enum ice_flow_dir {
 118         ICE_FLOW_RX             = 0x02,
 119 };
 120
 121 enum ice_flow_priority {
 122         ICE_FLOW_PRIO_LOW,
 123         ICE_FLOW_PRIO_NORMAL,
 124         ICE_FLOW_PRIO_HIGH
 125 };
 126
 127 #define ICE_FLOW_SEG_MAX                2
 128 #define ICE_FLOW_FV_EXTRACT_SZ          2
 129
 130 #define ICE_FLOW_SET_HDRS(seg, val)     ((seg)->hdrs |= (u32)(val))
 131
 132 struct ice_flow_seg_xtrct {
 133         u8 prot_id;     /* Protocol ID of extracted header field */
 134         u16 off;        /* Starting offset of the field in header in bytes */
 135         u8 idx;         /* Index of FV entry used */
 136         u8 disp;        /* Displacement of field in bits fr. FV entry's start */
 137 };
 138
 139 enum ice_flow_fld_match_type {
 140         ICE_FLOW_FLD_TYPE_REG,          /* Value, mask */
 141         ICE_FLOW_FLD_TYPE_RANGE,        /* Value, mask, last (upper bound) */
 142         ICE_FLOW_FLD_TYPE_PREFIX,       /* IP address, prefix, size of prefix */
 143         ICE_FLOW_FLD_TYPE_SIZE,         /* Value, mask, size of match */
 144 };
 145
 146 struct ice_flow_fld_loc {
 147         /* Describe offsets of field information relative to the beginning of
 148          * input buffer provided when adding flow entries.
 149          */
 150         u16 val;        /* Offset where the value is located */
 151         u16 mask;       /* Offset where the mask/prefix value is located */
 152         u16 last;       /* Length or offset where the upper value is located */
 153 };
 154
 155 struct ice_flow_fld_info {
 156         enum ice_flow_fld_match_type type;
 157         /* Location where to retrieve data from an input buffer */
 158         struct ice_flow_fld_loc src;
 159         /* Location where to put the data into the final entry buffer */
 160         struct ice_flow_fld_loc entry;
 161         struct ice_flow_seg_xtrct xtrct;
 162 };
 163
 164 struct ice_flow_seg_info {
 165         u32 hdrs;       /* Bitmask indicating protocol headers present */
 166         u64 match;      /* Bitmask indicating header fields to be matched */
 167         u64 range;      /* Bitmask indicating header fields matched as ranges */
 168
 169         struct ice_flow_fld_info fields[ICE_FLOW_FIELD_IDX_MAX];
 170 };
 171
 172 struct ice_flow_prof {
 173         struct list_head l_entry;
 174
 175         u64 id;
 176         enum ice_flow_dir dir;
 177         u8 segs_cnt;
 178
 179         /* Keep track of flow entries associated with this flow profile */
 180         struct mutex entries_lock;
 181         struct list_head entries;
 182
 183         struct ice_flow_seg_info segs[ICE_FLOW_SEG_MAX];
 184
 185         /* software VSI handles referenced by this flow profile */
 186         DECLARE_BITMAP(vsis, ICE_MAX_VSI);
 187 };
 188
 189 struct ice_rss_cfg {
 190         struct list_head l_entry;
 191         /* bitmap of VSIs added to the RSS entry */
 192         DECLARE_BITMAP(vsis, ICE_MAX_VSI);
 193         u64 hashed_flds;
 194         u32 packet_hdr;
 195 };
 196
 197 enum ice_status ice_flow_rem_entry(struct ice_hw *hw, u64 entry_h);
 198 void ice_rem_vsi_rss_list(struct ice_hw *hw, u16 vsi_handle);
 199 enum ice_status ice_replay_rss_cfg(struct ice_hw *hw, u16 vsi_handle);
 200 enum ice_status
 201 ice_add_avf_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds);
 202 enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle);
 203 enum ice_status
 204 ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
 205                 u32 addl_hdrs);
 206 u64 ice_get_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u32 hdrs);
 207 #endif /* _ICE_FLOW_H_ */