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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / net / ethernet / rocker / rocker_hw.h
blob59f1f8b690d2c4836d14eb9e503f1de79ca1dcb7
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * drivers/net/ethernet/rocker/rocker_hw.h - Rocker switch device driver
4 * Copyright (c) 2014-2016 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2014 Scott Feldman <sfeldma@gmail.com>
6 */
7
8 #ifndef _ROCKER_HW_H
9 #define _ROCKER_HW_H
10
11 #include <linux/types.h>
12
13 /* Return codes */
14 enum {
15 ROCKER_OK = 0,
16 ROCKER_ENOENT = 2,
17 ROCKER_ENXIO = 6,
18 ROCKER_ENOMEM = 12,
19 ROCKER_EEXIST = 17,
20 ROCKER_EINVAL = 22,
21 ROCKER_EMSGSIZE = 90,
22 ROCKER_ENOTSUP = 95,
23 ROCKER_ENOBUFS = 105,
24 };
25
26 #define ROCKER_FP_PORTS_MAX 62
27
28 #define PCI_VENDOR_ID_REDHAT 0x1b36
29 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
30
31 #define ROCKER_PCI_BAR0_SIZE 0x2000
32
33 /* MSI-X vectors */
34 enum {
35 ROCKER_MSIX_VEC_CMD,
36 ROCKER_MSIX_VEC_EVENT,
37 ROCKER_MSIX_VEC_TEST,
38 ROCKER_MSIX_VEC_RESERVED0,
39 __ROCKER_MSIX_VEC_TX,
40 __ROCKER_MSIX_VEC_RX,
41 #define ROCKER_MSIX_VEC_TX(port) \
42 (__ROCKER_MSIX_VEC_TX + ((port) * 2))
43 #define ROCKER_MSIX_VEC_RX(port) \
44 (__ROCKER_MSIX_VEC_RX + ((port) * 2))
45 #define ROCKER_MSIX_VEC_COUNT(portcnt) \
46 (ROCKER_MSIX_VEC_RX((portcnt - 1)) + 1)
47 };
48
49 /* Rocker bogus registers */
50 #define ROCKER_BOGUS_REG0 0x0000
51 #define ROCKER_BOGUS_REG1 0x0004
52 #define ROCKER_BOGUS_REG2 0x0008
53 #define ROCKER_BOGUS_REG3 0x000c
54
55 /* Rocker test registers */
56 #define ROCKER_TEST_REG 0x0010
57 #define ROCKER_TEST_REG64 0x0018 /* 8-byte */
58 #define ROCKER_TEST_IRQ 0x0020
59 #define ROCKER_TEST_DMA_ADDR 0x0028 /* 8-byte */
60 #define ROCKER_TEST_DMA_SIZE 0x0030
61 #define ROCKER_TEST_DMA_CTRL 0x0034
62
63 /* Rocker test register ctrl */
64 #define ROCKER_TEST_DMA_CTRL_CLEAR BIT(0)
65 #define ROCKER_TEST_DMA_CTRL_FILL BIT(1)
66 #define ROCKER_TEST_DMA_CTRL_INVERT BIT(2)
67
68 /* Rocker DMA ring register offsets */
69 #define ROCKER_DMA_DESC_ADDR(x) (0x1000 + (x) * 32) /* 8-byte */
70 #define ROCKER_DMA_DESC_SIZE(x) (0x1008 + (x) * 32)
71 #define ROCKER_DMA_DESC_HEAD(x) (0x100c + (x) * 32)
72 #define ROCKER_DMA_DESC_TAIL(x) (0x1010 + (x) * 32)
73 #define ROCKER_DMA_DESC_CTRL(x) (0x1014 + (x) * 32)
74 #define ROCKER_DMA_DESC_CREDITS(x) (0x1018 + (x) * 32)
75 #define ROCKER_DMA_DESC_RES1(x) (0x101c + (x) * 32)
76
77 /* Rocker dma ctrl register bits */
78 #define ROCKER_DMA_DESC_CTRL_RESET BIT(0)
79
80 /* Rocker DMA ring types */
81 enum rocker_dma_type {
82 ROCKER_DMA_CMD,
83 ROCKER_DMA_EVENT,
84 __ROCKER_DMA_TX,
85 __ROCKER_DMA_RX,
86 #define ROCKER_DMA_TX(port) (__ROCKER_DMA_TX + (port) * 2)
87 #define ROCKER_DMA_RX(port) (__ROCKER_DMA_RX + (port) * 2)
88 };
89
90 /* Rocker DMA ring size limits and default sizes */
91 #define ROCKER_DMA_SIZE_MIN 2ul
92 #define ROCKER_DMA_SIZE_MAX 65536ul
93 #define ROCKER_DMA_CMD_DEFAULT_SIZE 32ul
94 #define ROCKER_DMA_EVENT_DEFAULT_SIZE 32ul
95 #define ROCKER_DMA_TX_DEFAULT_SIZE 64ul
96 #define ROCKER_DMA_TX_DESC_SIZE 256
97 #define ROCKER_DMA_RX_DEFAULT_SIZE 64ul
98 #define ROCKER_DMA_RX_DESC_SIZE 256
99
100 /* Rocker DMA descriptor struct */
101 struct rocker_desc {
102 u64 buf_addr;
103 u64 cookie;
104 u16 buf_size;
105 u16 tlv_size;
106 u16 resv[5];
107 u16 comp_err;
108 };
109
110 #define ROCKER_DMA_DESC_COMP_ERR_GEN BIT(15)
111
112 /* Rocker DMA TLV struct */
113 struct rocker_tlv {
114 u32 type;
115 u16 len;
116 };
117
118 /* TLVs */
119 enum {
120 ROCKER_TLV_CMD_UNSPEC,
121 ROCKER_TLV_CMD_TYPE, /* u16 */
122 ROCKER_TLV_CMD_INFO, /* nest */
123
124 __ROCKER_TLV_CMD_MAX,
125 ROCKER_TLV_CMD_MAX = __ROCKER_TLV_CMD_MAX - 1,
126 };
127
128 enum {
129 ROCKER_TLV_CMD_TYPE_UNSPEC,
130 ROCKER_TLV_CMD_TYPE_GET_PORT_SETTINGS,
131 ROCKER_TLV_CMD_TYPE_SET_PORT_SETTINGS,
132 ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_ADD,
133 ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_MOD,
134 ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_DEL,
135 ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_GET_STATS,
136 ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_ADD,
137 ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_MOD,
138 ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_DEL,
139 ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_GET_STATS,
140
141 ROCKER_TLV_CMD_TYPE_CLEAR_PORT_STATS,
142 ROCKER_TLV_CMD_TYPE_GET_PORT_STATS,
143
144 __ROCKER_TLV_CMD_TYPE_MAX,
145 ROCKER_TLV_CMD_TYPE_MAX = __ROCKER_TLV_CMD_TYPE_MAX - 1,
146 };
147
148 enum {
149 ROCKER_TLV_CMD_PORT_SETTINGS_UNSPEC,
150 ROCKER_TLV_CMD_PORT_SETTINGS_PPORT, /* u32 */
151 ROCKER_TLV_CMD_PORT_SETTINGS_SPEED, /* u32 */
152 ROCKER_TLV_CMD_PORT_SETTINGS_DUPLEX, /* u8 */
153 ROCKER_TLV_CMD_PORT_SETTINGS_AUTONEG, /* u8 */
154 ROCKER_TLV_CMD_PORT_SETTINGS_MACADDR, /* binary */
155 ROCKER_TLV_CMD_PORT_SETTINGS_MODE, /* u8 */
156 ROCKER_TLV_CMD_PORT_SETTINGS_LEARNING, /* u8 */
157 ROCKER_TLV_CMD_PORT_SETTINGS_PHYS_NAME, /* binary */
158 ROCKER_TLV_CMD_PORT_SETTINGS_MTU, /* u16 */
159
160 __ROCKER_TLV_CMD_PORT_SETTINGS_MAX,
161 ROCKER_TLV_CMD_PORT_SETTINGS_MAX =
162 __ROCKER_TLV_CMD_PORT_SETTINGS_MAX - 1,
163 };
164
165 enum {
166 ROCKER_TLV_CMD_PORT_STATS_UNSPEC,
167 ROCKER_TLV_CMD_PORT_STATS_PPORT, /* u32 */
168
169 ROCKER_TLV_CMD_PORT_STATS_RX_PKTS, /* u64 */
170 ROCKER_TLV_CMD_PORT_STATS_RX_BYTES, /* u64 */
171 ROCKER_TLV_CMD_PORT_STATS_RX_DROPPED, /* u64 */
172 ROCKER_TLV_CMD_PORT_STATS_RX_ERRORS, /* u64 */
173
174 ROCKER_TLV_CMD_PORT_STATS_TX_PKTS, /* u64 */
175 ROCKER_TLV_CMD_PORT_STATS_TX_BYTES, /* u64 */
176 ROCKER_TLV_CMD_PORT_STATS_TX_DROPPED, /* u64 */
177 ROCKER_TLV_CMD_PORT_STATS_TX_ERRORS, /* u64 */
178
179 __ROCKER_TLV_CMD_PORT_STATS_MAX,
180 ROCKER_TLV_CMD_PORT_STATS_MAX = __ROCKER_TLV_CMD_PORT_STATS_MAX - 1,
181 };
182
183 enum rocker_port_mode {
184 ROCKER_PORT_MODE_OF_DPA,
185 };
186
187 enum {
188 ROCKER_TLV_EVENT_UNSPEC,
189 ROCKER_TLV_EVENT_TYPE, /* u16 */
190 ROCKER_TLV_EVENT_INFO, /* nest */
191
192 __ROCKER_TLV_EVENT_MAX,
193 ROCKER_TLV_EVENT_MAX = __ROCKER_TLV_EVENT_MAX - 1,
194 };
195
196 enum {
197 ROCKER_TLV_EVENT_TYPE_UNSPEC,
198 ROCKER_TLV_EVENT_TYPE_LINK_CHANGED,
199 ROCKER_TLV_EVENT_TYPE_MAC_VLAN_SEEN,
200
201 __ROCKER_TLV_EVENT_TYPE_MAX,
202 ROCKER_TLV_EVENT_TYPE_MAX = __ROCKER_TLV_EVENT_TYPE_MAX - 1,
203 };
204
205 enum {
206 ROCKER_TLV_EVENT_LINK_CHANGED_UNSPEC,
207 ROCKER_TLV_EVENT_LINK_CHANGED_PPORT, /* u32 */
208 ROCKER_TLV_EVENT_LINK_CHANGED_LINKUP, /* u8 */
209
210 __ROCKER_TLV_EVENT_LINK_CHANGED_MAX,
211 ROCKER_TLV_EVENT_LINK_CHANGED_MAX =
212 __ROCKER_TLV_EVENT_LINK_CHANGED_MAX - 1,
213 };
214
215 enum {
216 ROCKER_TLV_EVENT_MAC_VLAN_UNSPEC,
217 ROCKER_TLV_EVENT_MAC_VLAN_PPORT, /* u32 */
218 ROCKER_TLV_EVENT_MAC_VLAN_MAC, /* binary */
219 ROCKER_TLV_EVENT_MAC_VLAN_VLAN_ID, /* __be16 */
220
221 __ROCKER_TLV_EVENT_MAC_VLAN_MAX,
222 ROCKER_TLV_EVENT_MAC_VLAN_MAX = __ROCKER_TLV_EVENT_MAC_VLAN_MAX - 1,
223 };
224
225 enum {
226 ROCKER_TLV_RX_UNSPEC,
227 ROCKER_TLV_RX_FLAGS, /* u16, see ROCKER_RX_FLAGS_ */
228 ROCKER_TLV_RX_CSUM, /* u16 */
229 ROCKER_TLV_RX_FRAG_ADDR, /* u64 */
230 ROCKER_TLV_RX_FRAG_MAX_LEN, /* u16 */
231 ROCKER_TLV_RX_FRAG_LEN, /* u16 */
232
233 __ROCKER_TLV_RX_MAX,
234 ROCKER_TLV_RX_MAX = __ROCKER_TLV_RX_MAX - 1,
235 };
236
237 #define ROCKER_RX_FLAGS_IPV4 BIT(0)
238 #define ROCKER_RX_FLAGS_IPV6 BIT(1)
239 #define ROCKER_RX_FLAGS_CSUM_CALC BIT(2)
240 #define ROCKER_RX_FLAGS_IPV4_CSUM_GOOD BIT(3)
241 #define ROCKER_RX_FLAGS_IP_FRAG BIT(4)
242 #define ROCKER_RX_FLAGS_TCP BIT(5)
243 #define ROCKER_RX_FLAGS_UDP BIT(6)
244 #define ROCKER_RX_FLAGS_TCP_UDP_CSUM_GOOD BIT(7)
245 #define ROCKER_RX_FLAGS_FWD_OFFLOAD BIT(8)
246
247 enum {
248 ROCKER_TLV_TX_UNSPEC,
249 ROCKER_TLV_TX_OFFLOAD, /* u8, see ROCKER_TX_OFFLOAD_ */
250 ROCKER_TLV_TX_L3_CSUM_OFF, /* u16 */
251 ROCKER_TLV_TX_TSO_MSS, /* u16 */
252 ROCKER_TLV_TX_TSO_HDR_LEN, /* u16 */
253 ROCKER_TLV_TX_FRAGS, /* array */
254
255 __ROCKER_TLV_TX_MAX,
256 ROCKER_TLV_TX_MAX = __ROCKER_TLV_TX_MAX - 1,
257 };
258
259 #define ROCKER_TX_OFFLOAD_NONE 0
260 #define ROCKER_TX_OFFLOAD_IP_CSUM 1
261 #define ROCKER_TX_OFFLOAD_TCP_UDP_CSUM 2
262 #define ROCKER_TX_OFFLOAD_L3_CSUM 3
263 #define ROCKER_TX_OFFLOAD_TSO 4
264
265 #define ROCKER_TX_FRAGS_MAX 16
266
267 enum {
268 ROCKER_TLV_TX_FRAG_UNSPEC,
269 ROCKER_TLV_TX_FRAG, /* nest */
270
271 __ROCKER_TLV_TX_FRAG_MAX,
272 ROCKER_TLV_TX_FRAG_MAX = __ROCKER_TLV_TX_FRAG_MAX - 1,
273 };
274
275 enum {
276 ROCKER_TLV_TX_FRAG_ATTR_UNSPEC,
277 ROCKER_TLV_TX_FRAG_ATTR_ADDR, /* u64 */
278 ROCKER_TLV_TX_FRAG_ATTR_LEN, /* u16 */
279
280 __ROCKER_TLV_TX_FRAG_ATTR_MAX,
281 ROCKER_TLV_TX_FRAG_ATTR_MAX = __ROCKER_TLV_TX_FRAG_ATTR_MAX - 1,
282 };
283
284 /* cmd info nested for OF-DPA msgs */
285 enum {
286 ROCKER_TLV_OF_DPA_UNSPEC,
287 ROCKER_TLV_OF_DPA_TABLE_ID, /* u16 */
288 ROCKER_TLV_OF_DPA_PRIORITY, /* u32 */
289 ROCKER_TLV_OF_DPA_HARDTIME, /* u32 */
290 ROCKER_TLV_OF_DPA_IDLETIME, /* u32 */
291 ROCKER_TLV_OF_DPA_COOKIE, /* u64 */
292 ROCKER_TLV_OF_DPA_IN_PPORT, /* u32 */
293 ROCKER_TLV_OF_DPA_IN_PPORT_MASK, /* u32 */
294 ROCKER_TLV_OF_DPA_OUT_PPORT, /* u32 */
295 ROCKER_TLV_OF_DPA_GOTO_TABLE_ID, /* u16 */
296 ROCKER_TLV_OF_DPA_GROUP_ID, /* u32 */
297 ROCKER_TLV_OF_DPA_GROUP_ID_LOWER, /* u32 */
298 ROCKER_TLV_OF_DPA_GROUP_COUNT, /* u16 */
299 ROCKER_TLV_OF_DPA_GROUP_IDS, /* u32 array */
300 ROCKER_TLV_OF_DPA_VLAN_ID, /* __be16 */
301 ROCKER_TLV_OF_DPA_VLAN_ID_MASK, /* __be16 */
302 ROCKER_TLV_OF_DPA_VLAN_PCP, /* __be16 */
303 ROCKER_TLV_OF_DPA_VLAN_PCP_MASK, /* __be16 */
304 ROCKER_TLV_OF_DPA_VLAN_PCP_ACTION, /* u8 */
305 ROCKER_TLV_OF_DPA_NEW_VLAN_ID, /* __be16 */
306 ROCKER_TLV_OF_DPA_NEW_VLAN_PCP, /* u8 */
307 ROCKER_TLV_OF_DPA_TUNNEL_ID, /* u32 */
308 ROCKER_TLV_OF_DPA_TUNNEL_LPORT, /* u32 */
309 ROCKER_TLV_OF_DPA_ETHERTYPE, /* __be16 */
310 ROCKER_TLV_OF_DPA_DST_MAC, /* binary */
311 ROCKER_TLV_OF_DPA_DST_MAC_MASK, /* binary */
312 ROCKER_TLV_OF_DPA_SRC_MAC, /* binary */
313 ROCKER_TLV_OF_DPA_SRC_MAC_MASK, /* binary */
314 ROCKER_TLV_OF_DPA_IP_PROTO, /* u8 */
315 ROCKER_TLV_OF_DPA_IP_PROTO_MASK, /* u8 */
316 ROCKER_TLV_OF_DPA_IP_DSCP, /* u8 */
317 ROCKER_TLV_OF_DPA_IP_DSCP_MASK, /* u8 */
318 ROCKER_TLV_OF_DPA_IP_DSCP_ACTION, /* u8 */
319 ROCKER_TLV_OF_DPA_NEW_IP_DSCP, /* u8 */
320 ROCKER_TLV_OF_DPA_IP_ECN, /* u8 */
321 ROCKER_TLV_OF_DPA_IP_ECN_MASK, /* u8 */
322 ROCKER_TLV_OF_DPA_DST_IP, /* __be32 */
323 ROCKER_TLV_OF_DPA_DST_IP_MASK, /* __be32 */
324 ROCKER_TLV_OF_DPA_SRC_IP, /* __be32 */
325 ROCKER_TLV_OF_DPA_SRC_IP_MASK, /* __be32 */
326 ROCKER_TLV_OF_DPA_DST_IPV6, /* binary */
327 ROCKER_TLV_OF_DPA_DST_IPV6_MASK, /* binary */
328 ROCKER_TLV_OF_DPA_SRC_IPV6, /* binary */
329 ROCKER_TLV_OF_DPA_SRC_IPV6_MASK, /* binary */
330 ROCKER_TLV_OF_DPA_SRC_ARP_IP, /* __be32 */
331 ROCKER_TLV_OF_DPA_SRC_ARP_IP_MASK, /* __be32 */
332 ROCKER_TLV_OF_DPA_L4_DST_PORT, /* __be16 */
333 ROCKER_TLV_OF_DPA_L4_DST_PORT_MASK, /* __be16 */
334 ROCKER_TLV_OF_DPA_L4_SRC_PORT, /* __be16 */
335 ROCKER_TLV_OF_DPA_L4_SRC_PORT_MASK, /* __be16 */
336 ROCKER_TLV_OF_DPA_ICMP_TYPE, /* u8 */
337 ROCKER_TLV_OF_DPA_ICMP_TYPE_MASK, /* u8 */
338 ROCKER_TLV_OF_DPA_ICMP_CODE, /* u8 */
339 ROCKER_TLV_OF_DPA_ICMP_CODE_MASK, /* u8 */
340 ROCKER_TLV_OF_DPA_IPV6_LABEL, /* __be32 */
341 ROCKER_TLV_OF_DPA_IPV6_LABEL_MASK, /* __be32 */
342 ROCKER_TLV_OF_DPA_QUEUE_ID_ACTION, /* u8 */
343 ROCKER_TLV_OF_DPA_NEW_QUEUE_ID, /* u8 */
344 ROCKER_TLV_OF_DPA_CLEAR_ACTIONS, /* u32 */
345 ROCKER_TLV_OF_DPA_POP_VLAN, /* u8 */
346 ROCKER_TLV_OF_DPA_TTL_CHECK, /* u8 */
347 ROCKER_TLV_OF_DPA_COPY_CPU_ACTION, /* u8 */
348
349 __ROCKER_TLV_OF_DPA_MAX,
350 ROCKER_TLV_OF_DPA_MAX = __ROCKER_TLV_OF_DPA_MAX - 1,
351 };
352
353 /* OF-DPA table IDs */
354
355 enum rocker_of_dpa_table_id {
356 ROCKER_OF_DPA_TABLE_ID_INGRESS_PORT = 0,
357 ROCKER_OF_DPA_TABLE_ID_VLAN = 10,
358 ROCKER_OF_DPA_TABLE_ID_TERMINATION_MAC = 20,
359 ROCKER_OF_DPA_TABLE_ID_UNICAST_ROUTING = 30,
360 ROCKER_OF_DPA_TABLE_ID_MULTICAST_ROUTING = 40,
361 ROCKER_OF_DPA_TABLE_ID_BRIDGING = 50,
362 ROCKER_OF_DPA_TABLE_ID_ACL_POLICY = 60,
363 };
364
365 /* OF-DPA flow stats */
366 enum {
367 ROCKER_TLV_OF_DPA_FLOW_STAT_UNSPEC,
368 ROCKER_TLV_OF_DPA_FLOW_STAT_DURATION, /* u32 */
369 ROCKER_TLV_OF_DPA_FLOW_STAT_RX_PKTS, /* u64 */
370 ROCKER_TLV_OF_DPA_FLOW_STAT_TX_PKTS, /* u64 */
371
372 __ROCKER_TLV_OF_DPA_FLOW_STAT_MAX,
373 ROCKER_TLV_OF_DPA_FLOW_STAT_MAX = __ROCKER_TLV_OF_DPA_FLOW_STAT_MAX - 1,
374 };
375
376 /* OF-DPA group types */
377 enum rocker_of_dpa_group_type {
378 ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE = 0,
379 ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE,
380 ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST,
381 ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST,
382 ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD,
383 ROCKER_OF_DPA_GROUP_TYPE_L3_INTERFACE,
384 ROCKER_OF_DPA_GROUP_TYPE_L3_MCAST,
385 ROCKER_OF_DPA_GROUP_TYPE_L3_ECMP,
386 ROCKER_OF_DPA_GROUP_TYPE_L2_OVERLAY,
387 };
388
389 /* OF-DPA group L2 overlay types */
390 enum rocker_of_dpa_overlay_type {
391 ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_UCAST = 0,
392 ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_MCAST,
393 ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_UCAST,
394 ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_MCAST,
395 };
396
397 /* OF-DPA group ID encoding */
398 #define ROCKER_GROUP_TYPE_SHIFT 28
399 #define ROCKER_GROUP_TYPE_MASK 0xf0000000
400 #define ROCKER_GROUP_VLAN_SHIFT 16
401 #define ROCKER_GROUP_VLAN_MASK 0x0fff0000
402 #define ROCKER_GROUP_PORT_SHIFT 0
403 #define ROCKER_GROUP_PORT_MASK 0x0000ffff
404 #define ROCKER_GROUP_TUNNEL_ID_SHIFT 12
405 #define ROCKER_GROUP_TUNNEL_ID_MASK 0x0ffff000
406 #define ROCKER_GROUP_SUBTYPE_SHIFT 10
407 #define ROCKER_GROUP_SUBTYPE_MASK 0x00000c00
408 #define ROCKER_GROUP_INDEX_SHIFT 0
409 #define ROCKER_GROUP_INDEX_MASK 0x0000ffff
410 #define ROCKER_GROUP_INDEX_LONG_SHIFT 0
411 #define ROCKER_GROUP_INDEX_LONG_MASK 0x0fffffff
412
413 #define ROCKER_GROUP_TYPE_GET(group_id) \
414 (((group_id) & ROCKER_GROUP_TYPE_MASK) >> ROCKER_GROUP_TYPE_SHIFT)
415 #define ROCKER_GROUP_TYPE_SET(type) \
416 (((type) << ROCKER_GROUP_TYPE_SHIFT) & ROCKER_GROUP_TYPE_MASK)
417 #define ROCKER_GROUP_VLAN_GET(group_id) \
418 (((group_id) & ROCKER_GROUP_VLAN_ID_MASK) >> ROCKER_GROUP_VLAN_ID_SHIFT)
419 #define ROCKER_GROUP_VLAN_SET(vlan_id) \
420 (((vlan_id) << ROCKER_GROUP_VLAN_SHIFT) & ROCKER_GROUP_VLAN_MASK)
421 #define ROCKER_GROUP_PORT_GET(group_id) \
422 (((group_id) & ROCKER_GROUP_PORT_MASK) >> ROCKER_GROUP_PORT_SHIFT)
423 #define ROCKER_GROUP_PORT_SET(port) \
424 (((port) << ROCKER_GROUP_PORT_SHIFT) & ROCKER_GROUP_PORT_MASK)
425 #define ROCKER_GROUP_INDEX_GET(group_id) \
426 (((group_id) & ROCKER_GROUP_INDEX_MASK) >> ROCKER_GROUP_INDEX_SHIFT)
427 #define ROCKER_GROUP_INDEX_SET(index) \
428 (((index) << ROCKER_GROUP_INDEX_SHIFT) & ROCKER_GROUP_INDEX_MASK)
429 #define ROCKER_GROUP_INDEX_LONG_GET(group_id) \
430 (((group_id) & ROCKER_GROUP_INDEX_LONG_MASK) >> \
431 ROCKER_GROUP_INDEX_LONG_SHIFT)
432 #define ROCKER_GROUP_INDEX_LONG_SET(index) \
433 (((index) << ROCKER_GROUP_INDEX_LONG_SHIFT) & \
434 ROCKER_GROUP_INDEX_LONG_MASK)
435
436 #define ROCKER_GROUP_NONE 0
437 #define ROCKER_GROUP_L2_INTERFACE(vlan_id, port) \
438 (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE) |\
439 ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_PORT_SET(port))
440 #define ROCKER_GROUP_L2_REWRITE(index) \
441 (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE) |\
442 ROCKER_GROUP_INDEX_LONG_SET(index))
443 #define ROCKER_GROUP_L2_MCAST(vlan_id, index) \
444 (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST) |\
445 ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_INDEX_SET(index))
446 #define ROCKER_GROUP_L2_FLOOD(vlan_id, index) \
447 (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD) |\
448 ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_INDEX_SET(index))
449 #define ROCKER_GROUP_L3_UNICAST(index) \
450 (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST) |\
451 ROCKER_GROUP_INDEX_LONG_SET(index))
452
453 /* Rocker general purpose registers */
454 #define ROCKER_CONTROL 0x0300
455 #define ROCKER_PORT_PHYS_COUNT 0x0304
456 #define ROCKER_PORT_PHYS_LINK_STATUS 0x0310 /* 8-byte */
457 #define ROCKER_PORT_PHYS_ENABLE 0x0318 /* 8-byte */
458 #define ROCKER_SWITCH_ID 0x0320 /* 8-byte */
459
460 /* Rocker control bits */
461 #define ROCKER_CONTROL_RESET BIT(0)
462
463 #endif
Linux with added FPC-III support