drivers/net/ethernet/sfc/nic.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /****************************************************************************
   3  * Driver for Solarflare network controllers and boards
   4  * Copyright 2005-2006 Fen Systems Ltd.
   5  * Copyright 2006-2013 Solarflare Communications Inc.
   6  */
   7
   8 #ifndef EFX_NIC_H
   9 #define EFX_NIC_H
  10
  11 #include <linux/net_tstamp.h>
  12 #include "net_driver.h"
  13 #include "efx.h"
  14 #include "efx_common.h"
  15 #include "mcdi.h"
  16
  17 enum {
  18         /* Revisions 0-2 were Falcon A0, A1 and B0 respectively.
  19          * They are not supported by this driver but these revision numbers
  20          * form part of the ethtool API for register dumping.
  21          */
  22         EFX_REV_SIENA_A0 = 3,
  23         EFX_REV_HUNT_A0 = 4,
  24 };
  25
  26 static inline int efx_nic_rev(struct efx_nic *efx)
  27 {
  28         return efx->type->revision;
  29 }
  30
  31 u32 efx_farch_fpga_ver(struct efx_nic *efx);
  32
  33 /* Read the current event from the event queue */
  34 static inline efx_qword_t *efx_event(struct efx_channel *channel,
  35                                      unsigned int index)
  36 {
  37         return ((efx_qword_t *) (channel->eventq.buf.addr)) +
  38                 (index & channel->eventq_mask);
  39 }
  40
  41 /* See if an event is present
  42  *
  43  * We check both the high and low dword of the event for all ones.  We
  44  * wrote all ones when we cleared the event, and no valid event can
  45  * have all ones in either its high or low dwords.  This approach is
  46  * robust against reordering.
  47  *
  48  * Note that using a single 64-bit comparison is incorrect; even
  49  * though the CPU read will be atomic, the DMA write may not be.
  50  */
  51 static inline int efx_event_present(efx_qword_t *event)
  52 {
  53         return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
  54                   EFX_DWORD_IS_ALL_ONES(event->dword[1]));
  55 }
  56
  57 /* Returns a pointer to the specified transmit descriptor in the TX
  58  * descriptor queue belonging to the specified channel.
  59  */
  60 static inline efx_qword_t *
  61 efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
  62 {
  63         return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index;
  64 }
  65
  66 /* Get partner of a TX queue, seen as part of the same net core queue */
  67 static struct efx_tx_queue *efx_tx_queue_partner(struct efx_tx_queue *tx_queue)
  68 {
  69         if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
  70                 return tx_queue - EFX_TXQ_TYPE_OFFLOAD;
  71         else
  72                 return tx_queue + EFX_TXQ_TYPE_OFFLOAD;
  73 }
  74
  75 /* Report whether this TX queue would be empty for the given write_count.
  76  * May return false negative.
  77  */
  78 static inline bool __efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue,
  79                                          unsigned int write_count)
  80 {
  81         unsigned int empty_read_count = READ_ONCE(tx_queue->empty_read_count);
  82
  83         if (empty_read_count == 0)
  84                 return false;
  85
  86         return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0;
  87 }
  88
  89 /* Report whether the NIC considers this TX queue empty, using
  90  * packet_write_count (the write count recorded for the last completable
  91  * doorbell push).  May return false negative.  EF10 only, which is OK
  92  * because only EF10 supports PIO.
  93  */
  94 static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue)
  95 {
  96         EFX_WARN_ON_ONCE_PARANOID(!tx_queue->efx->type->option_descriptors);
  97         return __efx_nic_tx_is_empty(tx_queue, tx_queue->packet_write_count);
  98 }
  99
 100 /* Decide whether we can use TX PIO, ie. write packet data directly into
 101  * a buffer on the device.  This can reduce latency at the expense of
 102  * throughput, so we only do this if both hardware and software TX rings
 103  * are empty.  This also ensures that only one packet at a time can be
 104  * using the PIO buffer.
 105  */
 106 static inline bool efx_nic_may_tx_pio(struct efx_tx_queue *tx_queue)
 107 {
 108         struct efx_tx_queue *partner = efx_tx_queue_partner(tx_queue);
 109
 110         return tx_queue->piobuf && efx_nic_tx_is_empty(tx_queue) &&
 111                efx_nic_tx_is_empty(partner);
 112 }
 113
 114 /* Decide whether to push a TX descriptor to the NIC vs merely writing
 115  * the doorbell.  This can reduce latency when we are adding a single
 116  * descriptor to an empty queue, but is otherwise pointless.  Further,
 117  * Falcon and Siena have hardware bugs (SF bug 33851) that may be
 118  * triggered if we don't check this.
 119  * We use the write_count used for the last doorbell push, to get the
 120  * NIC's view of the tx queue.
 121  */
 122 static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue,
 123                                             unsigned int write_count)
 124 {
 125         bool was_empty = __efx_nic_tx_is_empty(tx_queue, write_count);
 126
 127         tx_queue->empty_read_count = 0;
 128         return was_empty && tx_queue->write_count - write_count == 1;
 129 }
 130
 131 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
 132 static inline efx_qword_t *
 133 efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
 134 {
 135         return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index;
 136 }
 137
 138 enum {
 139         PHY_TYPE_NONE = 0,
 140         PHY_TYPE_TXC43128 = 1,
 141         PHY_TYPE_88E1111 = 2,
 142         PHY_TYPE_SFX7101 = 3,
 143         PHY_TYPE_QT2022C2 = 4,
 144         PHY_TYPE_PM8358 = 6,
 145         PHY_TYPE_SFT9001A = 8,
 146         PHY_TYPE_QT2025C = 9,
 147         PHY_TYPE_SFT9001B = 10,
 148 };
 149
 150 /* Alignment of PCIe DMA boundaries (4KB) */
 151 #define EFX_PAGE_SIZE   4096
 152 /* Size and alignment of buffer table entries (same) */
 153 #define EFX_BUF_SIZE    EFX_PAGE_SIZE
 154
 155 /* NIC-generic software stats */
 156 enum {
 157         GENERIC_STAT_rx_noskb_drops,
 158         GENERIC_STAT_rx_nodesc_trunc,
 159         GENERIC_STAT_COUNT
 160 };
 161
 162 enum {
 163         SIENA_STAT_tx_bytes = GENERIC_STAT_COUNT,
 164         SIENA_STAT_tx_good_bytes,
 165         SIENA_STAT_tx_bad_bytes,
 166         SIENA_STAT_tx_packets,
 167         SIENA_STAT_tx_bad,
 168         SIENA_STAT_tx_pause,
 169         SIENA_STAT_tx_control,
 170         SIENA_STAT_tx_unicast,
 171         SIENA_STAT_tx_multicast,
 172         SIENA_STAT_tx_broadcast,
 173         SIENA_STAT_tx_lt64,
 174         SIENA_STAT_tx_64,
 175         SIENA_STAT_tx_65_to_127,
 176         SIENA_STAT_tx_128_to_255,
 177         SIENA_STAT_tx_256_to_511,
 178         SIENA_STAT_tx_512_to_1023,
 179         SIENA_STAT_tx_1024_to_15xx,
 180         SIENA_STAT_tx_15xx_to_jumbo,
 181         SIENA_STAT_tx_gtjumbo,
 182         SIENA_STAT_tx_collision,
 183         SIENA_STAT_tx_single_collision,
 184         SIENA_STAT_tx_multiple_collision,
 185         SIENA_STAT_tx_excessive_collision,
 186         SIENA_STAT_tx_deferred,
 187         SIENA_STAT_tx_late_collision,
 188         SIENA_STAT_tx_excessive_deferred,
 189         SIENA_STAT_tx_non_tcpudp,
 190         SIENA_STAT_tx_mac_src_error,
 191         SIENA_STAT_tx_ip_src_error,
 192         SIENA_STAT_rx_bytes,
 193         SIENA_STAT_rx_good_bytes,
 194         SIENA_STAT_rx_bad_bytes,
 195         SIENA_STAT_rx_packets,
 196         SIENA_STAT_rx_good,
 197         SIENA_STAT_rx_bad,
 198         SIENA_STAT_rx_pause,
 199         SIENA_STAT_rx_control,
 200         SIENA_STAT_rx_unicast,
 201         SIENA_STAT_rx_multicast,
 202         SIENA_STAT_rx_broadcast,
 203         SIENA_STAT_rx_lt64,
 204         SIENA_STAT_rx_64,
 205         SIENA_STAT_rx_65_to_127,
 206         SIENA_STAT_rx_128_to_255,
 207         SIENA_STAT_rx_256_to_511,
 208         SIENA_STAT_rx_512_to_1023,
 209         SIENA_STAT_rx_1024_to_15xx,
 210         SIENA_STAT_rx_15xx_to_jumbo,
 211         SIENA_STAT_rx_gtjumbo,
 212         SIENA_STAT_rx_bad_gtjumbo,
 213         SIENA_STAT_rx_overflow,
 214         SIENA_STAT_rx_false_carrier,
 215         SIENA_STAT_rx_symbol_error,
 216         SIENA_STAT_rx_align_error,
 217         SIENA_STAT_rx_length_error,
 218         SIENA_STAT_rx_internal_error,
 219         SIENA_STAT_rx_nodesc_drop_cnt,
 220         SIENA_STAT_COUNT
 221 };
 222
 223 /**
 224  * struct siena_nic_data - Siena NIC state
 225  * @efx: Pointer back to main interface structure
 226  * @wol_filter_id: Wake-on-LAN packet filter id
 227  * @stats: Hardware statistics
 228  * @vf: Array of &struct siena_vf objects
 229  * @vf_buftbl_base: The zeroth buffer table index used to back VF queues.
 230  * @vfdi_status: Common VFDI status page to be dmad to VF address space.
 231  * @local_addr_list: List of local addresses. Protected by %local_lock.
 232  * @local_page_list: List of DMA addressable pages used to broadcast
 233  *      %local_addr_list. Protected by %local_lock.
 234  * @local_lock: Mutex protecting %local_addr_list and %local_page_list.
 235  * @peer_work: Work item to broadcast peer addresses to VMs.
 236  */
 237 struct siena_nic_data {
 238         struct efx_nic *efx;
 239         int wol_filter_id;
 240         u64 stats[SIENA_STAT_COUNT];
 241 #ifdef CONFIG_SFC_SRIOV
 242         struct siena_vf *vf;
 243         struct efx_channel *vfdi_channel;
 244         unsigned vf_buftbl_base;
 245         struct efx_buffer vfdi_status;
 246         struct list_head local_addr_list;
 247         struct list_head local_page_list;
 248         struct mutex local_lock;
 249         struct work_struct peer_work;
 250 #endif
 251 };
 252
 253 enum {
 254         EF10_STAT_port_tx_bytes = GENERIC_STAT_COUNT,
 255         EF10_STAT_port_tx_packets,
 256         EF10_STAT_port_tx_pause,
 257         EF10_STAT_port_tx_control,
 258         EF10_STAT_port_tx_unicast,
 259         EF10_STAT_port_tx_multicast,
 260         EF10_STAT_port_tx_broadcast,
 261         EF10_STAT_port_tx_lt64,
 262         EF10_STAT_port_tx_64,
 263         EF10_STAT_port_tx_65_to_127,
 264         EF10_STAT_port_tx_128_to_255,
 265         EF10_STAT_port_tx_256_to_511,
 266         EF10_STAT_port_tx_512_to_1023,
 267         EF10_STAT_port_tx_1024_to_15xx,
 268         EF10_STAT_port_tx_15xx_to_jumbo,
 269         EF10_STAT_port_rx_bytes,
 270         EF10_STAT_port_rx_bytes_minus_good_bytes,
 271         EF10_STAT_port_rx_good_bytes,
 272         EF10_STAT_port_rx_bad_bytes,
 273         EF10_STAT_port_rx_packets,
 274         EF10_STAT_port_rx_good,
 275         EF10_STAT_port_rx_bad,
 276         EF10_STAT_port_rx_pause,
 277         EF10_STAT_port_rx_control,
 278         EF10_STAT_port_rx_unicast,
 279         EF10_STAT_port_rx_multicast,
 280         EF10_STAT_port_rx_broadcast,
 281         EF10_STAT_port_rx_lt64,
 282         EF10_STAT_port_rx_64,
 283         EF10_STAT_port_rx_65_to_127,
 284         EF10_STAT_port_rx_128_to_255,
 285         EF10_STAT_port_rx_256_to_511,
 286         EF10_STAT_port_rx_512_to_1023,
 287         EF10_STAT_port_rx_1024_to_15xx,
 288         EF10_STAT_port_rx_15xx_to_jumbo,
 289         EF10_STAT_port_rx_gtjumbo,
 290         EF10_STAT_port_rx_bad_gtjumbo,
 291         EF10_STAT_port_rx_overflow,
 292         EF10_STAT_port_rx_align_error,
 293         EF10_STAT_port_rx_length_error,
 294         EF10_STAT_port_rx_nodesc_drops,
 295         EF10_STAT_port_rx_pm_trunc_bb_overflow,
 296         EF10_STAT_port_rx_pm_discard_bb_overflow,
 297         EF10_STAT_port_rx_pm_trunc_vfifo_full,
 298         EF10_STAT_port_rx_pm_discard_vfifo_full,
 299         EF10_STAT_port_rx_pm_trunc_qbb,
 300         EF10_STAT_port_rx_pm_discard_qbb,
 301         EF10_STAT_port_rx_pm_discard_mapping,
 302         EF10_STAT_port_rx_dp_q_disabled_packets,
 303         EF10_STAT_port_rx_dp_di_dropped_packets,
 304         EF10_STAT_port_rx_dp_streaming_packets,
 305         EF10_STAT_port_rx_dp_hlb_fetch,
 306         EF10_STAT_port_rx_dp_hlb_wait,
 307         EF10_STAT_rx_unicast,
 308         EF10_STAT_rx_unicast_bytes,
 309         EF10_STAT_rx_multicast,
 310         EF10_STAT_rx_multicast_bytes,
 311         EF10_STAT_rx_broadcast,
 312         EF10_STAT_rx_broadcast_bytes,
 313         EF10_STAT_rx_bad,
 314         EF10_STAT_rx_bad_bytes,
 315         EF10_STAT_rx_overflow,
 316         EF10_STAT_tx_unicast,
 317         EF10_STAT_tx_unicast_bytes,
 318         EF10_STAT_tx_multicast,
 319         EF10_STAT_tx_multicast_bytes,
 320         EF10_STAT_tx_broadcast,
 321         EF10_STAT_tx_broadcast_bytes,
 322         EF10_STAT_tx_bad,
 323         EF10_STAT_tx_bad_bytes,
 324         EF10_STAT_tx_overflow,
 325         EF10_STAT_V1_COUNT,
 326         EF10_STAT_fec_uncorrected_errors = EF10_STAT_V1_COUNT,
 327         EF10_STAT_fec_corrected_errors,
 328         EF10_STAT_fec_corrected_symbols_lane0,
 329         EF10_STAT_fec_corrected_symbols_lane1,
 330         EF10_STAT_fec_corrected_symbols_lane2,
 331         EF10_STAT_fec_corrected_symbols_lane3,
 332         EF10_STAT_ctpio_vi_busy_fallback,
 333         EF10_STAT_ctpio_long_write_success,
 334         EF10_STAT_ctpio_missing_dbell_fail,
 335         EF10_STAT_ctpio_overflow_fail,
 336         EF10_STAT_ctpio_underflow_fail,
 337         EF10_STAT_ctpio_timeout_fail,
 338         EF10_STAT_ctpio_noncontig_wr_fail,
 339         EF10_STAT_ctpio_frm_clobber_fail,
 340         EF10_STAT_ctpio_invalid_wr_fail,
 341         EF10_STAT_ctpio_vi_clobber_fallback,
 342         EF10_STAT_ctpio_unqualified_fallback,
 343         EF10_STAT_ctpio_runt_fallback,
 344         EF10_STAT_ctpio_success,
 345         EF10_STAT_ctpio_fallback,
 346         EF10_STAT_ctpio_poison,
 347         EF10_STAT_ctpio_erase,
 348         EF10_STAT_COUNT
 349 };
 350
 351 /* Maximum number of TX PIO buffers we may allocate to a function.
 352  * This matches the total number of buffers on each SFC9100-family
 353  * controller.
 354  */
 355 #define EF10_TX_PIOBUF_COUNT 16
 356
 357 /**
 358  * struct efx_ef10_nic_data - EF10 architecture NIC state
 359  * @mcdi_buf: DMA buffer for MCDI
 360  * @warm_boot_count: Last seen MC warm boot count
 361  * @vi_base: Absolute index of first VI in this function
 362  * @n_allocated_vis: Number of VIs allocated to this function
 363  * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot
 364  * @must_restore_rss_contexts: Flag: RSS contexts have yet to be restored after
 365  *      MC reboot
 366  * @must_restore_filters: Flag: filters have yet to be restored after MC reboot
 367  * @n_piobufs: Number of PIO buffers allocated to this function
 368  * @wc_membase: Base address of write-combining mapping of the memory BAR
 369  * @pio_write_base: Base address for writing PIO buffers
 370  * @pio_write_vi_base: Relative VI number for @pio_write_base
 371  * @piobuf_handle: Handle of each PIO buffer allocated
 372  * @piobuf_size: size of a single PIO buffer
 373  * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC
 374  *      reboot
 375  * @rx_rss_context_exclusive: Whether our RSS context is exclusive or shared
 376  * @stats: Hardware statistics
 377  * @workaround_35388: Flag: firmware supports workaround for bug 35388
 378  * @workaround_26807: Flag: firmware supports workaround for bug 26807
 379  * @workaround_61265: Flag: firmware supports workaround for bug 61265
 380  * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated
 381  *      after MC reboot
 382  * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of
 383  *      %MC_CMD_GET_CAPABILITIES response)
 384  * @datapath_caps2: Further Capabilities of datapath firmware (FLAGS2 field of
 385  * %MC_CMD_GET_CAPABILITIES response)
 386  * @rx_dpcpu_fw_id: Firmware ID of the RxDPCPU
 387  * @tx_dpcpu_fw_id: Firmware ID of the TxDPCPU
 388  * @vport_id: The function's vport ID, only relevant for PFs
 389  * @must_probe_vswitching: Flag: vswitching has yet to be setup after MC reboot
 390  * @pf_index: The number for this PF, or the parent PF if this is a VF
 391 #ifdef CONFIG_SFC_SRIOV
 392  * @vf: Pointer to VF data structure
 393 #endif
 394  * @vport_mac: The MAC address on the vport, only for PFs; VFs will be zero
 395  * @vlan_list: List of VLANs added over the interface. Serialised by vlan_lock.
 396  * @vlan_lock: Lock to serialize access to vlan_list.
 397  * @udp_tunnels: UDP tunnel port numbers and types.
 398  * @udp_tunnels_dirty: flag indicating a reboot occurred while pushing
 399  *      @udp_tunnels to hardware and thus the push must be re-done.
 400  * @udp_tunnels_lock: Serialises writes to @udp_tunnels and @udp_tunnels_dirty.
 401  */
 402 struct efx_ef10_nic_data {
 403         struct efx_buffer mcdi_buf;
 404         u16 warm_boot_count;
 405         unsigned int vi_base;
 406         unsigned int n_allocated_vis;
 407         bool must_realloc_vis;
 408         bool must_restore_rss_contexts;
 409         bool must_restore_filters;
 410         unsigned int n_piobufs;
 411         void __iomem *wc_membase, *pio_write_base;
 412         unsigned int pio_write_vi_base;
 413         unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT];
 414         u16 piobuf_size;
 415         bool must_restore_piobufs;
 416         bool rx_rss_context_exclusive;
 417         u64 stats[EF10_STAT_COUNT];
 418         bool workaround_35388;
 419         bool workaround_26807;
 420         bool workaround_61265;
 421         bool must_check_datapath_caps;
 422         u32 datapath_caps;
 423         u32 datapath_caps2;
 424         unsigned int rx_dpcpu_fw_id;
 425         unsigned int tx_dpcpu_fw_id;
 426         unsigned int vport_id;
 427         bool must_probe_vswitching;
 428         unsigned int pf_index;
 429         u8 port_id[ETH_ALEN];
 430 #ifdef CONFIG_SFC_SRIOV
 431         unsigned int vf_index;
 432         struct ef10_vf *vf;
 433 #endif
 434         u8 vport_mac[ETH_ALEN];
 435         struct list_head vlan_list;
 436         struct mutex vlan_lock;
 437         struct efx_udp_tunnel udp_tunnels[16];
 438         bool udp_tunnels_dirty;
 439         struct mutex udp_tunnels_lock;
 440         u64 licensed_features;
 441 };
 442
 443 int efx_init_sriov(void);
 444 void efx_fini_sriov(void);
 445
 446 struct ethtool_ts_info;
 447 int efx_ptp_probe(struct efx_nic *efx, struct efx_channel *channel);
 448 void efx_ptp_defer_probe_with_channel(struct efx_nic *efx);
 449 struct efx_channel *efx_ptp_channel(struct efx_nic *efx);
 450 void efx_ptp_remove(struct efx_nic *efx);
 451 int efx_ptp_set_ts_config(struct efx_nic *efx, struct ifreq *ifr);
 452 int efx_ptp_get_ts_config(struct efx_nic *efx, struct ifreq *ifr);
 453 void efx_ptp_get_ts_info(struct efx_nic *efx, struct ethtool_ts_info *ts_info);
 454 bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
 455 int efx_ptp_get_mode(struct efx_nic *efx);
 456 int efx_ptp_change_mode(struct efx_nic *efx, bool enable_wanted,
 457                         unsigned int new_mode);
 458 int efx_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
 459 void efx_ptp_event(struct efx_nic *efx, efx_qword_t *ev);
 460 size_t efx_ptp_describe_stats(struct efx_nic *efx, u8 *strings);
 461 size_t efx_ptp_update_stats(struct efx_nic *efx, u64 *stats);
 462 void efx_time_sync_event(struct efx_channel *channel, efx_qword_t *ev);
 463 void __efx_rx_skb_attach_timestamp(struct efx_channel *channel,
 464                                    struct sk_buff *skb);
 465 static inline void efx_rx_skb_attach_timestamp(struct efx_channel *channel,
 466                                                struct sk_buff *skb)
 467 {
 468         if (channel->sync_events_state == SYNC_EVENTS_VALID)
 469                 __efx_rx_skb_attach_timestamp(channel, skb);
 470 }
 471 void efx_ptp_start_datapath(struct efx_nic *efx);
 472 void efx_ptp_stop_datapath(struct efx_nic *efx);
 473 bool efx_ptp_use_mac_tx_timestamps(struct efx_nic *efx);
 474 ktime_t efx_ptp_nic_to_kernel_time(struct efx_tx_queue *tx_queue);
 475
 476 extern const struct efx_nic_type falcon_a1_nic_type;
 477 extern const struct efx_nic_type falcon_b0_nic_type;
 478 extern const struct efx_nic_type siena_a0_nic_type;
 479 extern const struct efx_nic_type efx_hunt_a0_nic_type;
 480 extern const struct efx_nic_type efx_hunt_a0_vf_nic_type;
 481
 482 /**************************************************************************
 483  *
 484  * Externs
 485  *
 486  **************************************************************************
 487  */
 488
 489 int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
 490
 491 /* TX data path */
 492 static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
 493 {
 494         return tx_queue->efx->type->tx_probe(tx_queue);
 495 }
 496 static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
 497 {
 498         tx_queue->efx->type->tx_init(tx_queue);
 499 }
 500 static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
 501 {
 502         tx_queue->efx->type->tx_remove(tx_queue);
 503 }
 504 static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
 505 {
 506         tx_queue->efx->type->tx_write(tx_queue);
 507 }
 508
 509 int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
 510                         bool *data_mapped);
 511
 512 /* RX data path */
 513 static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
 514 {
 515         return rx_queue->efx->type->rx_probe(rx_queue);
 516 }
 517 static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
 518 {
 519         rx_queue->efx->type->rx_init(rx_queue);
 520 }
 521 static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
 522 {
 523         rx_queue->efx->type->rx_remove(rx_queue);
 524 }
 525 static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
 526 {
 527         rx_queue->efx->type->rx_write(rx_queue);
 528 }
 529 static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue)
 530 {
 531         rx_queue->efx->type->rx_defer_refill(rx_queue);
 532 }
 533
 534 /* Event data path */
 535 static inline int efx_nic_probe_eventq(struct efx_channel *channel)
 536 {
 537         return channel->efx->type->ev_probe(channel);
 538 }
 539 static inline int efx_nic_init_eventq(struct efx_channel *channel)
 540 {
 541         return channel->efx->type->ev_init(channel);
 542 }
 543 static inline void efx_nic_fini_eventq(struct efx_channel *channel)
 544 {
 545         channel->efx->type->ev_fini(channel);
 546 }
 547 static inline void efx_nic_remove_eventq(struct efx_channel *channel)
 548 {
 549         channel->efx->type->ev_remove(channel);
 550 }
 551 static inline int
 552 efx_nic_process_eventq(struct efx_channel *channel, int quota)
 553 {
 554         return channel->efx->type->ev_process(channel, quota);
 555 }
 556 static inline void efx_nic_eventq_read_ack(struct efx_channel *channel)
 557 {
 558         channel->efx->type->ev_read_ack(channel);
 559 }
 560
 561 void efx_nic_event_test_start(struct efx_channel *channel);
 562
 563 /* Falcon/Siena queue operations */
 564 int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);
 565 void efx_farch_tx_init(struct efx_tx_queue *tx_queue);
 566 void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);
 567 void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);
 568 void efx_farch_tx_write(struct efx_tx_queue *tx_queue);
 569 unsigned int efx_farch_tx_limit_len(struct efx_tx_queue *tx_queue,
 570                                     dma_addr_t dma_addr, unsigned int len);
 571 int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);
 572 void efx_farch_rx_init(struct efx_rx_queue *rx_queue);
 573 void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);
 574 void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);
 575 void efx_farch_rx_write(struct efx_rx_queue *rx_queue);
 576 void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);
 577 int efx_farch_ev_probe(struct efx_channel *channel);
 578 int efx_farch_ev_init(struct efx_channel *channel);
 579 void efx_farch_ev_fini(struct efx_channel *channel);
 580 void efx_farch_ev_remove(struct efx_channel *channel);
 581 int efx_farch_ev_process(struct efx_channel *channel, int quota);
 582 void efx_farch_ev_read_ack(struct efx_channel *channel);
 583 void efx_farch_ev_test_generate(struct efx_channel *channel);
 584
 585 /* Falcon/Siena filter operations */
 586 int efx_farch_filter_table_probe(struct efx_nic *efx);
 587 void efx_farch_filter_table_restore(struct efx_nic *efx);
 588 void efx_farch_filter_table_remove(struct efx_nic *efx);
 589 void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);
 590 s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec,
 591                             bool replace);
 592 int efx_farch_filter_remove_safe(struct efx_nic *efx,
 593                                  enum efx_filter_priority priority,
 594                                  u32 filter_id);
 595 int efx_farch_filter_get_safe(struct efx_nic *efx,
 596                               enum efx_filter_priority priority, u32 filter_id,
 597                               struct efx_filter_spec *);
 598 int efx_farch_filter_clear_rx(struct efx_nic *efx,
 599                               enum efx_filter_priority priority);
 600 u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
 601                                    enum efx_filter_priority priority);
 602 u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);
 603 s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
 604                                 enum efx_filter_priority priority, u32 *buf,
 605                                 u32 size);
 606 #ifdef CONFIG_RFS_ACCEL
 607 bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
 608                                      unsigned int index);
 609 #endif
 610 void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);
 611
 612 bool efx_nic_event_present(struct efx_channel *channel);
 613
 614 /* Some statistics are computed as A - B where A and B each increase
 615  * linearly with some hardware counter(s) and the counters are read
 616  * asynchronously.  If the counters contributing to B are always read
 617  * after those contributing to A, the computed value may be lower than
 618  * the true value by some variable amount, and may decrease between
 619  * subsequent computations.
 620  *
 621  * We should never allow statistics to decrease or to exceed the true
 622  * value.  Since the computed value will never be greater than the
 623  * true value, we can achieve this by only storing the computed value
 624  * when it increases.
 625  */
 626 static inline void efx_update_diff_stat(u64 *stat, u64 diff)
 627 {
 628         if ((s64)(diff - *stat) > 0)
 629                 *stat = diff;
 630 }
 631
 632 /* Interrupts */
 633 int efx_nic_init_interrupt(struct efx_nic *efx);
 634 int efx_nic_irq_test_start(struct efx_nic *efx);
 635 void efx_nic_fini_interrupt(struct efx_nic *efx);
 636
 637 /* Falcon/Siena interrupts */
 638 void efx_farch_irq_enable_master(struct efx_nic *efx);
 639 int efx_farch_irq_test_generate(struct efx_nic *efx);
 640 void efx_farch_irq_disable_master(struct efx_nic *efx);
 641 irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);
 642 irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);
 643 irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);
 644
 645 static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel)
 646 {
 647         return READ_ONCE(channel->event_test_cpu);
 648 }
 649 static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx)
 650 {
 651         return READ_ONCE(efx->last_irq_cpu);
 652 }
 653
 654 /* Global Resources */
 655 int efx_nic_flush_queues(struct efx_nic *efx);
 656 void siena_prepare_flush(struct efx_nic *efx);
 657 int efx_farch_fini_dmaq(struct efx_nic *efx);
 658 void efx_farch_finish_flr(struct efx_nic *efx);
 659 void siena_finish_flush(struct efx_nic *efx);
 660 void falcon_start_nic_stats(struct efx_nic *efx);
 661 void falcon_stop_nic_stats(struct efx_nic *efx);
 662 int falcon_reset_xaui(struct efx_nic *efx);
 663 void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
 664 void efx_farch_init_common(struct efx_nic *efx);
 665 void efx_ef10_handle_drain_event(struct efx_nic *efx);
 666 void efx_farch_rx_push_indir_table(struct efx_nic *efx);
 667 void efx_farch_rx_pull_indir_table(struct efx_nic *efx);
 668
 669 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
 670                          unsigned int len, gfp_t gfp_flags);
 671 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer);
 672
 673 /* Tests */
 674 struct efx_farch_register_test {
 675         unsigned address;
 676         efx_oword_t mask;
 677 };
 678
 679 int efx_farch_test_registers(struct efx_nic *efx,
 680                              const struct efx_farch_register_test *regs,
 681                              size_t n_regs);
 682
 683 size_t efx_nic_get_regs_len(struct efx_nic *efx);
 684 void efx_nic_get_regs(struct efx_nic *efx, void *buf);
 685
 686 size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
 687                               const unsigned long *mask, u8 *names);
 688 void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
 689                           const unsigned long *mask, u64 *stats,
 690                           const void *dma_buf, bool accumulate);
 691 void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat);
 692
 693 #define EFX_MAX_FLUSH_TIME 5000
 694
 695 void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
 696                               efx_qword_t *event);
 697
 698 #endif /* EFX_NIC_H */