gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / net / ethernet / smsc / smsc9420.c
blob7312e522c0226ed608fb4a554d0a3822a106a95c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /***************************************************************************
4 * Copyright (C) 2007,2008 SMSC
6 ***************************************************************************
7 */
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 #include <linux/interrupt.h>
12 #include <linux/kernel.h>
13 #include <linux/netdevice.h>
14 #include <linux/phy.h>
15 #include <linux/pci.h>
16 #include <linux/if_vlan.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/crc32.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <asm/unaligned.h>
22 #include "smsc9420.h"
24 #define DRV_NAME "smsc9420"
25 #define DRV_MDIONAME "smsc9420-mdio"
26 #define DRV_DESCRIPTION "SMSC LAN9420 driver"
27 #define DRV_VERSION "1.01"
29 MODULE_LICENSE("GPL");
30 MODULE_VERSION(DRV_VERSION);
32 struct smsc9420_dma_desc {
33 u32 status;
34 u32 length;
35 u32 buffer1;
36 u32 buffer2;
39 struct smsc9420_ring_info {
40 struct sk_buff *skb;
41 dma_addr_t mapping;
44 struct smsc9420_pdata {
45 void __iomem *ioaddr;
46 struct pci_dev *pdev;
47 struct net_device *dev;
49 struct smsc9420_dma_desc *rx_ring;
50 struct smsc9420_dma_desc *tx_ring;
51 struct smsc9420_ring_info *tx_buffers;
52 struct smsc9420_ring_info *rx_buffers;
53 dma_addr_t rx_dma_addr;
54 dma_addr_t tx_dma_addr;
55 int tx_ring_head, tx_ring_tail;
56 int rx_ring_head, rx_ring_tail;
58 spinlock_t int_lock;
59 spinlock_t phy_lock;
61 struct napi_struct napi;
63 bool software_irq_signal;
64 bool rx_csum;
65 u32 msg_enable;
67 struct mii_bus *mii_bus;
68 int last_duplex;
69 int last_carrier;
72 static const struct pci_device_id smsc9420_id_table[] = {
73 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, },
74 { 0, }
77 MODULE_DEVICE_TABLE(pci, smsc9420_id_table);
79 #define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
81 static uint smsc_debug;
82 static uint debug = -1;
83 module_param(debug, uint, 0);
84 MODULE_PARM_DESC(debug, "debug level");
86 static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
88 return ioread32(pd->ioaddr + offset);
91 static inline void
92 smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
94 iowrite32(value, pd->ioaddr + offset);
97 static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
99 /* to ensure PCI write completion, we must perform a PCI read */
100 smsc9420_reg_read(pd, ID_REV);
103 static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
105 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
106 unsigned long flags;
107 u32 addr;
108 int i, reg = -EIO;
110 spin_lock_irqsave(&pd->phy_lock, flags);
112 /* confirm MII not busy */
113 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
114 netif_warn(pd, drv, pd->dev, "MII is busy???\n");
115 goto out;
118 /* set the address, index & direction (read from PHY) */
119 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
120 MII_ACCESS_MII_READ_;
121 smsc9420_reg_write(pd, MII_ACCESS, addr);
123 /* wait for read to complete with 50us timeout */
124 for (i = 0; i < 5; i++) {
125 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
126 MII_ACCESS_MII_BUSY_)) {
127 reg = (u16)smsc9420_reg_read(pd, MII_DATA);
128 goto out;
130 udelay(10);
133 netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
135 out:
136 spin_unlock_irqrestore(&pd->phy_lock, flags);
137 return reg;
140 static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
141 u16 val)
143 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
144 unsigned long flags;
145 u32 addr;
146 int i, reg = -EIO;
148 spin_lock_irqsave(&pd->phy_lock, flags);
150 /* confirm MII not busy */
151 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
152 netif_warn(pd, drv, pd->dev, "MII is busy???\n");
153 goto out;
156 /* put the data to write in the MAC */
157 smsc9420_reg_write(pd, MII_DATA, (u32)val);
159 /* set the address, index & direction (write to PHY) */
160 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
161 MII_ACCESS_MII_WRITE_;
162 smsc9420_reg_write(pd, MII_ACCESS, addr);
164 /* wait for write to complete with 50us timeout */
165 for (i = 0; i < 5; i++) {
166 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
167 MII_ACCESS_MII_BUSY_)) {
168 reg = 0;
169 goto out;
171 udelay(10);
174 netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
176 out:
177 spin_unlock_irqrestore(&pd->phy_lock, flags);
178 return reg;
181 /* Returns hash bit number for given MAC address
182 * Example:
183 * 01 00 5E 00 00 01 -> returns bit number 31 */
184 static u32 smsc9420_hash(u8 addr[ETH_ALEN])
186 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
189 static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
191 int timeout = 100000;
193 BUG_ON(!pd);
195 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
196 netif_dbg(pd, drv, pd->dev, "%s: Eeprom busy\n", __func__);
197 return -EIO;
200 smsc9420_reg_write(pd, E2P_CMD,
201 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
203 do {
204 udelay(10);
205 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
206 return 0;
207 } while (timeout--);
209 netif_warn(pd, drv, pd->dev, "%s: Eeprom timed out\n", __func__);
210 return -EIO;
213 static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev,
214 struct ethtool_drvinfo *drvinfo)
216 struct smsc9420_pdata *pd = netdev_priv(netdev);
218 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
219 strlcpy(drvinfo->bus_info, pci_name(pd->pdev),
220 sizeof(drvinfo->bus_info));
221 strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
224 static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev)
226 struct smsc9420_pdata *pd = netdev_priv(netdev);
227 return pd->msg_enable;
230 static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)
232 struct smsc9420_pdata *pd = netdev_priv(netdev);
233 pd->msg_enable = data;
236 static int smsc9420_ethtool_getregslen(struct net_device *dev)
238 /* all smsc9420 registers plus all phy registers */
239 return 0x100 + (32 * sizeof(u32));
242 static void
243 smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
244 void *buf)
246 struct smsc9420_pdata *pd = netdev_priv(dev);
247 struct phy_device *phy_dev = dev->phydev;
248 unsigned int i, j = 0;
249 u32 *data = buf;
251 regs->version = smsc9420_reg_read(pd, ID_REV);
252 for (i = 0; i < 0x100; i += (sizeof(u32)))
253 data[j++] = smsc9420_reg_read(pd, i);
255 // cannot read phy registers if the net device is down
256 if (!phy_dev)
257 return;
259 for (i = 0; i <= 31; i++)
260 data[j++] = smsc9420_mii_read(phy_dev->mdio.bus,
261 phy_dev->mdio.addr, i);
264 static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
266 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
267 temp &= ~GPIO_CFG_EEPR_EN_;
268 smsc9420_reg_write(pd, GPIO_CFG, temp);
269 msleep(1);
272 static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
274 int timeout = 100;
275 u32 e2cmd;
277 netif_dbg(pd, hw, pd->dev, "op 0x%08x\n", op);
278 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
279 netif_warn(pd, hw, pd->dev, "Busy at start\n");
280 return -EBUSY;
283 e2cmd = op | E2P_CMD_EPC_BUSY_;
284 smsc9420_reg_write(pd, E2P_CMD, e2cmd);
286 do {
287 msleep(1);
288 e2cmd = smsc9420_reg_read(pd, E2P_CMD);
289 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
291 if (!timeout) {
292 netif_info(pd, hw, pd->dev, "TIMED OUT\n");
293 return -EAGAIN;
296 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
297 netif_info(pd, hw, pd->dev,
298 "Error occurred during eeprom operation\n");
299 return -EINVAL;
302 return 0;
305 static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
306 u8 address, u8 *data)
308 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
309 int ret;
311 netif_dbg(pd, hw, pd->dev, "address 0x%x\n", address);
312 ret = smsc9420_eeprom_send_cmd(pd, op);
314 if (!ret)
315 data[address] = smsc9420_reg_read(pd, E2P_DATA);
317 return ret;
320 static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
321 u8 address, u8 data)
323 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
324 int ret;
326 netif_dbg(pd, hw, pd->dev, "address 0x%x, data 0x%x\n", address, data);
327 ret = smsc9420_eeprom_send_cmd(pd, op);
329 if (!ret) {
330 op = E2P_CMD_EPC_CMD_WRITE_ | address;
331 smsc9420_reg_write(pd, E2P_DATA, (u32)data);
332 ret = smsc9420_eeprom_send_cmd(pd, op);
335 return ret;
338 static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev)
340 return SMSC9420_EEPROM_SIZE;
343 static int smsc9420_ethtool_get_eeprom(struct net_device *dev,
344 struct ethtool_eeprom *eeprom, u8 *data)
346 struct smsc9420_pdata *pd = netdev_priv(dev);
347 u8 eeprom_data[SMSC9420_EEPROM_SIZE];
348 int len, i;
350 smsc9420_eeprom_enable_access(pd);
352 len = min(eeprom->len, SMSC9420_EEPROM_SIZE);
353 for (i = 0; i < len; i++) {
354 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
355 if (ret < 0) {
356 eeprom->len = 0;
357 return ret;
361 memcpy(data, &eeprom_data[eeprom->offset], len);
362 eeprom->magic = SMSC9420_EEPROM_MAGIC;
363 eeprom->len = len;
364 return 0;
367 static int smsc9420_ethtool_set_eeprom(struct net_device *dev,
368 struct ethtool_eeprom *eeprom, u8 *data)
370 struct smsc9420_pdata *pd = netdev_priv(dev);
371 int ret;
373 if (eeprom->magic != SMSC9420_EEPROM_MAGIC)
374 return -EINVAL;
376 smsc9420_eeprom_enable_access(pd);
377 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
378 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
379 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
381 /* Single byte write, according to man page */
382 eeprom->len = 1;
384 return ret;
387 static const struct ethtool_ops smsc9420_ethtool_ops = {
388 .get_drvinfo = smsc9420_ethtool_get_drvinfo,
389 .get_msglevel = smsc9420_ethtool_get_msglevel,
390 .set_msglevel = smsc9420_ethtool_set_msglevel,
391 .nway_reset = phy_ethtool_nway_reset,
392 .get_link = ethtool_op_get_link,
393 .get_eeprom_len = smsc9420_ethtool_get_eeprom_len,
394 .get_eeprom = smsc9420_ethtool_get_eeprom,
395 .set_eeprom = smsc9420_ethtool_set_eeprom,
396 .get_regs_len = smsc9420_ethtool_getregslen,
397 .get_regs = smsc9420_ethtool_getregs,
398 .get_ts_info = ethtool_op_get_ts_info,
399 .get_link_ksettings = phy_ethtool_get_link_ksettings,
400 .set_link_ksettings = phy_ethtool_set_link_ksettings,
403 /* Sets the device MAC address to dev_addr */
404 static void smsc9420_set_mac_address(struct net_device *dev)
406 struct smsc9420_pdata *pd = netdev_priv(dev);
407 u8 *dev_addr = dev->dev_addr;
408 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
409 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
410 (dev_addr[1] << 8) | dev_addr[0];
412 smsc9420_reg_write(pd, ADDRH, mac_high16);
413 smsc9420_reg_write(pd, ADDRL, mac_low32);
416 static void smsc9420_check_mac_address(struct net_device *dev)
418 struct smsc9420_pdata *pd = netdev_priv(dev);
420 /* Check if mac address has been specified when bringing interface up */
421 if (is_valid_ether_addr(dev->dev_addr)) {
422 smsc9420_set_mac_address(dev);
423 netif_dbg(pd, probe, pd->dev,
424 "MAC Address is specified by configuration\n");
425 } else {
426 /* Try reading mac address from device. if EEPROM is present
427 * it will already have been set */
428 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
429 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
430 dev->dev_addr[0] = (u8)(mac_low32);
431 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
432 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
433 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
434 dev->dev_addr[4] = (u8)(mac_high16);
435 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
437 if (is_valid_ether_addr(dev->dev_addr)) {
438 /* eeprom values are valid so use them */
439 netif_dbg(pd, probe, pd->dev,
440 "Mac Address is read from EEPROM\n");
441 } else {
442 /* eeprom values are invalid, generate random MAC */
443 eth_hw_addr_random(dev);
444 smsc9420_set_mac_address(dev);
445 netif_dbg(pd, probe, pd->dev,
446 "MAC Address is set to random\n");
451 static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
453 u32 dmac_control, mac_cr, dma_intr_ena;
454 int timeout = 1000;
456 /* disable TX DMAC */
457 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
458 dmac_control &= (~DMAC_CONTROL_ST_);
459 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
461 /* Wait max 10ms for transmit process to stop */
462 while (--timeout) {
463 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
464 break;
465 udelay(10);
468 if (!timeout)
469 netif_warn(pd, ifdown, pd->dev, "TX DMAC failed to stop\n");
471 /* ACK Tx DMAC stop bit */
472 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
474 /* mask TX DMAC interrupts */
475 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
476 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_);
477 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
478 smsc9420_pci_flush_write(pd);
480 /* stop MAC TX */
481 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
482 smsc9420_reg_write(pd, MAC_CR, mac_cr);
483 smsc9420_pci_flush_write(pd);
486 static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
488 int i;
490 BUG_ON(!pd->tx_ring);
492 if (!pd->tx_buffers)
493 return;
495 for (i = 0; i < TX_RING_SIZE; i++) {
496 struct sk_buff *skb = pd->tx_buffers[i].skb;
498 if (skb) {
499 BUG_ON(!pd->tx_buffers[i].mapping);
500 pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping,
501 skb->len, PCI_DMA_TODEVICE);
502 dev_kfree_skb_any(skb);
505 pd->tx_ring[i].status = 0;
506 pd->tx_ring[i].length = 0;
507 pd->tx_ring[i].buffer1 = 0;
508 pd->tx_ring[i].buffer2 = 0;
510 wmb();
512 kfree(pd->tx_buffers);
513 pd->tx_buffers = NULL;
515 pd->tx_ring_head = 0;
516 pd->tx_ring_tail = 0;
519 static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
521 int i;
523 BUG_ON(!pd->rx_ring);
525 if (!pd->rx_buffers)
526 return;
528 for (i = 0; i < RX_RING_SIZE; i++) {
529 if (pd->rx_buffers[i].skb)
530 dev_kfree_skb_any(pd->rx_buffers[i].skb);
532 if (pd->rx_buffers[i].mapping)
533 pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping,
534 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
536 pd->rx_ring[i].status = 0;
537 pd->rx_ring[i].length = 0;
538 pd->rx_ring[i].buffer1 = 0;
539 pd->rx_ring[i].buffer2 = 0;
541 wmb();
543 kfree(pd->rx_buffers);
544 pd->rx_buffers = NULL;
546 pd->rx_ring_head = 0;
547 pd->rx_ring_tail = 0;
550 static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
552 int timeout = 1000;
553 u32 mac_cr, dmac_control, dma_intr_ena;
555 /* mask RX DMAC interrupts */
556 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
557 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
558 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
559 smsc9420_pci_flush_write(pd);
561 /* stop RX MAC prior to stoping DMA */
562 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
563 smsc9420_reg_write(pd, MAC_CR, mac_cr);
564 smsc9420_pci_flush_write(pd);
566 /* stop RX DMAC */
567 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
568 dmac_control &= (~DMAC_CONTROL_SR_);
569 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
570 smsc9420_pci_flush_write(pd);
572 /* wait up to 10ms for receive to stop */
573 while (--timeout) {
574 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
575 break;
576 udelay(10);
579 if (!timeout)
580 netif_warn(pd, ifdown, pd->dev,
581 "RX DMAC did not stop! timeout\n");
583 /* ACK the Rx DMAC stop bit */
584 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
587 static irqreturn_t smsc9420_isr(int irq, void *dev_id)
589 struct smsc9420_pdata *pd = dev_id;
590 u32 int_cfg, int_sts, int_ctl;
591 irqreturn_t ret = IRQ_NONE;
592 ulong flags;
594 BUG_ON(!pd);
595 BUG_ON(!pd->ioaddr);
597 int_cfg = smsc9420_reg_read(pd, INT_CFG);
599 /* check if it's our interrupt */
600 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) !=
601 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_))
602 return IRQ_NONE;
604 int_sts = smsc9420_reg_read(pd, INT_STAT);
606 if (likely(INT_STAT_DMAC_INT_ & int_sts)) {
607 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
608 u32 ints_to_clear = 0;
610 if (status & DMAC_STS_TX_) {
611 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_);
612 netif_wake_queue(pd->dev);
615 if (status & DMAC_STS_RX_) {
616 /* mask RX DMAC interrupts */
617 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
618 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
619 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
620 smsc9420_pci_flush_write(pd);
622 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_);
623 napi_schedule(&pd->napi);
626 if (ints_to_clear)
627 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
629 ret = IRQ_HANDLED;
632 if (unlikely(INT_STAT_SW_INT_ & int_sts)) {
633 /* mask software interrupt */
634 spin_lock_irqsave(&pd->int_lock, flags);
635 int_ctl = smsc9420_reg_read(pd, INT_CTL);
636 int_ctl &= (~INT_CTL_SW_INT_EN_);
637 smsc9420_reg_write(pd, INT_CTL, int_ctl);
638 spin_unlock_irqrestore(&pd->int_lock, flags);
640 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
641 pd->software_irq_signal = true;
642 smp_wmb();
644 ret = IRQ_HANDLED;
647 /* to ensure PCI write completion, we must perform a PCI read */
648 smsc9420_pci_flush_write(pd);
650 return ret;
653 #ifdef CONFIG_NET_POLL_CONTROLLER
654 static void smsc9420_poll_controller(struct net_device *dev)
656 struct smsc9420_pdata *pd = netdev_priv(dev);
657 const int irq = pd->pdev->irq;
659 disable_irq(irq);
660 smsc9420_isr(0, dev);
661 enable_irq(irq);
663 #endif /* CONFIG_NET_POLL_CONTROLLER */
665 static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
667 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
668 smsc9420_reg_read(pd, BUS_MODE);
669 udelay(2);
670 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
671 netif_warn(pd, drv, pd->dev, "Software reset not cleared\n");
674 static int smsc9420_stop(struct net_device *dev)
676 struct smsc9420_pdata *pd = netdev_priv(dev);
677 u32 int_cfg;
678 ulong flags;
680 BUG_ON(!pd);
681 BUG_ON(!dev->phydev);
683 /* disable master interrupt */
684 spin_lock_irqsave(&pd->int_lock, flags);
685 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
686 smsc9420_reg_write(pd, INT_CFG, int_cfg);
687 spin_unlock_irqrestore(&pd->int_lock, flags);
689 netif_tx_disable(dev);
690 napi_disable(&pd->napi);
692 smsc9420_stop_tx(pd);
693 smsc9420_free_tx_ring(pd);
695 smsc9420_stop_rx(pd);
696 smsc9420_free_rx_ring(pd);
698 free_irq(pd->pdev->irq, pd);
700 smsc9420_dmac_soft_reset(pd);
702 phy_stop(dev->phydev);
704 phy_disconnect(dev->phydev);
705 mdiobus_unregister(pd->mii_bus);
706 mdiobus_free(pd->mii_bus);
708 return 0;
711 static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status)
713 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) {
714 dev->stats.rx_errors++;
715 if (desc_status & RDES0_DESCRIPTOR_ERROR_)
716 dev->stats.rx_over_errors++;
717 else if (desc_status & (RDES0_FRAME_TOO_LONG_ |
718 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_))
719 dev->stats.rx_frame_errors++;
720 else if (desc_status & RDES0_CRC_ERROR_)
721 dev->stats.rx_crc_errors++;
724 if (unlikely(desc_status & RDES0_LENGTH_ERROR_))
725 dev->stats.rx_length_errors++;
727 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) &&
728 (desc_status & RDES0_FIRST_DESCRIPTOR_))))
729 dev->stats.rx_length_errors++;
731 if (desc_status & RDES0_MULTICAST_FRAME_)
732 dev->stats.multicast++;
735 static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
736 const u32 status)
738 struct net_device *dev = pd->dev;
739 struct sk_buff *skb;
740 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_)
741 >> RDES0_FRAME_LENGTH_SHFT_;
743 /* remove crc from packet lendth */
744 packet_length -= 4;
746 if (pd->rx_csum)
747 packet_length -= 2;
749 dev->stats.rx_packets++;
750 dev->stats.rx_bytes += packet_length;
752 pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping,
753 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
754 pd->rx_buffers[index].mapping = 0;
756 skb = pd->rx_buffers[index].skb;
757 pd->rx_buffers[index].skb = NULL;
759 if (pd->rx_csum) {
760 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) +
761 NET_IP_ALIGN + packet_length + 4);
762 put_unaligned_le16(hw_csum, &skb->csum);
763 skb->ip_summed = CHECKSUM_COMPLETE;
766 skb_reserve(skb, NET_IP_ALIGN);
767 skb_put(skb, packet_length);
769 skb->protocol = eth_type_trans(skb, dev);
771 netif_receive_skb(skb);
774 static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
776 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
777 dma_addr_t mapping;
779 BUG_ON(pd->rx_buffers[index].skb);
780 BUG_ON(pd->rx_buffers[index].mapping);
782 if (unlikely(!skb))
783 return -ENOMEM;
785 mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb),
786 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
787 if (pci_dma_mapping_error(pd->pdev, mapping)) {
788 dev_kfree_skb_any(skb);
789 netif_warn(pd, rx_err, pd->dev, "pci_map_single failed!\n");
790 return -ENOMEM;
793 pd->rx_buffers[index].skb = skb;
794 pd->rx_buffers[index].mapping = mapping;
795 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
796 pd->rx_ring[index].status = RDES0_OWN_;
797 wmb();
799 return 0;
802 static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
804 while (pd->rx_ring_tail != pd->rx_ring_head) {
805 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
806 break;
808 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
812 static int smsc9420_rx_poll(struct napi_struct *napi, int budget)
814 struct smsc9420_pdata *pd =
815 container_of(napi, struct smsc9420_pdata, napi);
816 struct net_device *dev = pd->dev;
817 u32 drop_frame_cnt, dma_intr_ena, status;
818 int work_done;
820 for (work_done = 0; work_done < budget; work_done++) {
821 rmb();
822 status = pd->rx_ring[pd->rx_ring_head].status;
824 /* stop if DMAC owns this dma descriptor */
825 if (status & RDES0_OWN_)
826 break;
828 smsc9420_rx_count_stats(dev, status);
829 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
830 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
831 smsc9420_alloc_new_rx_buffers(pd);
834 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
835 dev->stats.rx_dropped +=
836 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF);
838 /* Kick RXDMA */
839 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
840 smsc9420_pci_flush_write(pd);
842 if (work_done < budget) {
843 napi_complete_done(&pd->napi, work_done);
845 /* re-enable RX DMA interrupts */
846 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
847 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
848 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
849 smsc9420_pci_flush_write(pd);
851 return work_done;
854 static void
855 smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length)
857 if (unlikely(status & TDES0_ERROR_SUMMARY_)) {
858 dev->stats.tx_errors++;
859 if (status & (TDES0_EXCESSIVE_DEFERRAL_ |
860 TDES0_EXCESSIVE_COLLISIONS_))
861 dev->stats.tx_aborted_errors++;
863 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_))
864 dev->stats.tx_carrier_errors++;
865 } else {
866 dev->stats.tx_packets++;
867 dev->stats.tx_bytes += (length & 0x7FF);
870 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) {
871 dev->stats.collisions += 16;
872 } else {
873 dev->stats.collisions +=
874 (status & TDES0_COLLISION_COUNT_MASK_) >>
875 TDES0_COLLISION_COUNT_SHFT_;
878 if (unlikely(status & TDES0_HEARTBEAT_FAIL_))
879 dev->stats.tx_heartbeat_errors++;
882 /* Check for completed dma transfers, update stats and free skbs */
883 static void smsc9420_complete_tx(struct net_device *dev)
885 struct smsc9420_pdata *pd = netdev_priv(dev);
887 while (pd->tx_ring_tail != pd->tx_ring_head) {
888 int index = pd->tx_ring_tail;
889 u32 status, length;
891 rmb();
892 status = pd->tx_ring[index].status;
893 length = pd->tx_ring[index].length;
895 /* Check if DMA still owns this descriptor */
896 if (unlikely(TDES0_OWN_ & status))
897 break;
899 smsc9420_tx_update_stats(dev, status, length);
901 BUG_ON(!pd->tx_buffers[index].skb);
902 BUG_ON(!pd->tx_buffers[index].mapping);
904 pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping,
905 pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE);
906 pd->tx_buffers[index].mapping = 0;
908 dev_kfree_skb_any(pd->tx_buffers[index].skb);
909 pd->tx_buffers[index].skb = NULL;
911 pd->tx_ring[index].buffer1 = 0;
912 wmb();
914 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
918 static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb,
919 struct net_device *dev)
921 struct smsc9420_pdata *pd = netdev_priv(dev);
922 dma_addr_t mapping;
923 int index = pd->tx_ring_head;
924 u32 tmp_desc1;
925 bool about_to_take_last_desc =
926 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
928 smsc9420_complete_tx(dev);
930 rmb();
931 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
932 BUG_ON(pd->tx_buffers[index].skb);
933 BUG_ON(pd->tx_buffers[index].mapping);
935 mapping = pci_map_single(pd->pdev, skb->data,
936 skb->len, PCI_DMA_TODEVICE);
937 if (pci_dma_mapping_error(pd->pdev, mapping)) {
938 netif_warn(pd, tx_err, pd->dev,
939 "pci_map_single failed, dropping packet\n");
940 return NETDEV_TX_BUSY;
943 pd->tx_buffers[index].skb = skb;
944 pd->tx_buffers[index].mapping = mapping;
946 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF));
947 if (unlikely(about_to_take_last_desc)) {
948 tmp_desc1 |= TDES1_IC_;
949 netif_stop_queue(pd->dev);
952 /* check if we are at the last descriptor and need to set EOR */
953 if (unlikely(index == (TX_RING_SIZE - 1)))
954 tmp_desc1 |= TDES1_TER_;
956 pd->tx_ring[index].buffer1 = mapping;
957 pd->tx_ring[index].length = tmp_desc1;
958 wmb();
960 /* increment head */
961 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
963 /* assign ownership to DMAC */
964 pd->tx_ring[index].status = TDES0_OWN_;
965 wmb();
967 skb_tx_timestamp(skb);
969 /* kick the DMA */
970 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
971 smsc9420_pci_flush_write(pd);
973 return NETDEV_TX_OK;
976 static struct net_device_stats *smsc9420_get_stats(struct net_device *dev)
978 struct smsc9420_pdata *pd = netdev_priv(dev);
979 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
980 dev->stats.rx_dropped +=
981 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF);
982 return &dev->stats;
985 static void smsc9420_set_multicast_list(struct net_device *dev)
987 struct smsc9420_pdata *pd = netdev_priv(dev);
988 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
990 if (dev->flags & IFF_PROMISC) {
991 netif_dbg(pd, hw, pd->dev, "Promiscuous Mode Enabled\n");
992 mac_cr |= MAC_CR_PRMS_;
993 mac_cr &= (~MAC_CR_MCPAS_);
994 mac_cr &= (~MAC_CR_HPFILT_);
995 } else if (dev->flags & IFF_ALLMULTI) {
996 netif_dbg(pd, hw, pd->dev, "Receive all Multicast Enabled\n");
997 mac_cr &= (~MAC_CR_PRMS_);
998 mac_cr |= MAC_CR_MCPAS_;
999 mac_cr &= (~MAC_CR_HPFILT_);
1000 } else if (!netdev_mc_empty(dev)) {
1001 struct netdev_hw_addr *ha;
1002 u32 hash_lo = 0, hash_hi = 0;
1004 netif_dbg(pd, hw, pd->dev, "Multicast filter enabled\n");
1005 netdev_for_each_mc_addr(ha, dev) {
1006 u32 bit_num = smsc9420_hash(ha->addr);
1007 u32 mask = 1 << (bit_num & 0x1F);
1009 if (bit_num & 0x20)
1010 hash_hi |= mask;
1011 else
1012 hash_lo |= mask;
1015 smsc9420_reg_write(pd, HASHH, hash_hi);
1016 smsc9420_reg_write(pd, HASHL, hash_lo);
1018 mac_cr &= (~MAC_CR_PRMS_);
1019 mac_cr &= (~MAC_CR_MCPAS_);
1020 mac_cr |= MAC_CR_HPFILT_;
1021 } else {
1022 netif_dbg(pd, hw, pd->dev, "Receive own packets only\n");
1023 smsc9420_reg_write(pd, HASHH, 0);
1024 smsc9420_reg_write(pd, HASHL, 0);
1026 mac_cr &= (~MAC_CR_PRMS_);
1027 mac_cr &= (~MAC_CR_MCPAS_);
1028 mac_cr &= (~MAC_CR_HPFILT_);
1031 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1032 smsc9420_pci_flush_write(pd);
1035 static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
1037 struct net_device *dev = pd->dev;
1038 struct phy_device *phy_dev = dev->phydev;
1039 u32 flow;
1041 if (phy_dev->duplex == DUPLEX_FULL) {
1042 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
1043 u16 rmtadv = phy_read(phy_dev, MII_LPA);
1044 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1046 if (cap & FLOW_CTRL_RX)
1047 flow = 0xFFFF0002;
1048 else
1049 flow = 0;
1051 netif_info(pd, link, pd->dev, "rx pause %s, tx pause %s\n",
1052 cap & FLOW_CTRL_RX ? "enabled" : "disabled",
1053 cap & FLOW_CTRL_TX ? "enabled" : "disabled");
1054 } else {
1055 netif_info(pd, link, pd->dev, "half duplex\n");
1056 flow = 0;
1059 smsc9420_reg_write(pd, FLOW, flow);
1062 /* Update link mode if anything has changed. Called periodically when the
1063 * PHY is in polling mode, even if nothing has changed. */
1064 static void smsc9420_phy_adjust_link(struct net_device *dev)
1066 struct smsc9420_pdata *pd = netdev_priv(dev);
1067 struct phy_device *phy_dev = dev->phydev;
1068 int carrier;
1070 if (phy_dev->duplex != pd->last_duplex) {
1071 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1072 if (phy_dev->duplex) {
1073 netif_dbg(pd, link, pd->dev, "full duplex mode\n");
1074 mac_cr |= MAC_CR_FDPX_;
1075 } else {
1076 netif_dbg(pd, link, pd->dev, "half duplex mode\n");
1077 mac_cr &= ~MAC_CR_FDPX_;
1079 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1081 smsc9420_phy_update_flowcontrol(pd);
1082 pd->last_duplex = phy_dev->duplex;
1085 carrier = netif_carrier_ok(dev);
1086 if (carrier != pd->last_carrier) {
1087 if (carrier)
1088 netif_dbg(pd, link, pd->dev, "carrier OK\n");
1089 else
1090 netif_dbg(pd, link, pd->dev, "no carrier\n");
1091 pd->last_carrier = carrier;
1095 static int smsc9420_mii_probe(struct net_device *dev)
1097 struct smsc9420_pdata *pd = netdev_priv(dev);
1098 struct phy_device *phydev = NULL;
1100 BUG_ON(dev->phydev);
1102 /* Device only supports internal PHY at address 1 */
1103 phydev = mdiobus_get_phy(pd->mii_bus, 1);
1104 if (!phydev) {
1105 netdev_err(dev, "no PHY found at address 1\n");
1106 return -ENODEV;
1109 phydev = phy_connect(dev, phydev_name(phydev),
1110 smsc9420_phy_adjust_link, PHY_INTERFACE_MODE_MII);
1112 if (IS_ERR(phydev)) {
1113 netdev_err(dev, "Could not attach to PHY\n");
1114 return PTR_ERR(phydev);
1117 phy_set_max_speed(phydev, SPEED_100);
1119 /* mask with MAC supported features */
1120 phy_support_asym_pause(phydev);
1122 phy_attached_info(phydev);
1124 pd->last_duplex = -1;
1125 pd->last_carrier = -1;
1127 return 0;
1130 static int smsc9420_mii_init(struct net_device *dev)
1132 struct smsc9420_pdata *pd = netdev_priv(dev);
1133 int err = -ENXIO;
1135 pd->mii_bus = mdiobus_alloc();
1136 if (!pd->mii_bus) {
1137 err = -ENOMEM;
1138 goto err_out_1;
1140 pd->mii_bus->name = DRV_MDIONAME;
1141 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
1142 (pd->pdev->bus->number << 8) | pd->pdev->devfn);
1143 pd->mii_bus->priv = pd;
1144 pd->mii_bus->read = smsc9420_mii_read;
1145 pd->mii_bus->write = smsc9420_mii_write;
1147 /* Mask all PHYs except ID 1 (internal) */
1148 pd->mii_bus->phy_mask = ~(1 << 1);
1150 if (mdiobus_register(pd->mii_bus)) {
1151 netif_warn(pd, probe, pd->dev, "Error registering mii bus\n");
1152 goto err_out_free_bus_2;
1155 if (smsc9420_mii_probe(dev) < 0) {
1156 netif_warn(pd, probe, pd->dev, "Error probing mii bus\n");
1157 goto err_out_unregister_bus_3;
1160 return 0;
1162 err_out_unregister_bus_3:
1163 mdiobus_unregister(pd->mii_bus);
1164 err_out_free_bus_2:
1165 mdiobus_free(pd->mii_bus);
1166 err_out_1:
1167 return err;
1170 static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1172 int i;
1174 BUG_ON(!pd->tx_ring);
1176 pd->tx_buffers = kmalloc_array(TX_RING_SIZE,
1177 sizeof(struct smsc9420_ring_info),
1178 GFP_KERNEL);
1179 if (!pd->tx_buffers)
1180 return -ENOMEM;
1182 /* Initialize the TX Ring */
1183 for (i = 0; i < TX_RING_SIZE; i++) {
1184 pd->tx_buffers[i].skb = NULL;
1185 pd->tx_buffers[i].mapping = 0;
1186 pd->tx_ring[i].status = 0;
1187 pd->tx_ring[i].length = 0;
1188 pd->tx_ring[i].buffer1 = 0;
1189 pd->tx_ring[i].buffer2 = 0;
1191 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1192 wmb();
1194 pd->tx_ring_head = 0;
1195 pd->tx_ring_tail = 0;
1197 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1198 smsc9420_pci_flush_write(pd);
1200 return 0;
1203 static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1205 int i;
1207 BUG_ON(!pd->rx_ring);
1209 pd->rx_buffers = kmalloc_array(RX_RING_SIZE,
1210 sizeof(struct smsc9420_ring_info),
1211 GFP_KERNEL);
1212 if (pd->rx_buffers == NULL)
1213 goto out;
1215 /* initialize the rx ring */
1216 for (i = 0; i < RX_RING_SIZE; i++) {
1217 pd->rx_ring[i].status = 0;
1218 pd->rx_ring[i].length = PKT_BUF_SZ;
1219 pd->rx_ring[i].buffer2 = 0;
1220 pd->rx_buffers[i].skb = NULL;
1221 pd->rx_buffers[i].mapping = 0;
1223 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1225 /* now allocate the entire ring of skbs */
1226 for (i = 0; i < RX_RING_SIZE; i++) {
1227 if (smsc9420_alloc_rx_buffer(pd, i)) {
1228 netif_warn(pd, ifup, pd->dev,
1229 "failed to allocate rx skb %d\n", i);
1230 goto out_free_rx_skbs;
1234 pd->rx_ring_head = 0;
1235 pd->rx_ring_tail = 0;
1237 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1238 netif_dbg(pd, ifup, pd->dev, "VLAN1 = 0x%08x\n",
1239 smsc9420_reg_read(pd, VLAN1));
1241 if (pd->rx_csum) {
1242 /* Enable RX COE */
1243 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1244 smsc9420_reg_write(pd, COE_CR, coe);
1245 netif_dbg(pd, ifup, pd->dev, "COE_CR = 0x%08x\n", coe);
1248 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1249 smsc9420_pci_flush_write(pd);
1251 return 0;
1253 out_free_rx_skbs:
1254 smsc9420_free_rx_ring(pd);
1255 out:
1256 return -ENOMEM;
1259 static int smsc9420_open(struct net_device *dev)
1261 struct smsc9420_pdata *pd = netdev_priv(dev);
1262 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl;
1263 const int irq = pd->pdev->irq;
1264 unsigned long flags;
1265 int result = 0, timeout;
1267 if (!is_valid_ether_addr(dev->dev_addr)) {
1268 netif_warn(pd, ifup, pd->dev,
1269 "dev_addr is not a valid MAC address\n");
1270 result = -EADDRNOTAVAIL;
1271 goto out_0;
1274 netif_carrier_off(dev);
1276 /* disable, mask and acknowledge all interrupts */
1277 spin_lock_irqsave(&pd->int_lock, flags);
1278 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1279 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1280 smsc9420_reg_write(pd, INT_CTL, 0);
1281 spin_unlock_irqrestore(&pd->int_lock, flags);
1282 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1283 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1284 smsc9420_pci_flush_write(pd);
1286 result = request_irq(irq, smsc9420_isr, IRQF_SHARED, DRV_NAME, pd);
1287 if (result) {
1288 netif_warn(pd, ifup, pd->dev, "Unable to use IRQ = %d\n", irq);
1289 result = -ENODEV;
1290 goto out_0;
1293 smsc9420_dmac_soft_reset(pd);
1295 /* make sure MAC_CR is sane */
1296 smsc9420_reg_write(pd, MAC_CR, 0);
1298 smsc9420_set_mac_address(dev);
1300 /* Configure GPIO pins to drive LEDs */
1301 smsc9420_reg_write(pd, GPIO_CFG,
1302 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_));
1304 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16;
1306 #ifdef __BIG_ENDIAN
1307 bus_mode |= BUS_MODE_DBO_;
1308 #endif
1310 smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1312 smsc9420_pci_flush_write(pd);
1314 /* set bus master bridge arbitration priority for Rx and TX DMA */
1315 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1317 smsc9420_reg_write(pd, DMAC_CONTROL,
1318 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_));
1320 smsc9420_pci_flush_write(pd);
1322 /* test the IRQ connection to the ISR */
1323 netif_dbg(pd, ifup, pd->dev, "Testing ISR using IRQ %d\n", irq);
1324 pd->software_irq_signal = false;
1326 spin_lock_irqsave(&pd->int_lock, flags);
1327 /* configure interrupt deassertion timer and enable interrupts */
1328 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1329 int_cfg &= ~(INT_CFG_INT_DEAS_MASK);
1330 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK);
1331 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1333 /* unmask software interrupt */
1334 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1335 smsc9420_reg_write(pd, INT_CTL, int_ctl);
1336 spin_unlock_irqrestore(&pd->int_lock, flags);
1337 smsc9420_pci_flush_write(pd);
1339 timeout = 1000;
1340 while (timeout--) {
1341 if (pd->software_irq_signal)
1342 break;
1343 msleep(1);
1346 /* disable interrupts */
1347 spin_lock_irqsave(&pd->int_lock, flags);
1348 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1349 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1350 spin_unlock_irqrestore(&pd->int_lock, flags);
1352 if (!pd->software_irq_signal) {
1353 netif_warn(pd, ifup, pd->dev, "ISR failed signaling test\n");
1354 result = -ENODEV;
1355 goto out_free_irq_1;
1358 netif_dbg(pd, ifup, pd->dev, "ISR passed test using IRQ %d\n", irq);
1360 result = smsc9420_alloc_tx_ring(pd);
1361 if (result) {
1362 netif_warn(pd, ifup, pd->dev,
1363 "Failed to Initialize tx dma ring\n");
1364 result = -ENOMEM;
1365 goto out_free_irq_1;
1368 result = smsc9420_alloc_rx_ring(pd);
1369 if (result) {
1370 netif_warn(pd, ifup, pd->dev,
1371 "Failed to Initialize rx dma ring\n");
1372 result = -ENOMEM;
1373 goto out_free_tx_ring_2;
1376 result = smsc9420_mii_init(dev);
1377 if (result) {
1378 netif_warn(pd, ifup, pd->dev, "Failed to initialize Phy\n");
1379 result = -ENODEV;
1380 goto out_free_rx_ring_3;
1383 /* Bring the PHY up */
1384 phy_start(dev->phydev);
1386 napi_enable(&pd->napi);
1388 /* start tx and rx */
1389 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1390 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1392 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1393 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_;
1394 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1395 smsc9420_pci_flush_write(pd);
1397 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1398 dma_intr_ena |=
1399 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
1400 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1401 smsc9420_pci_flush_write(pd);
1403 netif_wake_queue(dev);
1405 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1407 /* enable interrupts */
1408 spin_lock_irqsave(&pd->int_lock, flags);
1409 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1410 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1411 spin_unlock_irqrestore(&pd->int_lock, flags);
1413 return 0;
1415 out_free_rx_ring_3:
1416 smsc9420_free_rx_ring(pd);
1417 out_free_tx_ring_2:
1418 smsc9420_free_tx_ring(pd);
1419 out_free_irq_1:
1420 free_irq(irq, pd);
1421 out_0:
1422 return result;
1425 #ifdef CONFIG_PM
1427 static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state)
1429 struct net_device *dev = pci_get_drvdata(pdev);
1430 struct smsc9420_pdata *pd = netdev_priv(dev);
1431 u32 int_cfg;
1432 ulong flags;
1434 /* disable interrupts */
1435 spin_lock_irqsave(&pd->int_lock, flags);
1436 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1437 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1438 spin_unlock_irqrestore(&pd->int_lock, flags);
1440 if (netif_running(dev)) {
1441 netif_tx_disable(dev);
1442 smsc9420_stop_tx(pd);
1443 smsc9420_free_tx_ring(pd);
1445 napi_disable(&pd->napi);
1446 smsc9420_stop_rx(pd);
1447 smsc9420_free_rx_ring(pd);
1449 free_irq(pd->pdev->irq, pd);
1451 netif_device_detach(dev);
1454 pci_save_state(pdev);
1455 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1456 pci_disable_device(pdev);
1457 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1459 return 0;
1462 static int smsc9420_resume(struct pci_dev *pdev)
1464 struct net_device *dev = pci_get_drvdata(pdev);
1465 struct smsc9420_pdata *pd = netdev_priv(dev);
1466 int err;
1468 pci_set_power_state(pdev, PCI_D0);
1469 pci_restore_state(pdev);
1471 err = pci_enable_device(pdev);
1472 if (err)
1473 return err;
1475 pci_set_master(pdev);
1477 err = pci_enable_wake(pdev, PCI_D0, 0);
1478 if (err)
1479 netif_warn(pd, ifup, pd->dev, "pci_enable_wake failed: %d\n",
1480 err);
1482 if (netif_running(dev)) {
1483 /* FIXME: gross. It looks like ancient PM relic.*/
1484 err = smsc9420_open(dev);
1485 netif_device_attach(dev);
1487 return err;
1490 #endif /* CONFIG_PM */
1492 static const struct net_device_ops smsc9420_netdev_ops = {
1493 .ndo_open = smsc9420_open,
1494 .ndo_stop = smsc9420_stop,
1495 .ndo_start_xmit = smsc9420_hard_start_xmit,
1496 .ndo_get_stats = smsc9420_get_stats,
1497 .ndo_set_rx_mode = smsc9420_set_multicast_list,
1498 .ndo_do_ioctl = phy_do_ioctl_running,
1499 .ndo_validate_addr = eth_validate_addr,
1500 .ndo_set_mac_address = eth_mac_addr,
1501 #ifdef CONFIG_NET_POLL_CONTROLLER
1502 .ndo_poll_controller = smsc9420_poll_controller,
1503 #endif /* CONFIG_NET_POLL_CONTROLLER */
1506 static int
1507 smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1509 struct net_device *dev;
1510 struct smsc9420_pdata *pd;
1511 void __iomem *virt_addr;
1512 int result = 0;
1513 u32 id_rev;
1515 pr_info("%s version %s\n", DRV_DESCRIPTION, DRV_VERSION);
1517 /* First do the PCI initialisation */
1518 result = pci_enable_device(pdev);
1519 if (unlikely(result)) {
1520 pr_err("Cannot enable smsc9420\n");
1521 goto out_0;
1524 pci_set_master(pdev);
1526 dev = alloc_etherdev(sizeof(*pd));
1527 if (!dev)
1528 goto out_disable_pci_device_1;
1530 SET_NETDEV_DEV(dev, &pdev->dev);
1532 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) {
1533 netdev_err(dev, "Cannot find PCI device base address\n");
1534 goto out_free_netdev_2;
1537 if ((pci_request_regions(pdev, DRV_NAME))) {
1538 netdev_err(dev, "Cannot obtain PCI resources, aborting\n");
1539 goto out_free_netdev_2;
1542 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1543 netdev_err(dev, "No usable DMA configuration, aborting\n");
1544 goto out_free_regions_3;
1547 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR),
1548 pci_resource_len(pdev, SMSC_BAR));
1549 if (!virt_addr) {
1550 netdev_err(dev, "Cannot map device registers, aborting\n");
1551 goto out_free_regions_3;
1554 /* registers are double mapped with 0 offset for LE and 0x200 for BE */
1555 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET;
1557 pd = netdev_priv(dev);
1559 /* pci descriptors are created in the PCI consistent area */
1560 pd->rx_ring = pci_alloc_consistent(pdev,
1561 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE +
1562 sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE,
1563 &pd->rx_dma_addr);
1565 if (!pd->rx_ring)
1566 goto out_free_io_4;
1568 /* descriptors are aligned due to the nature of pci_alloc_consistent */
1569 pd->tx_ring = (pd->rx_ring + RX_RING_SIZE);
1570 pd->tx_dma_addr = pd->rx_dma_addr +
1571 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE;
1573 pd->pdev = pdev;
1574 pd->dev = dev;
1575 pd->ioaddr = virt_addr;
1576 pd->msg_enable = smsc_debug;
1577 pd->rx_csum = true;
1579 netif_dbg(pd, probe, pd->dev, "lan_base=0x%08lx\n", (ulong)virt_addr);
1581 id_rev = smsc9420_reg_read(pd, ID_REV);
1582 switch (id_rev & 0xFFFF0000) {
1583 case 0x94200000:
1584 netif_info(pd, probe, pd->dev,
1585 "LAN9420 identified, ID_REV=0x%08X\n", id_rev);
1586 break;
1587 default:
1588 netif_warn(pd, probe, pd->dev, "LAN9420 NOT identified\n");
1589 netif_warn(pd, probe, pd->dev, "ID_REV=0x%08X\n", id_rev);
1590 goto out_free_dmadesc_5;
1593 smsc9420_dmac_soft_reset(pd);
1594 smsc9420_eeprom_reload(pd);
1595 smsc9420_check_mac_address(dev);
1597 dev->netdev_ops = &smsc9420_netdev_ops;
1598 dev->ethtool_ops = &smsc9420_ethtool_ops;
1600 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT);
1602 result = register_netdev(dev);
1603 if (result) {
1604 netif_warn(pd, probe, pd->dev, "error %i registering device\n",
1605 result);
1606 goto out_free_dmadesc_5;
1609 pci_set_drvdata(pdev, dev);
1611 spin_lock_init(&pd->int_lock);
1612 spin_lock_init(&pd->phy_lock);
1614 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1616 return 0;
1618 out_free_dmadesc_5:
1619 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1620 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1621 out_free_io_4:
1622 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1623 out_free_regions_3:
1624 pci_release_regions(pdev);
1625 out_free_netdev_2:
1626 free_netdev(dev);
1627 out_disable_pci_device_1:
1628 pci_disable_device(pdev);
1629 out_0:
1630 return -ENODEV;
1633 static void smsc9420_remove(struct pci_dev *pdev)
1635 struct net_device *dev;
1636 struct smsc9420_pdata *pd;
1638 dev = pci_get_drvdata(pdev);
1639 if (!dev)
1640 return;
1642 pd = netdev_priv(dev);
1643 unregister_netdev(dev);
1645 /* tx_buffers and rx_buffers are freed in stop */
1646 BUG_ON(pd->tx_buffers);
1647 BUG_ON(pd->rx_buffers);
1649 BUG_ON(!pd->tx_ring);
1650 BUG_ON(!pd->rx_ring);
1652 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1653 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1655 iounmap(pd->ioaddr - LAN9420_CPSR_ENDIAN_OFFSET);
1656 pci_release_regions(pdev);
1657 free_netdev(dev);
1658 pci_disable_device(pdev);
1661 static struct pci_driver smsc9420_driver = {
1662 .name = DRV_NAME,
1663 .id_table = smsc9420_id_table,
1664 .probe = smsc9420_probe,
1665 .remove = smsc9420_remove,
1666 #ifdef CONFIG_PM
1667 .suspend = smsc9420_suspend,
1668 .resume = smsc9420_resume,
1669 #endif /* CONFIG_PM */
1672 static int __init smsc9420_init_module(void)
1674 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT);
1676 return pci_register_driver(&smsc9420_driver);
1679 static void __exit smsc9420_exit_module(void)
1681 pci_unregister_driver(&smsc9420_driver);
1684 module_init(smsc9420_init_module);
1685 module_exit(smsc9420_exit_module);