drivers/net/ethernet/ti/am65-cpsw-nuss.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  */
   5
   6 #ifndef AM65_CPSW_NUSS_H_
   7 #define AM65_CPSW_NUSS_H_
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/netdevice.h>
  12
  13 #define HOST_PORT_NUM           0
  14
  15 #define AM65_CPSW_MAX_TX_QUEUES 8
  16 #define AM65_CPSW_MAX_RX_QUEUES 1
  17 #define AM65_CPSW_MAX_RX_FLOWS  1
  18
  19 struct am65_cpsw_slave_data {
  20         bool                            mac_only;
  21         struct cpsw_sl                  *mac_sl;
  22         struct device_node              *phy_node;
  23         struct phy_device               *phy;
  24         phy_interface_t                 phy_if;
  25         struct phy                      *ifphy;
  26         bool                            rx_pause;
  27         bool                            tx_pause;
  28         u8                              mac_addr[ETH_ALEN];
  29 };
  30
  31 struct am65_cpsw_port {
  32         struct am65_cpsw_common         *common;
  33         struct net_device               *ndev;
  34         const char                      *name;
  35         u32                             port_id;
  36         void __iomem                    *port_base;
  37         void __iomem                    *stat_base;
  38         bool                            disabled;
  39         struct am65_cpsw_slave_data     slave;
  40 };
  41
  42 struct am65_cpsw_host {
  43         struct am65_cpsw_common         *common;
  44         void __iomem                    *port_base;
  45         void __iomem                    *stat_base;
  46 };
  47
  48 struct am65_cpsw_tx_chn {
  49         struct napi_struct napi_tx;
  50         struct am65_cpsw_common *common;
  51         struct k3_cppi_desc_pool *desc_pool;
  52         struct k3_udma_glue_tx_channel *tx_chn;
  53         int irq;
  54         u32 id;
  55         u32 descs_num;
  56         char tx_chn_name[128];
  57 };
  58
  59 struct am65_cpsw_rx_chn {
  60         struct device *dev;
  61         struct k3_cppi_desc_pool *desc_pool;
  62         struct k3_udma_glue_rx_channel *rx_chn;
  63         u32 descs_num;
  64         int irq;
  65 };
  66
  67 #define AM65_CPSW_QUIRK_I2027_NO_TX_CSUM BIT(0)
  68
  69 struct am65_cpsw_pdata {
  70         u32     quirks;
  71 };
  72
  73 struct am65_cpsw_common {
  74         struct device           *dev;
  75         const struct am65_cpsw_pdata *pdata;
  76
  77         void __iomem            *ss_base;
  78         void __iomem            *cpsw_base;
  79
  80         u32                     port_num;
  81         struct am65_cpsw_host   host;
  82         struct am65_cpsw_port   *ports;
  83         u32                     disabled_ports_mask;
  84
  85         int                     usage_count; /* number of opened ports */
  86         struct cpsw_ale         *ale;
  87         int                     tx_ch_num;
  88         u32                     rx_flow_id_base;
  89
  90         struct am65_cpsw_tx_chn tx_chns[AM65_CPSW_MAX_TX_QUEUES];
  91         struct completion       tdown_complete;
  92         atomic_t                tdown_cnt;
  93
  94         struct am65_cpsw_rx_chn rx_chns;
  95         struct napi_struct      napi_rx;
  96
  97         u32                     nuss_ver;
  98         u32                     cpsw_ver;
  99
 100         bool                    pf_p0_rx_ptype_rrobin;
 101 };
 102
 103 struct am65_cpsw_ndev_stats {
 104         u64 tx_packets;
 105         u64 tx_bytes;
 106         u64 rx_packets;
 107         u64 rx_bytes;
 108         struct u64_stats_sync syncp;
 109 };
 110
 111 struct am65_cpsw_ndev_priv {
 112         u32                     msg_enable;
 113         struct am65_cpsw_port   *port;
 114         struct am65_cpsw_ndev_stats __percpu *stats;
 115 };
 116
 117 #define am65_ndev_to_priv(ndev) \
 118         ((struct am65_cpsw_ndev_priv *)netdev_priv(ndev))
 119 #define am65_ndev_to_port(ndev) (am65_ndev_to_priv(ndev)->port)
 120 #define am65_ndev_to_common(ndev) (am65_ndev_to_port(ndev)->common)
 121 #define am65_ndev_to_slave(ndev) (&am65_ndev_to_port(ndev)->slave)
 122
 123 #define am65_common_get_host(common) (&(common)->host)
 124 #define am65_common_get_port(common, id) (&(common)->ports[(id) - 1])
 125
 126 #define am65_cpsw_napi_to_common(pnapi) \
 127         container_of(pnapi, struct am65_cpsw_common, napi_rx)
 128 #define am65_cpsw_napi_to_tx_chn(pnapi) \
 129         container_of(pnapi, struct am65_cpsw_tx_chn, napi_tx)
 130
 131 #define AM65_CPSW_DRV_NAME "am65-cpsw-nuss"
 132
 133 #define AM65_CPSW_IS_CPSW2G(common) ((common)->port_num == 1)
 134
 135 extern const struct ethtool_ops am65_cpsw_ethtool_ops_slave;
 136
 137 void am65_cpsw_nuss_adjust_link(struct net_device *ndev);
 138 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common);
 139 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common);
 140 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx);
 141
 142 #endif /* AM65_CPSW_NUSS_H_ */