drivers/net/wireless/intel/iwlwifi/fw/api/phy-ctxt.h

   1 /******************************************************************************
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   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  11  * Copyright(c) 2018        Intel Corporation
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  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of version 2 of the GNU General Public License as
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  26  *  Intel Linux Wireless <linuxwifi@intel.com>
  27  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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  29  * BSD LICENSE
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  31  * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  32  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  33  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  34  * Copyright(c) 2018        Intel Corporation
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  63  *****************************************************************************/
  64
  65 #ifndef __iwl_fw_api_phy_ctxt_h__
  66 #define __iwl_fw_api_phy_ctxt_h__
  67
  68 /* Supported bands */
  69 #define PHY_BAND_5  (0)
  70 #define PHY_BAND_24 (1)
  71
  72 /* Supported channel width, vary if there is VHT support */
  73 #define PHY_VHT_CHANNEL_MODE20  (0x0)
  74 #define PHY_VHT_CHANNEL_MODE40  (0x1)
  75 #define PHY_VHT_CHANNEL_MODE80  (0x2)
  76 #define PHY_VHT_CHANNEL_MODE160 (0x3)
  77
  78 /*
  79  * Control channel position:
  80  * For legacy set bit means upper channel, otherwise lower.
  81  * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
  82  *   bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
  83  *                                   center_freq
  84  *                                        |
  85  * 40Mhz                          |_______|_______|
  86  * 80Mhz                  |_______|_______|_______|_______|
  87  * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
  88  * code      011     010     001     000  |  100     101     110    111
  89  */
  90 #define PHY_VHT_CTRL_POS_1_BELOW  (0x0)
  91 #define PHY_VHT_CTRL_POS_2_BELOW  (0x1)
  92 #define PHY_VHT_CTRL_POS_3_BELOW  (0x2)
  93 #define PHY_VHT_CTRL_POS_4_BELOW  (0x3)
  94 #define PHY_VHT_CTRL_POS_1_ABOVE  (0x4)
  95 #define PHY_VHT_CTRL_POS_2_ABOVE  (0x5)
  96 #define PHY_VHT_CTRL_POS_3_ABOVE  (0x6)
  97 #define PHY_VHT_CTRL_POS_4_ABOVE  (0x7)
  98
  99 /*
 100  * struct iwl_fw_channel_info_v1 - channel information
 101  *
 102  * @band: PHY_BAND_*
 103  * @channel: channel number
 104  * @width: PHY_[VHT|LEGACY]_CHANNEL_*
 105  * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
 106  */
 107 struct iwl_fw_channel_info_v1 {
 108         u8 band;
 109         u8 channel;
 110         u8 width;
 111         u8 ctrl_pos;
 112 } __packed; /* CHANNEL_CONFIG_API_S_VER_1 */
 113
 114 /*
 115  * struct iwl_fw_channel_info - channel information
 116  *
 117  * @channel: channel number
 118  * @band: PHY_BAND_*
 119  * @width: PHY_[VHT|LEGACY]_CHANNEL_*
 120  * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
 121  * @reserved: for future use and alignment
 122  */
 123 struct iwl_fw_channel_info {
 124         __le32 channel;
 125         u8 band;
 126         u8 width;
 127         u8 ctrl_pos;
 128         u8 reserved;
 129 } __packed; /*CHANNEL_CONFIG_API_S_VER_2 */
 130
 131 #define PHY_RX_CHAIN_DRIVER_FORCE_POS   (0)
 132 #define PHY_RX_CHAIN_DRIVER_FORCE_MSK \
 133         (0x1 << PHY_RX_CHAIN_DRIVER_FORCE_POS)
 134 #define PHY_RX_CHAIN_VALID_POS          (1)
 135 #define PHY_RX_CHAIN_VALID_MSK \
 136         (0x7 << PHY_RX_CHAIN_VALID_POS)
 137 #define PHY_RX_CHAIN_FORCE_SEL_POS      (4)
 138 #define PHY_RX_CHAIN_FORCE_SEL_MSK \
 139         (0x7 << PHY_RX_CHAIN_FORCE_SEL_POS)
 140 #define PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
 141 #define PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
 142         (0x7 << PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
 143 #define PHY_RX_CHAIN_CNT_POS            (10)
 144 #define PHY_RX_CHAIN_CNT_MSK \
 145         (0x3 << PHY_RX_CHAIN_CNT_POS)
 146 #define PHY_RX_CHAIN_MIMO_CNT_POS       (12)
 147 #define PHY_RX_CHAIN_MIMO_CNT_MSK \
 148         (0x3 << PHY_RX_CHAIN_MIMO_CNT_POS)
 149 #define PHY_RX_CHAIN_MIMO_FORCE_POS     (14)
 150 #define PHY_RX_CHAIN_MIMO_FORCE_MSK \
 151         (0x1 << PHY_RX_CHAIN_MIMO_FORCE_POS)
 152
 153 /* TODO: fix the value, make it depend on firmware at runtime? */
 154 #define NUM_PHY_CTX     3
 155
 156 /* TODO: complete missing documentation */
 157 /**
 158  * struct iwl_phy_context_cmd_tail - tail of iwl_phy_ctx_cmd for alignment with
 159  *      various channel structures.
 160  *
 161  * @txchain_info: ???
 162  * @rxchain_info: ???
 163  * @acquisition_data: ???
 164  * @dsp_cfg_flags: set to 0
 165  */
 166 struct iwl_phy_context_cmd_tail {
 167         __le32 txchain_info;
 168         __le32 rxchain_info;
 169         __le32 acquisition_data;
 170         __le32 dsp_cfg_flags;
 171 } __packed;
 172
 173 /**
 174  * struct iwl_phy_context_cmd - config of the PHY context
 175  * ( PHY_CONTEXT_CMD = 0x8 )
 176  * @id_and_color: ID and color of the relevant Binding
 177  * @action: action to perform, one of FW_CTXT_ACTION_*
 178  * @apply_time: 0 means immediate apply and context switch.
 179  *      other value means apply new params after X usecs
 180  * @tx_param_color: ???
 181  * @ci: channel info
 182  * @tail: command tail
 183  */
 184 struct iwl_phy_context_cmd {
 185         /* COMMON_INDEX_HDR_API_S_VER_1 */
 186         __le32 id_and_color;
 187         __le32 action;
 188         /* PHY_CONTEXT_DATA_API_S_VER_1 */
 189         __le32 apply_time;
 190         __le32 tx_param_color;
 191         struct iwl_fw_channel_info ci;
 192         struct iwl_phy_context_cmd_tail tail;
 193 } __packed; /* PHY_CONTEXT_CMD_API_VER_1 */
 194
 195 #endif /* __iwl_fw_api_phy_ctxt_h__ */