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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / net / wireless / intel / iwlwifi / iwl-eeprom-parse.c
blobcf7e2a9232e525bed83d8d979ef1513c7154e3a9
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2018 - 2019 Intel Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called COPYING.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <linuxwifi@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 * BSD LICENSE
29 *
30 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
31 * Copyright(c) 2015 Intel Mobile Communications GmbH
32 * Copyright(c) 2018 - 2019 Intel Corporation
33 * All rights reserved.
34 *
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
37 * are met:
38 *
39 * * Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * * Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in
43 * the documentation and/or other materials provided with the
44 * distribution.
45 * * Neither the name Intel Corporation nor the names of its
46 * contributors may be used to endorse or promote products derived
47 * from this software without specific prior written permission.
48 *
49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
50 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
51 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
52 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
53 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
55 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
59 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60 *****************************************************************************/
61 #include <linux/types.h>
62 #include <linux/slab.h>
63 #include <linux/export.h>
64 #include "iwl-drv.h"
65 #include "iwl-modparams.h"
66 #include "iwl-eeprom-parse.h"
67
68 /* EEPROM offset definitions */
69
70 /* indirect access definitions */
71 #define ADDRESS_MSK 0x0000FFFF
72 #define INDIRECT_TYPE_MSK 0x000F0000
73 #define INDIRECT_HOST 0x00010000
74 #define INDIRECT_GENERAL 0x00020000
75 #define INDIRECT_REGULATORY 0x00030000
76 #define INDIRECT_CALIBRATION 0x00040000
77 #define INDIRECT_PROCESS_ADJST 0x00050000
78 #define INDIRECT_OTHERS 0x00060000
79 #define INDIRECT_TXP_LIMIT 0x00070000
80 #define INDIRECT_TXP_LIMIT_SIZE 0x00080000
81 #define INDIRECT_ADDRESS 0x00100000
82
83 /* corresponding link offsets in EEPROM */
84 #define EEPROM_LINK_HOST (2*0x64)
85 #define EEPROM_LINK_GENERAL (2*0x65)
86 #define EEPROM_LINK_REGULATORY (2*0x66)
87 #define EEPROM_LINK_CALIBRATION (2*0x67)
88 #define EEPROM_LINK_PROCESS_ADJST (2*0x68)
89 #define EEPROM_LINK_OTHERS (2*0x69)
90 #define EEPROM_LINK_TXP_LIMIT (2*0x6a)
91 #define EEPROM_LINK_TXP_LIMIT_SIZE (2*0x6b)
92
93 /* General */
94 #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
95 #define EEPROM_SUBSYSTEM_ID (2*0x0A) /* 2 bytes */
96 #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
97 #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
98 #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
99 #define EEPROM_VERSION (2*0x44) /* 2 bytes */
100 #define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */
101 #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
102 #define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */
103 #define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */
104
105 /* calibration */
106 struct iwl_eeprom_calib_hdr {
107 u8 version;
108 u8 pa_type;
109 __le16 voltage;
110 } __packed;
111
112 #define EEPROM_CALIB_ALL (INDIRECT_ADDRESS | INDIRECT_CALIBRATION)
113 #define EEPROM_XTAL ((2*0x128) | EEPROM_CALIB_ALL)
114
115 /* temperature */
116 #define EEPROM_KELVIN_TEMPERATURE ((2*0x12A) | EEPROM_CALIB_ALL)
117 #define EEPROM_RAW_TEMPERATURE ((2*0x12B) | EEPROM_CALIB_ALL)
118
119 /* SKU Capabilities (actual values from EEPROM definition) */
120 enum eeprom_sku_bits {
121 EEPROM_SKU_CAP_BAND_24GHZ = BIT(4),
122 EEPROM_SKU_CAP_BAND_52GHZ = BIT(5),
123 EEPROM_SKU_CAP_11N_ENABLE = BIT(6),
124 EEPROM_SKU_CAP_AMT_ENABLE = BIT(7),
125 EEPROM_SKU_CAP_IPAN_ENABLE = BIT(8)
126 };
127
128 /* radio config bits (actual values from EEPROM definition) */
129 #define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
130 #define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
131 #define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
132 #define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
133 #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
134 #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
135
136
137 /*
138 * EEPROM bands
139 * These are the channel numbers from each band in the order
140 * that they are stored in the EEPROM band information. Note
141 * that EEPROM bands aren't the same as mac80211 bands, and
142 * there are even special "ht40 bands" in the EEPROM.
143 */
144 static const u8 iwl_eeprom_band_1[14] = { /* 2.4 GHz */
145 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
146 };
147
148 static const u8 iwl_eeprom_band_2[] = { /* 4915-5080MHz */
149 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
150 };
151
152 static const u8 iwl_eeprom_band_3[] = { /* 5170-5320MHz */
153 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
154 };
155
156 static const u8 iwl_eeprom_band_4[] = { /* 5500-5700MHz */
157 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
158 };
159
160 static const u8 iwl_eeprom_band_5[] = { /* 5725-5825MHz */
161 145, 149, 153, 157, 161, 165
162 };
163
164 static const u8 iwl_eeprom_band_6[] = { /* 2.4 ht40 channel */
165 1, 2, 3, 4, 5, 6, 7
166 };
167
168 static const u8 iwl_eeprom_band_7[] = { /* 5.2 ht40 channel */
169 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
170 };
171
172 #define IWL_NUM_CHANNELS (ARRAY_SIZE(iwl_eeprom_band_1) + \
173 ARRAY_SIZE(iwl_eeprom_band_2) + \
174 ARRAY_SIZE(iwl_eeprom_band_3) + \
175 ARRAY_SIZE(iwl_eeprom_band_4) + \
176 ARRAY_SIZE(iwl_eeprom_band_5))
177
178 /* rate data (static) */
179 static struct ieee80211_rate iwl_cfg80211_rates[] = {
180 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
181 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
182 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
183 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
184 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
185 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
186 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
187 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
188 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
189 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
190 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
191 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
192 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
193 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
194 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
195 };
196 #define RATES_24_OFFS 0
197 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
198 #define RATES_52_OFFS 4
199 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
200
201 /* EEPROM reading functions */
202
203 static u16 iwl_eeprom_query16(const u8 *eeprom, size_t eeprom_size, int offset)
204 {
205 if (WARN_ON(offset + sizeof(u16) > eeprom_size))
206 return 0;
207 return le16_to_cpup((__le16 *)(eeprom + offset));
208 }
209
210 static u32 eeprom_indirect_address(const u8 *eeprom, size_t eeprom_size,
211 u32 address)
212 {
213 u16 offset = 0;
214
215 if ((address & INDIRECT_ADDRESS) == 0)
216 return address;
217
218 switch (address & INDIRECT_TYPE_MSK) {
219 case INDIRECT_HOST:
220 offset = iwl_eeprom_query16(eeprom, eeprom_size,
221 EEPROM_LINK_HOST);
222 break;
223 case INDIRECT_GENERAL:
224 offset = iwl_eeprom_query16(eeprom, eeprom_size,
225 EEPROM_LINK_GENERAL);
226 break;
227 case INDIRECT_REGULATORY:
228 offset = iwl_eeprom_query16(eeprom, eeprom_size,
229 EEPROM_LINK_REGULATORY);
230 break;
231 case INDIRECT_TXP_LIMIT:
232 offset = iwl_eeprom_query16(eeprom, eeprom_size,
233 EEPROM_LINK_TXP_LIMIT);
234 break;
235 case INDIRECT_TXP_LIMIT_SIZE:
236 offset = iwl_eeprom_query16(eeprom, eeprom_size,
237 EEPROM_LINK_TXP_LIMIT_SIZE);
238 break;
239 case INDIRECT_CALIBRATION:
240 offset = iwl_eeprom_query16(eeprom, eeprom_size,
241 EEPROM_LINK_CALIBRATION);
242 break;
243 case INDIRECT_PROCESS_ADJST:
244 offset = iwl_eeprom_query16(eeprom, eeprom_size,
245 EEPROM_LINK_PROCESS_ADJST);
246 break;
247 case INDIRECT_OTHERS:
248 offset = iwl_eeprom_query16(eeprom, eeprom_size,
249 EEPROM_LINK_OTHERS);
250 break;
251 default:
252 WARN_ON(1);
253 break;
254 }
255
256 /* translate the offset from words to byte */
257 return (address & ADDRESS_MSK) + (offset << 1);
258 }
259
260 static const u8 *iwl_eeprom_query_addr(const u8 *eeprom, size_t eeprom_size,
261 u32 offset)
262 {
263 u32 address = eeprom_indirect_address(eeprom, eeprom_size, offset);
264
265 if (WARN_ON(address >= eeprom_size))
266 return NULL;
267
268 return &eeprom[address];
269 }
270
271 static int iwl_eeprom_read_calib(const u8 *eeprom, size_t eeprom_size,
272 struct iwl_nvm_data *data)
273 {
274 struct iwl_eeprom_calib_hdr *hdr;
275
276 hdr = (void *)iwl_eeprom_query_addr(eeprom, eeprom_size,
277 EEPROM_CALIB_ALL);
278 if (!hdr)
279 return -ENODATA;
280 data->calib_version = hdr->version;
281 data->calib_voltage = hdr->voltage;
282
283 return 0;
284 }
285
286 /**
287 * enum iwl_eeprom_channel_flags - channel flags in EEPROM
288 * @EEPROM_CHANNEL_VALID: channel is usable for this SKU/geo
289 * @EEPROM_CHANNEL_IBSS: usable as an IBSS channel
290 * @EEPROM_CHANNEL_ACTIVE: active scanning allowed
291 * @EEPROM_CHANNEL_RADAR: radar detection required
292 * @EEPROM_CHANNEL_WIDE: 20 MHz channel okay (?)
293 * @EEPROM_CHANNEL_DFS: dynamic freq selection candidate
294 */
295 enum iwl_eeprom_channel_flags {
296 EEPROM_CHANNEL_VALID = BIT(0),
297 EEPROM_CHANNEL_IBSS = BIT(1),
298 EEPROM_CHANNEL_ACTIVE = BIT(3),
299 EEPROM_CHANNEL_RADAR = BIT(4),
300 EEPROM_CHANNEL_WIDE = BIT(5),
301 EEPROM_CHANNEL_DFS = BIT(7),
302 };
303
304 /**
305 * struct iwl_eeprom_channel - EEPROM channel data
306 * @flags: %EEPROM_CHANNEL_* flags
307 * @max_power_avg: max power (in dBm) on this channel, at most 31 dBm
308 */
309 struct iwl_eeprom_channel {
310 u8 flags;
311 s8 max_power_avg;
312 } __packed;
313
314
315 enum iwl_eeprom_enhanced_txpwr_flags {
316 IWL_EEPROM_ENH_TXP_FL_VALID = BIT(0),
317 IWL_EEPROM_ENH_TXP_FL_BAND_52G = BIT(1),
318 IWL_EEPROM_ENH_TXP_FL_OFDM = BIT(2),
319 IWL_EEPROM_ENH_TXP_FL_40MHZ = BIT(3),
320 IWL_EEPROM_ENH_TXP_FL_HT_AP = BIT(4),
321 IWL_EEPROM_ENH_TXP_FL_RES1 = BIT(5),
322 IWL_EEPROM_ENH_TXP_FL_RES2 = BIT(6),
323 IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE = BIT(7),
324 };
325
326 /**
327 * iwl_eeprom_enhanced_txpwr structure
328 * @flags: entry flags
329 * @channel: channel number
330 * @chain_a_max_pwr: chain a max power in 1/2 dBm
331 * @chain_b_max_pwr: chain b max power in 1/2 dBm
332 * @chain_c_max_pwr: chain c max power in 1/2 dBm
333 * @delta_20_in_40: 20-in-40 deltas (hi/lo)
334 * @mimo2_max_pwr: mimo2 max power in 1/2 dBm
335 * @mimo3_max_pwr: mimo3 max power in 1/2 dBm
336 *
337 * This structure presents the enhanced regulatory tx power limit layout
338 * in an EEPROM image.
339 */
340 struct iwl_eeprom_enhanced_txpwr {
341 u8 flags;
342 u8 channel;
343 s8 chain_a_max;
344 s8 chain_b_max;
345 s8 chain_c_max;
346 u8 delta_20_in_40;
347 s8 mimo2_max;
348 s8 mimo3_max;
349 } __packed;
350
351 static s8 iwl_get_max_txpwr_half_dbm(const struct iwl_nvm_data *data,
352 struct iwl_eeprom_enhanced_txpwr *txp)
353 {
354 s8 result = 0; /* (.5 dBm) */
355
356 /* Take the highest tx power from any valid chains */
357 if (data->valid_tx_ant & ANT_A && txp->chain_a_max > result)
358 result = txp->chain_a_max;
359
360 if (data->valid_tx_ant & ANT_B && txp->chain_b_max > result)
361 result = txp->chain_b_max;
362
363 if (data->valid_tx_ant & ANT_C && txp->chain_c_max > result)
364 result = txp->chain_c_max;
365
366 if ((data->valid_tx_ant == ANT_AB ||
367 data->valid_tx_ant == ANT_BC ||
368 data->valid_tx_ant == ANT_AC) && txp->mimo2_max > result)
369 result = txp->mimo2_max;
370
371 if (data->valid_tx_ant == ANT_ABC && txp->mimo3_max > result)
372 result = txp->mimo3_max;
373
374 return result;
375 }
376
377 #define EEPROM_TXP_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT)
378 #define EEPROM_TXP_ENTRY_LEN sizeof(struct iwl_eeprom_enhanced_txpwr)
379 #define EEPROM_TXP_SZ_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT_SIZE)
380
381 #define TXP_CHECK_AND_PRINT(x) \
382 ((txp->flags & IWL_EEPROM_ENH_TXP_FL_##x) ? # x " " : "")
383
384 static void
385 iwl_eeprom_enh_txp_read_element(struct iwl_nvm_data *data,
386 struct iwl_eeprom_enhanced_txpwr *txp,
387 int n_channels, s8 max_txpower_avg)
388 {
389 int ch_idx;
390 enum nl80211_band band;
391
392 band = txp->flags & IWL_EEPROM_ENH_TXP_FL_BAND_52G ?
393 NL80211_BAND_5GHZ : NL80211_BAND_2GHZ;
394
395 for (ch_idx = 0; ch_idx < n_channels; ch_idx++) {
396 struct ieee80211_channel *chan = &data->channels[ch_idx];
397
398 /* update matching channel or from common data only */
399 if (txp->channel != 0 && chan->hw_value != txp->channel)
400 continue;
401
402 /* update matching band only */
403 if (band != chan->band)
404 continue;
405
406 if (chan->max_power < max_txpower_avg &&
407 !(txp->flags & IWL_EEPROM_ENH_TXP_FL_40MHZ))
408 chan->max_power = max_txpower_avg;
409 }
410 }
411
412 static void iwl_eeprom_enhanced_txpower(struct device *dev,
413 struct iwl_nvm_data *data,
414 const u8 *eeprom, size_t eeprom_size,
415 int n_channels)
416 {
417 struct iwl_eeprom_enhanced_txpwr *txp_array, *txp;
418 int idx, entries;
419 __le16 *txp_len;
420 s8 max_txp_avg_halfdbm;
421
422 BUILD_BUG_ON(sizeof(struct iwl_eeprom_enhanced_txpwr) != 8);
423
424 /* the length is in 16-bit words, but we want entries */
425 txp_len = (__le16 *)iwl_eeprom_query_addr(eeprom, eeprom_size,
426 EEPROM_TXP_SZ_OFFS);
427 entries = le16_to_cpup(txp_len) * 2 / EEPROM_TXP_ENTRY_LEN;
428
429 txp_array = (void *)iwl_eeprom_query_addr(eeprom, eeprom_size,
430 EEPROM_TXP_OFFS);
431
432 for (idx = 0; idx < entries; idx++) {
433 txp = &txp_array[idx];
434 /* skip invalid entries */
435 if (!(txp->flags & IWL_EEPROM_ENH_TXP_FL_VALID))
436 continue;
437
438 IWL_DEBUG_EEPROM(dev, "%s %d:\t %s%s%s%s%s%s%s%s (0x%02x)\n",
439 (txp->channel && (txp->flags &
440 IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE)) ?
441 "Common " : (txp->channel) ?
442 "Channel" : "Common",
443 (txp->channel),
444 TXP_CHECK_AND_PRINT(VALID),
445 TXP_CHECK_AND_PRINT(BAND_52G),
446 TXP_CHECK_AND_PRINT(OFDM),
447 TXP_CHECK_AND_PRINT(40MHZ),
448 TXP_CHECK_AND_PRINT(HT_AP),
449 TXP_CHECK_AND_PRINT(RES1),
450 TXP_CHECK_AND_PRINT(RES2),
451 TXP_CHECK_AND_PRINT(COMMON_TYPE),
452 txp->flags);
453 IWL_DEBUG_EEPROM(dev,
454 "\t\t chain_A: %d chain_B: %d chain_C: %d\n",
455 txp->chain_a_max, txp->chain_b_max,
456 txp->chain_c_max);
457 IWL_DEBUG_EEPROM(dev,
458 "\t\t MIMO2: %d MIMO3: %d High 20_on_40: 0x%02x Low 20_on_40: 0x%02x\n",
459 txp->mimo2_max, txp->mimo3_max,
460 ((txp->delta_20_in_40 & 0xf0) >> 4),
461 (txp->delta_20_in_40 & 0x0f));
462
463 max_txp_avg_halfdbm = iwl_get_max_txpwr_half_dbm(data, txp);
464
465 iwl_eeprom_enh_txp_read_element(data, txp, n_channels,
466 DIV_ROUND_UP(max_txp_avg_halfdbm, 2));
467
468 if (max_txp_avg_halfdbm > data->max_tx_pwr_half_dbm)
469 data->max_tx_pwr_half_dbm = max_txp_avg_halfdbm;
470 }
471 }
472
473 static void iwl_init_band_reference(const struct iwl_cfg *cfg,
474 const u8 *eeprom, size_t eeprom_size,
475 int eeprom_band, int *eeprom_ch_count,
476 const struct iwl_eeprom_channel **ch_info,
477 const u8 **eeprom_ch_array)
478 {
479 u32 offset = cfg->eeprom_params->regulatory_bands[eeprom_band - 1];
480
481 offset |= INDIRECT_ADDRESS | INDIRECT_REGULATORY;
482
483 *ch_info = (void *)iwl_eeprom_query_addr(eeprom, eeprom_size, offset);
484
485 switch (eeprom_band) {
486 case 1: /* 2.4GHz band */
487 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1);
488 *eeprom_ch_array = iwl_eeprom_band_1;
489 break;
490 case 2: /* 4.9GHz band */
491 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2);
492 *eeprom_ch_array = iwl_eeprom_band_2;
493 break;
494 case 3: /* 5.2GHz band */
495 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3);
496 *eeprom_ch_array = iwl_eeprom_band_3;
497 break;
498 case 4: /* 5.5GHz band */
499 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4);
500 *eeprom_ch_array = iwl_eeprom_band_4;
501 break;
502 case 5: /* 5.7GHz band */
503 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5);
504 *eeprom_ch_array = iwl_eeprom_band_5;
505 break;
506 case 6: /* 2.4GHz ht40 channels */
507 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6);
508 *eeprom_ch_array = iwl_eeprom_band_6;
509 break;
510 case 7: /* 5 GHz ht40 channels */
511 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7);
512 *eeprom_ch_array = iwl_eeprom_band_7;
513 break;
514 default:
515 *eeprom_ch_count = 0;
516 *eeprom_ch_array = NULL;
517 WARN_ON(1);
518 }
519 }
520
521 #define CHECK_AND_PRINT(x) \
522 ((eeprom_ch->flags & EEPROM_CHANNEL_##x) ? # x " " : "")
523
524 static void iwl_mod_ht40_chan_info(struct device *dev,
525 struct iwl_nvm_data *data, int n_channels,
526 enum nl80211_band band, u16 channel,
527 const struct iwl_eeprom_channel *eeprom_ch,
528 u8 clear_ht40_extension_channel)
529 {
530 struct ieee80211_channel *chan = NULL;
531 int i;
532
533 for (i = 0; i < n_channels; i++) {
534 if (data->channels[i].band != band)
535 continue;
536 if (data->channels[i].hw_value != channel)
537 continue;
538 chan = &data->channels[i];
539 break;
540 }
541
542 if (!chan)
543 return;
544
545 IWL_DEBUG_EEPROM(dev,
546 "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n",
547 channel,
548 band == NL80211_BAND_5GHZ ? "5.2" : "2.4",
549 CHECK_AND_PRINT(IBSS),
550 CHECK_AND_PRINT(ACTIVE),
551 CHECK_AND_PRINT(RADAR),
552 CHECK_AND_PRINT(WIDE),
553 CHECK_AND_PRINT(DFS),
554 eeprom_ch->flags,
555 eeprom_ch->max_power_avg,
556 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) &&
557 !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? ""
558 : "not ");
559
560 if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
561 chan->flags &= ~clear_ht40_extension_channel;
562 }
563
564 #define CHECK_AND_PRINT_I(x) \
565 ((eeprom_ch_info[ch_idx].flags & EEPROM_CHANNEL_##x) ? # x " " : "")
566
567 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
568 struct iwl_nvm_data *data,
569 const u8 *eeprom, size_t eeprom_size)
570 {
571 int band, ch_idx;
572 const struct iwl_eeprom_channel *eeprom_ch_info;
573 const u8 *eeprom_ch_array;
574 int eeprom_ch_count;
575 int n_channels = 0;
576
577 /*
578 * Loop through the 5 EEPROM bands and add them to the parse list
579 */
580 for (band = 1; band <= 5; band++) {
581 struct ieee80211_channel *channel;
582
583 iwl_init_band_reference(cfg, eeprom, eeprom_size, band,
584 &eeprom_ch_count, &eeprom_ch_info,
585 &eeprom_ch_array);
586
587 /* Loop through each band adding each of the channels */
588 for (ch_idx = 0; ch_idx < eeprom_ch_count; ch_idx++) {
589 const struct iwl_eeprom_channel *eeprom_ch;
590
591 eeprom_ch = &eeprom_ch_info[ch_idx];
592
593 if (!(eeprom_ch->flags & EEPROM_CHANNEL_VALID)) {
594 IWL_DEBUG_EEPROM(dev,
595 "Ch. %d Flags %x [%sGHz] - No traffic\n",
596 eeprom_ch_array[ch_idx],
597 eeprom_ch_info[ch_idx].flags,
598 (band != 1) ? "5.2" : "2.4");
599 continue;
600 }
601
602 channel = &data->channels[n_channels];
603 n_channels++;
604
605 channel->hw_value = eeprom_ch_array[ch_idx];
606 channel->band = (band == 1) ? NL80211_BAND_2GHZ
607 : NL80211_BAND_5GHZ;
608 channel->center_freq =
609 ieee80211_channel_to_frequency(
610 channel->hw_value, channel->band);
611
612 /* set no-HT40, will enable as appropriate later */
613 channel->flags = IEEE80211_CHAN_NO_HT40;
614
615 if (!(eeprom_ch->flags & EEPROM_CHANNEL_IBSS))
616 channel->flags |= IEEE80211_CHAN_NO_IR;
617
618 if (!(eeprom_ch->flags & EEPROM_CHANNEL_ACTIVE))
619 channel->flags |= IEEE80211_CHAN_NO_IR;
620
621 if (eeprom_ch->flags & EEPROM_CHANNEL_RADAR)
622 channel->flags |= IEEE80211_CHAN_RADAR;
623
624 /* Initialize regulatory-based run-time data */
625 channel->max_power =
626 eeprom_ch_info[ch_idx].max_power_avg;
627 IWL_DEBUG_EEPROM(dev,
628 "Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n",
629 channel->hw_value,
630 (band != 1) ? "5.2" : "2.4",
631 CHECK_AND_PRINT_I(VALID),
632 CHECK_AND_PRINT_I(IBSS),
633 CHECK_AND_PRINT_I(ACTIVE),
634 CHECK_AND_PRINT_I(RADAR),
635 CHECK_AND_PRINT_I(WIDE),
636 CHECK_AND_PRINT_I(DFS),
637 eeprom_ch_info[ch_idx].flags,
638 eeprom_ch_info[ch_idx].max_power_avg,
639 ((eeprom_ch_info[ch_idx].flags &
640 EEPROM_CHANNEL_IBSS) &&
641 !(eeprom_ch_info[ch_idx].flags &
642 EEPROM_CHANNEL_RADAR))
643 ? "" : "not ");
644 }
645 }
646
647 if (cfg->eeprom_params->enhanced_txpower) {
648 /*
649 * for newer device (6000 series and up)
650 * EEPROM contain enhanced tx power information
651 * driver need to process addition information
652 * to determine the max channel tx power limits
653 */
654 iwl_eeprom_enhanced_txpower(dev, data, eeprom, eeprom_size,
655 n_channels);
656 } else {
657 /* All others use data from channel map */
658 int i;
659
660 data->max_tx_pwr_half_dbm = -128;
661
662 for (i = 0; i < n_channels; i++)
663 data->max_tx_pwr_half_dbm =
664 max_t(s8, data->max_tx_pwr_half_dbm,
665 data->channels[i].max_power * 2);
666 }
667
668 /* Check if we do have HT40 channels */
669 if (cfg->eeprom_params->regulatory_bands[5] ==
670 EEPROM_REGULATORY_BAND_NO_HT40 &&
671 cfg->eeprom_params->regulatory_bands[6] ==
672 EEPROM_REGULATORY_BAND_NO_HT40)
673 return n_channels;
674
675 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
676 for (band = 6; band <= 7; band++) {
677 enum nl80211_band ieeeband;
678
679 iwl_init_band_reference(cfg, eeprom, eeprom_size, band,
680 &eeprom_ch_count, &eeprom_ch_info,
681 &eeprom_ch_array);
682
683 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
684 ieeeband = (band == 6) ? NL80211_BAND_2GHZ
685 : NL80211_BAND_5GHZ;
686
687 /* Loop through each band adding each of the channels */
688 for (ch_idx = 0; ch_idx < eeprom_ch_count; ch_idx++) {
689 /* Set up driver's info for lower half */
690 iwl_mod_ht40_chan_info(dev, data, n_channels, ieeeband,
691 eeprom_ch_array[ch_idx],
692 &eeprom_ch_info[ch_idx],
693 IEEE80211_CHAN_NO_HT40PLUS);
694
695 /* Set up driver's info for upper half */
696 iwl_mod_ht40_chan_info(dev, data, n_channels, ieeeband,
697 eeprom_ch_array[ch_idx] + 4,
698 &eeprom_ch_info[ch_idx],
699 IEEE80211_CHAN_NO_HT40MINUS);
700 }
701 }
702
703 return n_channels;
704 }
705
706 int iwl_init_sband_channels(struct iwl_nvm_data *data,
707 struct ieee80211_supported_band *sband,
708 int n_channels, enum nl80211_band band)
709 {
710 struct ieee80211_channel *chan = &data->channels[0];
711 int n = 0, idx = 0;
712
713 while (idx < n_channels && chan->band != band)
714 chan = &data->channels[++idx];
715
716 sband->channels = &data->channels[idx];
717
718 while (idx < n_channels && chan->band == band) {
719 chan = &data->channels[++idx];
720 n++;
721 }
722
723 sband->n_channels = n;
724
725 return n;
726 }
727
728 #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
729 #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
730
731 void iwl_init_ht_hw_capab(struct iwl_trans *trans,
732 struct iwl_nvm_data *data,
733 struct ieee80211_sta_ht_cap *ht_info,
734 enum nl80211_band band,
735 u8 tx_chains, u8 rx_chains)
736 {
737 const struct iwl_cfg *cfg = trans->cfg;
738 int max_bit_rate = 0;
739
740 tx_chains = hweight8(tx_chains);
741 if (cfg->rx_with_siso_diversity)
742 rx_chains = 1;
743 else
744 rx_chains = hweight8(rx_chains);
745
746 if (!(data->sku_cap_11n_enable) ||
747 (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) ||
748 !cfg->ht_params) {
749 ht_info->ht_supported = false;
750 return;
751 }
752
753 if (data->sku_cap_mimo_disabled)
754 rx_chains = 1;
755
756 ht_info->ht_supported = true;
757 ht_info->cap = IEEE80211_HT_CAP_DSSSCCK40;
758
759 if (cfg->ht_params->stbc) {
760 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
761
762 if (tx_chains > 1)
763 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
764 }
765
766 if (cfg->ht_params->ldpc)
767 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
768
769 if ((trans->trans_cfg->mq_rx_supported &&
770 iwlwifi_mod_params.amsdu_size == IWL_AMSDU_DEF) ||
771 iwlwifi_mod_params.amsdu_size >= IWL_AMSDU_8K)
772 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
773
774 ht_info->ampdu_factor = cfg->max_ht_ampdu_exponent;
775 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_4;
776
777 ht_info->mcs.rx_mask[0] = 0xFF;
778 if (rx_chains >= 2)
779 ht_info->mcs.rx_mask[1] = 0xFF;
780 if (rx_chains >= 3)
781 ht_info->mcs.rx_mask[2] = 0xFF;
782
783 if (cfg->ht_params->ht_greenfield_support)
784 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
785 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
786
787 max_bit_rate = MAX_BIT_RATE_20_MHZ;
788
789 if (cfg->ht_params->ht40_bands & BIT(band)) {
790 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
791 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
792 max_bit_rate = MAX_BIT_RATE_40_MHZ;
793 }
794
795 /* Highest supported Rx data rate */
796 max_bit_rate *= rx_chains;
797 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
798 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
799
800 /* Tx MCS capabilities */
801 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
802 if (tx_chains != rx_chains) {
803 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
804 ht_info->mcs.tx_params |= ((tx_chains - 1) <<
805 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
806 }
807 }
808
809 static void iwl_init_sbands(struct iwl_trans *trans, const struct iwl_cfg *cfg,
810 struct iwl_nvm_data *data,
811 const u8 *eeprom, size_t eeprom_size)
812 {
813 struct device *dev = trans->dev;
814 int n_channels = iwl_init_channel_map(dev, cfg, data,
815 eeprom, eeprom_size);
816 int n_used = 0;
817 struct ieee80211_supported_band *sband;
818
819 sband = &data->bands[NL80211_BAND_2GHZ];
820 sband->band = NL80211_BAND_2GHZ;
821 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
822 sband->n_bitrates = N_RATES_24;
823 n_used += iwl_init_sband_channels(data, sband, n_channels,
824 NL80211_BAND_2GHZ);
825 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ,
826 data->valid_tx_ant, data->valid_rx_ant);
827
828 sband = &data->bands[NL80211_BAND_5GHZ];
829 sband->band = NL80211_BAND_5GHZ;
830 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
831 sband->n_bitrates = N_RATES_52;
832 n_used += iwl_init_sband_channels(data, sband, n_channels,
833 NL80211_BAND_5GHZ);
834 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ,
835 data->valid_tx_ant, data->valid_rx_ant);
836
837 if (n_channels != n_used)
838 IWL_ERR_DEV(dev, "EEPROM: used only %d of %d channels\n",
839 n_used, n_channels);
840 }
841
842 /* EEPROM data functions */
843
844 struct iwl_nvm_data *
845 iwl_parse_eeprom_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
846 const u8 *eeprom, size_t eeprom_size)
847 {
848 struct iwl_nvm_data *data;
849 struct device *dev = trans->dev;
850 const void *tmp;
851 u16 radio_cfg, sku;
852
853 if (WARN_ON(!cfg || !cfg->eeprom_params))
854 return NULL;
855
856 data = kzalloc(struct_size(data, channels, IWL_NUM_CHANNELS),
857 GFP_KERNEL);
858 if (!data)
859 return NULL;
860
861 /* get MAC address(es) */
862 tmp = iwl_eeprom_query_addr(eeprom, eeprom_size, EEPROM_MAC_ADDRESS);
863 if (!tmp)
864 goto err_free;
865 memcpy(data->hw_addr, tmp, ETH_ALEN);
866 data->n_hw_addrs = iwl_eeprom_query16(eeprom, eeprom_size,
867 EEPROM_NUM_MAC_ADDRESS);
868
869 if (iwl_eeprom_read_calib(eeprom, eeprom_size, data))
870 goto err_free;
871
872 tmp = iwl_eeprom_query_addr(eeprom, eeprom_size, EEPROM_XTAL);
873 if (!tmp)
874 goto err_free;
875 memcpy(data->xtal_calib, tmp, sizeof(data->xtal_calib));
876
877 tmp = iwl_eeprom_query_addr(eeprom, eeprom_size,
878 EEPROM_RAW_TEMPERATURE);
879 if (!tmp)
880 goto err_free;
881 data->raw_temperature = *(__le16 *)tmp;
882
883 tmp = iwl_eeprom_query_addr(eeprom, eeprom_size,
884 EEPROM_KELVIN_TEMPERATURE);
885 if (!tmp)
886 goto err_free;
887 data->kelvin_temperature = *(__le16 *)tmp;
888 data->kelvin_voltage = *((__le16 *)tmp + 1);
889
890 radio_cfg = iwl_eeprom_query16(eeprom, eeprom_size,
891 EEPROM_RADIO_CONFIG);
892 data->radio_cfg_dash = EEPROM_RF_CFG_DASH_MSK(radio_cfg);
893 data->radio_cfg_pnum = EEPROM_RF_CFG_PNUM_MSK(radio_cfg);
894 data->radio_cfg_step = EEPROM_RF_CFG_STEP_MSK(radio_cfg);
895 data->radio_cfg_type = EEPROM_RF_CFG_TYPE_MSK(radio_cfg);
896 data->valid_rx_ant = EEPROM_RF_CFG_RX_ANT_MSK(radio_cfg);
897 data->valid_tx_ant = EEPROM_RF_CFG_TX_ANT_MSK(radio_cfg);
898
899 sku = iwl_eeprom_query16(eeprom, eeprom_size,
900 EEPROM_SKU_CAP);
901 data->sku_cap_11n_enable = sku & EEPROM_SKU_CAP_11N_ENABLE;
902 data->sku_cap_amt_enable = sku & EEPROM_SKU_CAP_AMT_ENABLE;
903 data->sku_cap_band_24ghz_enable = sku & EEPROM_SKU_CAP_BAND_24GHZ;
904 data->sku_cap_band_52ghz_enable = sku & EEPROM_SKU_CAP_BAND_52GHZ;
905 data->sku_cap_ipan_enable = sku & EEPROM_SKU_CAP_IPAN_ENABLE;
906 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
907 data->sku_cap_11n_enable = false;
908
909 data->nvm_version = iwl_eeprom_query16(eeprom, eeprom_size,
910 EEPROM_VERSION);
911
912 /* check overrides (some devices have wrong EEPROM) */
913 if (cfg->valid_tx_ant)
914 data->valid_tx_ant = cfg->valid_tx_ant;
915 if (cfg->valid_rx_ant)
916 data->valid_rx_ant = cfg->valid_rx_ant;
917
918 if (!data->valid_tx_ant || !data->valid_rx_ant) {
919 IWL_ERR_DEV(dev, "invalid antennas (0x%x, 0x%x)\n",
920 data->valid_tx_ant, data->valid_rx_ant);
921 goto err_free;
922 }
923
924 iwl_init_sbands(trans, cfg, data, eeprom, eeprom_size);
925
926 return data;
927 err_free:
928 kfree(data);
929 return NULL;
930 }
931 IWL_EXPORT_SYMBOL(iwl_parse_eeprom_data);
Linux with added FPC-III support