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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / net / wireless / intel / iwlwifi / iwl-nvm-parse.c
blob9e9810d2b26221650b6f958a329d8bdc2f7706ed
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11 * Copyright(c) 2018 - 2019 Intel Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING.
24 *
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 * BSD LICENSE
30 *
31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
34 * Copyright(c) 2018 - 2019 Intel Corporation
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 *
41 * * Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * * Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in
45 * the documentation and/or other materials provided with the
46 * distribution.
47 * * Neither the name Intel Corporation nor the names of its
48 * contributors may be used to endorse or promote products derived
49 * from this software without specific prior written permission.
50 *
51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63 #include <linux/types.h>
64 #include <linux/slab.h>
65 #include <linux/export.h>
66 #include <linux/etherdevice.h>
67 #include <linux/pci.h>
68 #include <linux/firmware.h>
69
70 #include "iwl-drv.h"
71 #include "iwl-modparams.h"
72 #include "iwl-nvm-parse.h"
73 #include "iwl-prph.h"
74 #include "iwl-io.h"
75 #include "iwl-csr.h"
76 #include "fw/acpi.h"
77 #include "fw/api/nvm-reg.h"
78 #include "fw/api/commands.h"
79 #include "fw/api/cmdhdr.h"
80 #include "fw/img.h"
81
82 /* NVM offsets (in words) definitions */
83 enum nvm_offsets {
84 /* NVM HW-Section offset (in words) definitions */
85 SUBSYSTEM_ID = 0x0A,
86 HW_ADDR = 0x15,
87
88 /* NVM SW-Section offset (in words) definitions */
89 NVM_SW_SECTION = 0x1C0,
90 NVM_VERSION = 0,
91 RADIO_CFG = 1,
92 SKU = 2,
93 N_HW_ADDRS = 3,
94 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
95
96 /* NVM calibration section offset (in words) definitions */
97 NVM_CALIB_SECTION = 0x2B8,
98 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION,
99
100 /* NVM REGULATORY -Section offset (in words) definitions */
101 NVM_CHANNELS_SDP = 0,
102 };
103
104 enum ext_nvm_offsets {
105 /* NVM HW-Section offset (in words) definitions */
106 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1,
107
108 /* NVM SW-Section offset (in words) definitions */
109 NVM_VERSION_EXT_NVM = 0,
110 RADIO_CFG_FAMILY_EXT_NVM = 0,
111 SKU_FAMILY_8000 = 2,
112 N_HW_ADDRS_FAMILY_8000 = 3,
113
114 /* NVM REGULATORY -Section offset (in words) definitions */
115 NVM_CHANNELS_EXTENDED = 0,
116 NVM_LAR_OFFSET_OLD = 0x4C7,
117 NVM_LAR_OFFSET = 0x507,
118 NVM_LAR_ENABLED = 0x7,
119 };
120
121 /* SKU Capabilities (actual values from NVM definition) */
122 enum nvm_sku_bits {
123 NVM_SKU_CAP_BAND_24GHZ = BIT(0),
124 NVM_SKU_CAP_BAND_52GHZ = BIT(1),
125 NVM_SKU_CAP_11N_ENABLE = BIT(2),
126 NVM_SKU_CAP_11AC_ENABLE = BIT(3),
127 NVM_SKU_CAP_MIMO_DISABLE = BIT(5),
128 };
129
130 /*
131 * These are the channel numbers in the order that they are stored in the NVM
132 */
133 static const u16 iwl_nvm_channels[] = {
134 /* 2.4 GHz */
135 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
136 /* 5 GHz */
137 36, 40, 44 , 48, 52, 56, 60, 64,
138 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
139 149, 153, 157, 161, 165
140 };
141
142 static const u16 iwl_ext_nvm_channels[] = {
143 /* 2.4 GHz */
144 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
145 /* 5 GHz */
146 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
147 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
148 149, 153, 157, 161, 165, 169, 173, 177, 181
149 };
150
151 static const u16 iwl_uhb_nvm_channels[] = {
152 /* 2.4 GHz */
153 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
154 /* 5 GHz */
155 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
156 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
157 149, 153, 157, 161, 165, 169, 173, 177, 181,
158 /* 6-7 GHz */
159 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69,
160 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129,
161 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185,
162 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233
163 };
164
165 #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
166 #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels)
167 #define IWL_NVM_NUM_CHANNELS_UHB ARRAY_SIZE(iwl_uhb_nvm_channels)
168 #define NUM_2GHZ_CHANNELS 14
169 #define FIRST_2GHZ_HT_MINUS 5
170 #define LAST_2GHZ_HT_PLUS 9
171 #define N_HW_ADDR_MASK 0xF
172
173 /* rate data (static) */
174 static struct ieee80211_rate iwl_cfg80211_rates[] = {
175 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
176 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
177 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
178 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
179 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
180 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
181 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
182 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
183 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
184 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
185 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
186 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
187 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
188 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
189 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
190 };
191 #define RATES_24_OFFS 0
192 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
193 #define RATES_52_OFFS 4
194 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
195
196 /**
197 * enum iwl_nvm_channel_flags - channel flags in NVM
198 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
199 * @NVM_CHANNEL_IBSS: usable as an IBSS channel
200 * @NVM_CHANNEL_ACTIVE: active scanning allowed
201 * @NVM_CHANNEL_RADAR: radar detection required
202 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
203 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
204 * on same channel on 2.4 or same UNII band on 5.2
205 * @NVM_CHANNEL_UNIFORM: uniform spreading required
206 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay
207 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay
208 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay
209 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay
210 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?)
211 */
212 enum iwl_nvm_channel_flags {
213 NVM_CHANNEL_VALID = BIT(0),
214 NVM_CHANNEL_IBSS = BIT(1),
215 NVM_CHANNEL_ACTIVE = BIT(3),
216 NVM_CHANNEL_RADAR = BIT(4),
217 NVM_CHANNEL_INDOOR_ONLY = BIT(5),
218 NVM_CHANNEL_GO_CONCURRENT = BIT(6),
219 NVM_CHANNEL_UNIFORM = BIT(7),
220 NVM_CHANNEL_20MHZ = BIT(8),
221 NVM_CHANNEL_40MHZ = BIT(9),
222 NVM_CHANNEL_80MHZ = BIT(10),
223 NVM_CHANNEL_160MHZ = BIT(11),
224 NVM_CHANNEL_DC_HIGH = BIT(12),
225 };
226
227 /**
228 * enum iwl_reg_capa_flags - global flags applied for the whole regulatory
229 * domain.
230 * @REG_CAPA_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
231 * 2.4Ghz band is allowed.
232 * @REG_CAPA_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
233 * 5Ghz band is allowed.
234 * @REG_CAPA_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
235 * for this regulatory domain (valid only in 5Ghz).
236 * @REG_CAPA_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
237 * for this regulatory domain (valid only in 5Ghz).
238 * @REG_CAPA_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
239 * @REG_CAPA_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
240 * @REG_CAPA_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden
241 * for this regulatory domain (valid only in 5Ghz).
242 * @REG_CAPA_DC_HIGH_ENABLED: DC HIGH allowed.
243 */
244 enum iwl_reg_capa_flags {
245 REG_CAPA_BF_CCD_LOW_BAND = BIT(0),
246 REG_CAPA_BF_CCD_HIGH_BAND = BIT(1),
247 REG_CAPA_160MHZ_ALLOWED = BIT(2),
248 REG_CAPA_80MHZ_ALLOWED = BIT(3),
249 REG_CAPA_MCS_8_ALLOWED = BIT(4),
250 REG_CAPA_MCS_9_ALLOWED = BIT(5),
251 REG_CAPA_40MHZ_FORBIDDEN = BIT(7),
252 REG_CAPA_DC_HIGH_ENABLED = BIT(9),
253 };
254
255 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level,
256 int chan, u32 flags)
257 {
258 #define CHECK_AND_PRINT_I(x) \
259 ((flags & NVM_CHANNEL_##x) ? " " #x : "")
260
261 if (!(flags & NVM_CHANNEL_VALID)) {
262 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n",
263 chan, flags);
264 return;
265 }
266
267 /* Note: already can print up to 101 characters, 110 is the limit! */
268 IWL_DEBUG_DEV(dev, level,
269 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n",
270 chan, flags,
271 CHECK_AND_PRINT_I(VALID),
272 CHECK_AND_PRINT_I(IBSS),
273 CHECK_AND_PRINT_I(ACTIVE),
274 CHECK_AND_PRINT_I(RADAR),
275 CHECK_AND_PRINT_I(INDOOR_ONLY),
276 CHECK_AND_PRINT_I(GO_CONCURRENT),
277 CHECK_AND_PRINT_I(UNIFORM),
278 CHECK_AND_PRINT_I(20MHZ),
279 CHECK_AND_PRINT_I(40MHZ),
280 CHECK_AND_PRINT_I(80MHZ),
281 CHECK_AND_PRINT_I(160MHZ),
282 CHECK_AND_PRINT_I(DC_HIGH));
283 #undef CHECK_AND_PRINT_I
284 }
285
286 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band,
287 u32 nvm_flags, const struct iwl_cfg *cfg)
288 {
289 u32 flags = IEEE80211_CHAN_NO_HT40;
290
291 if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) {
292 if (ch_num <= LAST_2GHZ_HT_PLUS)
293 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
294 if (ch_num >= FIRST_2GHZ_HT_MINUS)
295 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
296 } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
297 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
298 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
299 else
300 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
301 }
302 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
303 flags |= IEEE80211_CHAN_NO_80MHZ;
304 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
305 flags |= IEEE80211_CHAN_NO_160MHZ;
306
307 if (!(nvm_flags & NVM_CHANNEL_IBSS))
308 flags |= IEEE80211_CHAN_NO_IR;
309
310 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
311 flags |= IEEE80211_CHAN_NO_IR;
312
313 if (nvm_flags & NVM_CHANNEL_RADAR)
314 flags |= IEEE80211_CHAN_RADAR;
315
316 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
317 flags |= IEEE80211_CHAN_INDOOR_ONLY;
318
319 /* Set the GO concurrent flag only in case that NO_IR is set.
320 * Otherwise it is meaningless
321 */
322 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
323 (flags & IEEE80211_CHAN_NO_IR))
324 flags |= IEEE80211_CHAN_IR_CONCURRENT;
325
326 return flags;
327 }
328
329 static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx)
330 {
331 if (ch_idx >= NUM_2GHZ_CHANNELS)
332 return NL80211_BAND_5GHZ;
333 return NL80211_BAND_2GHZ;
334 }
335
336 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
337 struct iwl_nvm_data *data,
338 const void * const nvm_ch_flags,
339 u32 sbands_flags, bool v4)
340 {
341 int ch_idx;
342 int n_channels = 0;
343 struct ieee80211_channel *channel;
344 u32 ch_flags;
345 int num_of_ch;
346 const u16 *nvm_chan;
347
348 if (cfg->uhb_supported) {
349 num_of_ch = IWL_NVM_NUM_CHANNELS_UHB;
350 nvm_chan = iwl_uhb_nvm_channels;
351 } else if (cfg->nvm_type == IWL_NVM_EXT) {
352 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT;
353 nvm_chan = iwl_ext_nvm_channels;
354 } else {
355 num_of_ch = IWL_NVM_NUM_CHANNELS;
356 nvm_chan = iwl_nvm_channels;
357 }
358
359 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
360 enum nl80211_band band =
361 iwl_nl80211_band_from_channel_idx(ch_idx);
362
363 if (v4)
364 ch_flags =
365 __le32_to_cpup((__le32 *)nvm_ch_flags + ch_idx);
366 else
367 ch_flags =
368 __le16_to_cpup((__le16 *)nvm_ch_flags + ch_idx);
369
370 if (band == NL80211_BAND_5GHZ &&
371 !data->sku_cap_band_52ghz_enable)
372 continue;
373
374 /* workaround to disable wide channels in 5GHz */
375 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) &&
376 band == NL80211_BAND_5GHZ) {
377 ch_flags &= ~(NVM_CHANNEL_40MHZ |
378 NVM_CHANNEL_80MHZ |
379 NVM_CHANNEL_160MHZ);
380 }
381
382 if (ch_flags & NVM_CHANNEL_160MHZ)
383 data->vht160_supported = true;
384
385 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) &&
386 !(ch_flags & NVM_CHANNEL_VALID)) {
387 /*
388 * Channels might become valid later if lar is
389 * supported, hence we still want to add them to
390 * the list of supported channels to cfg80211.
391 */
392 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
393 nvm_chan[ch_idx], ch_flags);
394 continue;
395 }
396
397 channel = &data->channels[n_channels];
398 n_channels++;
399
400 channel->hw_value = nvm_chan[ch_idx];
401 channel->band = band;
402 channel->center_freq =
403 ieee80211_channel_to_frequency(
404 channel->hw_value, channel->band);
405
406 /* Initialize regulatory-based run-time data */
407
408 /*
409 * Default value - highest tx power value. max_power
410 * is not used in mvm, and is used for backwards compatibility
411 */
412 channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
413
414 /* don't put limitations in case we're using LAR */
415 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR))
416 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
417 ch_idx, band,
418 ch_flags, cfg);
419 else
420 channel->flags = 0;
421
422 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
423 channel->hw_value, ch_flags);
424 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n",
425 channel->hw_value, channel->max_power);
426 }
427
428 return n_channels;
429 }
430
431 static void iwl_init_vht_hw_capab(struct iwl_trans *trans,
432 struct iwl_nvm_data *data,
433 struct ieee80211_sta_vht_cap *vht_cap,
434 u8 tx_chains, u8 rx_chains)
435 {
436 const struct iwl_cfg *cfg = trans->cfg;
437 int num_rx_ants = num_of_ant(rx_chains);
438 int num_tx_ants = num_of_ant(tx_chains);
439 unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?:
440 IEEE80211_VHT_MAX_AMPDU_1024K);
441
442 vht_cap->vht_supported = true;
443
444 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
445 IEEE80211_VHT_CAP_RXSTBC_1 |
446 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
447 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
448 max_ampdu_exponent <<
449 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
450
451 if (data->vht160_supported)
452 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
453 IEEE80211_VHT_CAP_SHORT_GI_160;
454
455 if (cfg->vht_mu_mimo_supported)
456 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
457
458 if (cfg->ht_params->ldpc)
459 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
460
461 if (data->sku_cap_mimo_disabled) {
462 num_rx_ants = 1;
463 num_tx_ants = 1;
464 }
465
466 if (num_tx_ants > 1)
467 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
468 else
469 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
470
471 switch (iwlwifi_mod_params.amsdu_size) {
472 case IWL_AMSDU_DEF:
473 if (trans->trans_cfg->mq_rx_supported)
474 vht_cap->cap |=
475 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
476 else
477 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
478 break;
479 case IWL_AMSDU_2K:
480 if (trans->trans_cfg->mq_rx_supported)
481 vht_cap->cap |=
482 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
483 else
484 WARN(1, "RB size of 2K is not supported by this device\n");
485 break;
486 case IWL_AMSDU_4K:
487 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
488 break;
489 case IWL_AMSDU_8K:
490 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
491 break;
492 case IWL_AMSDU_12K:
493 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
494 break;
495 default:
496 break;
497 }
498
499 vht_cap->vht_mcs.rx_mcs_map =
500 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
501 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
502 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
503 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
504 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
505 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
506 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
507 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
508
509 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
510 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
511 /* this works because NOT_SUPPORTED == 3 */
512 vht_cap->vht_mcs.rx_mcs_map |=
513 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
514 }
515
516 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
517
518 vht_cap->vht_mcs.tx_highest |=
519 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
520 }
521
522 static struct ieee80211_sband_iftype_data iwl_he_capa[] = {
523 {
524 .types_mask = BIT(NL80211_IFTYPE_STATION),
525 .he_cap = {
526 .has_he = true,
527 .he_cap_elem = {
528 .mac_cap_info[0] =
529 IEEE80211_HE_MAC_CAP0_HTC_HE |
530 IEEE80211_HE_MAC_CAP0_TWT_REQ,
531 .mac_cap_info[1] =
532 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
533 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
534 .mac_cap_info[2] =
535 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP |
536 IEEE80211_HE_MAC_CAP2_ACK_EN,
537 .mac_cap_info[3] =
538 IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
539 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2,
540 .mac_cap_info[4] =
541 IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU |
542 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39,
543 .mac_cap_info[5] =
544 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 |
545 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 |
546 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU |
547 IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS |
548 IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX,
549 .phy_cap_info[0] =
550 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
551 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
552 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G,
553 .phy_cap_info[1] =
554 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK |
555 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
556 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
557 .phy_cap_info[2] =
558 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
559 .phy_cap_info[3] =
560 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM |
561 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
562 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM |
563 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
564 .phy_cap_info[4] =
565 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
566 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
567 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
568 .phy_cap_info[5] =
569 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
570 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2,
571 .phy_cap_info[6] =
572 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
573 .phy_cap_info[7] =
574 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_AR |
575 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
576 IEEE80211_HE_PHY_CAP7_MAX_NC_1,
577 .phy_cap_info[8] =
578 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
579 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
580 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
581 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
582 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_2x996,
583 .phy_cap_info[9] =
584 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK |
585 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
586 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
587 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED,
588 },
589 /*
590 * Set default Tx/Rx HE MCS NSS Support field.
591 * Indicate support for up to 2 spatial streams and all
592 * MCS, without any special cases
593 */
594 .he_mcs_nss_supp = {
595 .rx_mcs_80 = cpu_to_le16(0xfffa),
596 .tx_mcs_80 = cpu_to_le16(0xfffa),
597 .rx_mcs_160 = cpu_to_le16(0xfffa),
598 .tx_mcs_160 = cpu_to_le16(0xfffa),
599 .rx_mcs_80p80 = cpu_to_le16(0xffff),
600 .tx_mcs_80p80 = cpu_to_le16(0xffff),
601 },
602 /*
603 * Set default PPE thresholds, with PPET16 set to 0,
604 * PPET8 set to 7
605 */
606 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
607 },
608 },
609 {
610 .types_mask = BIT(NL80211_IFTYPE_AP),
611 .he_cap = {
612 .has_he = true,
613 .he_cap_elem = {
614 .mac_cap_info[0] =
615 IEEE80211_HE_MAC_CAP0_HTC_HE,
616 .mac_cap_info[1] =
617 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
618 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
619 .mac_cap_info[2] =
620 IEEE80211_HE_MAC_CAP2_BSR |
621 IEEE80211_HE_MAC_CAP2_ACK_EN,
622 .mac_cap_info[3] =
623 IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
624 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2,
625 .mac_cap_info[4] =
626 IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU,
627 .mac_cap_info[5] =
628 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU,
629 .phy_cap_info[0] =
630 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
631 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
632 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G,
633 .phy_cap_info[1] =
634 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
635 .phy_cap_info[2] =
636 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
637 .phy_cap_info[3] =
638 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM |
639 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
640 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM |
641 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
642 .phy_cap_info[4] =
643 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
644 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
645 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
646 .phy_cap_info[5] =
647 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
648 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2,
649 .phy_cap_info[6] =
650 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
651 .phy_cap_info[7] =
652 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
653 IEEE80211_HE_PHY_CAP7_MAX_NC_1,
654 .phy_cap_info[8] =
655 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
656 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
657 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
658 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
659 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_2x996,
660 .phy_cap_info[9] =
661 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
662 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
663 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED,
664 },
665 /*
666 * Set default Tx/Rx HE MCS NSS Support field.
667 * Indicate support for up to 2 spatial streams and all
668 * MCS, without any special cases
669 */
670 .he_mcs_nss_supp = {
671 .rx_mcs_80 = cpu_to_le16(0xfffa),
672 .tx_mcs_80 = cpu_to_le16(0xfffa),
673 .rx_mcs_160 = cpu_to_le16(0xfffa),
674 .tx_mcs_160 = cpu_to_le16(0xfffa),
675 .rx_mcs_80p80 = cpu_to_le16(0xffff),
676 .tx_mcs_80p80 = cpu_to_le16(0xffff),
677 },
678 /*
679 * Set default PPE thresholds, with PPET16 set to 0,
680 * PPET8 set to 7
681 */
682 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
683 },
684 },
685 };
686
687 static void iwl_init_he_hw_capab(struct iwl_trans *trans,
688 struct iwl_nvm_data *data,
689 struct ieee80211_supported_band *sband,
690 u8 tx_chains, u8 rx_chains)
691 {
692 sband->iftype_data = iwl_he_capa;
693 sband->n_iftype_data = ARRAY_SIZE(iwl_he_capa);
694
695 /* If not 2x2, we need to indicate 1x1 in the Midamble RX Max NSTS */
696 if ((tx_chains & rx_chains) != ANT_AB) {
697 int i;
698
699 for (i = 0; i < sband->n_iftype_data; i++) {
700 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[1] &=
701 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS;
702 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[2] &=
703 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS;
704 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[7] &=
705 ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
706 }
707 }
708 }
709
710 static void iwl_init_sbands(struct iwl_trans *trans,
711 struct iwl_nvm_data *data,
712 const void *nvm_ch_flags, u8 tx_chains,
713 u8 rx_chains, u32 sbands_flags, bool v4)
714 {
715 struct device *dev = trans->dev;
716 const struct iwl_cfg *cfg = trans->cfg;
717 int n_channels;
718 int n_used = 0;
719 struct ieee80211_supported_band *sband;
720
721 n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags,
722 sbands_flags, v4);
723 sband = &data->bands[NL80211_BAND_2GHZ];
724 sband->band = NL80211_BAND_2GHZ;
725 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
726 sband->n_bitrates = N_RATES_24;
727 n_used += iwl_init_sband_channels(data, sband, n_channels,
728 NL80211_BAND_2GHZ);
729 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ,
730 tx_chains, rx_chains);
731
732 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
733 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains);
734
735 sband = &data->bands[NL80211_BAND_5GHZ];
736 sband->band = NL80211_BAND_5GHZ;
737 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
738 sband->n_bitrates = N_RATES_52;
739 n_used += iwl_init_sband_channels(data, sband, n_channels,
740 NL80211_BAND_5GHZ);
741 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ,
742 tx_chains, rx_chains);
743 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
744 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap,
745 tx_chains, rx_chains);
746
747 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
748 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains);
749
750 if (n_channels != n_used)
751 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
752 n_used, n_channels);
753 }
754
755 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
756 const __le16 *phy_sku)
757 {
758 if (cfg->nvm_type != IWL_NVM_EXT)
759 return le16_to_cpup(nvm_sw + SKU);
760
761 return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000));
762 }
763
764 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
765 {
766 if (cfg->nvm_type != IWL_NVM_EXT)
767 return le16_to_cpup(nvm_sw + NVM_VERSION);
768 else
769 return le32_to_cpup((__le32 *)(nvm_sw +
770 NVM_VERSION_EXT_NVM));
771 }
772
773 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
774 const __le16 *phy_sku)
775 {
776 if (cfg->nvm_type != IWL_NVM_EXT)
777 return le16_to_cpup(nvm_sw + RADIO_CFG);
778
779 return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM));
780
781 }
782
783 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
784 {
785 int n_hw_addr;
786
787 if (cfg->nvm_type != IWL_NVM_EXT)
788 return le16_to_cpup(nvm_sw + N_HW_ADDRS);
789
790 n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000));
791
792 return n_hw_addr & N_HW_ADDR_MASK;
793 }
794
795 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
796 struct iwl_nvm_data *data,
797 u32 radio_cfg)
798 {
799 if (cfg->nvm_type != IWL_NVM_EXT) {
800 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
801 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
802 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
803 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
804 return;
805 }
806
807 /* set the radio configuration for family 8000 */
808 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg);
809 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg);
810 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg);
811 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg);
812 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg);
813 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg);
814 }
815
816 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
817 {
818 const u8 *hw_addr;
819
820 hw_addr = (const u8 *)&mac_addr0;
821 dest[0] = hw_addr[3];
822 dest[1] = hw_addr[2];
823 dest[2] = hw_addr[1];
824 dest[3] = hw_addr[0];
825
826 hw_addr = (const u8 *)&mac_addr1;
827 dest[4] = hw_addr[1];
828 dest[5] = hw_addr[0];
829 }
830
831 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
832 struct iwl_nvm_data *data)
833 {
834 __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_STRAP));
835 __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_STRAP));
836
837 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
838 /*
839 * If the OEM fused a valid address, use it instead of the one in the
840 * OTP
841 */
842 if (is_valid_ether_addr(data->hw_addr))
843 return;
844
845 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP));
846 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP));
847
848 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
849 }
850
851 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
852 const struct iwl_cfg *cfg,
853 struct iwl_nvm_data *data,
854 const __le16 *mac_override,
855 const __be16 *nvm_hw)
856 {
857 const u8 *hw_addr;
858
859 if (mac_override) {
860 static const u8 reserved_mac[] = {
861 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
862 };
863
864 hw_addr = (const u8 *)(mac_override +
865 MAC_ADDRESS_OVERRIDE_EXT_NVM);
866
867 /*
868 * Store the MAC address from MAO section.
869 * No byte swapping is required in MAO section
870 */
871 memcpy(data->hw_addr, hw_addr, ETH_ALEN);
872
873 /*
874 * Force the use of the OTP MAC address in case of reserved MAC
875 * address in the NVM, or if address is given but invalid.
876 */
877 if (is_valid_ether_addr(data->hw_addr) &&
878 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0)
879 return;
880
881 IWL_ERR(trans,
882 "mac address from nvm override section is not valid\n");
883 }
884
885 if (nvm_hw) {
886 /* read the mac address from WFMP registers */
887 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,
888 WFMP_MAC_ADDR_0));
889 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,
890 WFMP_MAC_ADDR_1));
891
892 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
893
894 return;
895 }
896
897 IWL_ERR(trans, "mac address is not found\n");
898 }
899
900 static int iwl_set_hw_address(struct iwl_trans *trans,
901 const struct iwl_cfg *cfg,
902 struct iwl_nvm_data *data, const __be16 *nvm_hw,
903 const __le16 *mac_override)
904 {
905 if (cfg->mac_addr_from_csr) {
906 iwl_set_hw_address_from_csr(trans, data);
907 } else if (cfg->nvm_type != IWL_NVM_EXT) {
908 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR);
909
910 /* The byte order is little endian 16 bit, meaning 214365 */
911 data->hw_addr[0] = hw_addr[1];
912 data->hw_addr[1] = hw_addr[0];
913 data->hw_addr[2] = hw_addr[3];
914 data->hw_addr[3] = hw_addr[2];
915 data->hw_addr[4] = hw_addr[5];
916 data->hw_addr[5] = hw_addr[4];
917 } else {
918 iwl_set_hw_address_family_8000(trans, cfg, data,
919 mac_override, nvm_hw);
920 }
921
922 if (!is_valid_ether_addr(data->hw_addr)) {
923 IWL_ERR(trans, "no valid mac address was found\n");
924 return -EINVAL;
925 }
926
927 IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr);
928
929 return 0;
930 }
931
932 static bool
933 iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg,
934 const __be16 *nvm_hw)
935 {
936 /*
937 * Workaround a bug in Indonesia SKUs where the regulatory in
938 * some 7000-family OTPs erroneously allow wide channels in
939 * 5GHz. To check for Indonesia, we take the SKU value from
940 * bits 1-4 in the subsystem ID and check if it is either 5 or
941 * 9. In those cases, we need to force-disable wide channels
942 * in 5GHz otherwise the FW will throw a sysassert when we try
943 * to use them.
944 */
945 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
946 /*
947 * Unlike the other sections in the NVM, the hw
948 * section uses big-endian.
949 */
950 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID);
951 u8 sku = (subsystem_id & 0x1e) >> 1;
952
953 if (sku == 5 || sku == 9) {
954 IWL_DEBUG_EEPROM(trans->dev,
955 "disabling wide channels in 5GHz (0x%0x %d)\n",
956 subsystem_id, sku);
957 return true;
958 }
959 }
960
961 return false;
962 }
963
964 struct iwl_nvm_data *
965 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
966 const struct iwl_fw *fw,
967 const __be16 *nvm_hw, const __le16 *nvm_sw,
968 const __le16 *nvm_calib, const __le16 *regulatory,
969 const __le16 *mac_override, const __le16 *phy_sku,
970 u8 tx_chains, u8 rx_chains)
971 {
972 struct iwl_nvm_data *data;
973 bool lar_enabled;
974 u32 sku, radio_cfg;
975 u32 sbands_flags = 0;
976 u16 lar_config;
977 const __le16 *ch_section;
978
979 if (cfg->uhb_supported)
980 data = kzalloc(struct_size(data, channels,
981 IWL_NVM_NUM_CHANNELS_UHB),
982 GFP_KERNEL);
983 else if (cfg->nvm_type != IWL_NVM_EXT)
984 data = kzalloc(struct_size(data, channels,
985 IWL_NVM_NUM_CHANNELS),
986 GFP_KERNEL);
987 else
988 data = kzalloc(struct_size(data, channels,
989 IWL_NVM_NUM_CHANNELS_EXT),
990 GFP_KERNEL);
991 if (!data)
992 return NULL;
993
994 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
995
996 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku);
997 iwl_set_radio_cfg(cfg, data, radio_cfg);
998 if (data->valid_tx_ant)
999 tx_chains &= data->valid_tx_ant;
1000 if (data->valid_rx_ant)
1001 rx_chains &= data->valid_rx_ant;
1002
1003 sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
1004 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
1005 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
1006 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
1007 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
1008 data->sku_cap_11n_enable = false;
1009 data->sku_cap_11ac_enable = data->sku_cap_11n_enable &&
1010 (sku & NVM_SKU_CAP_11AC_ENABLE);
1011 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE;
1012
1013 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
1014
1015 if (cfg->nvm_type != IWL_NVM_EXT) {
1016 /* Checking for required sections */
1017 if (!nvm_calib) {
1018 IWL_ERR(trans,
1019 "Can't parse empty Calib NVM sections\n");
1020 kfree(data);
1021 return NULL;
1022 }
1023
1024 ch_section = cfg->nvm_type == IWL_NVM_SDP ?
1025 &regulatory[NVM_CHANNELS_SDP] :
1026 &nvm_sw[NVM_CHANNELS];
1027
1028 /* in family 8000 Xtal calibration values moved to OTP */
1029 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
1030 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
1031 lar_enabled = true;
1032 } else {
1033 u16 lar_offset = data->nvm_version < 0xE39 ?
1034 NVM_LAR_OFFSET_OLD :
1035 NVM_LAR_OFFSET;
1036
1037 lar_config = le16_to_cpup(regulatory + lar_offset);
1038 data->lar_enabled = !!(lar_config &
1039 NVM_LAR_ENABLED);
1040 lar_enabled = data->lar_enabled;
1041 ch_section = &regulatory[NVM_CHANNELS_EXTENDED];
1042 }
1043
1044 /* If no valid mac address was found - bail out */
1045 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) {
1046 kfree(data);
1047 return NULL;
1048 }
1049
1050 if (lar_enabled &&
1051 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT))
1052 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1053
1054 if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw))
1055 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ;
1056
1057 iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains,
1058 sbands_flags, false);
1059 data->calib_version = 255;
1060
1061 return data;
1062 }
1063 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
1064
1065 static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan,
1066 int ch_idx, u16 nvm_flags,
1067 u16 cap_flags,
1068 const struct iwl_cfg *cfg)
1069 {
1070 u32 flags = NL80211_RRF_NO_HT40;
1071
1072 if (ch_idx < NUM_2GHZ_CHANNELS &&
1073 (nvm_flags & NVM_CHANNEL_40MHZ)) {
1074 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
1075 flags &= ~NL80211_RRF_NO_HT40PLUS;
1076 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
1077 flags &= ~NL80211_RRF_NO_HT40MINUS;
1078 } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
1079 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
1080 flags &= ~NL80211_RRF_NO_HT40PLUS;
1081 else
1082 flags &= ~NL80211_RRF_NO_HT40MINUS;
1083 }
1084
1085 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
1086 flags |= NL80211_RRF_NO_80MHZ;
1087 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
1088 flags |= NL80211_RRF_NO_160MHZ;
1089
1090 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
1091 flags |= NL80211_RRF_NO_IR;
1092
1093 if (nvm_flags & NVM_CHANNEL_RADAR)
1094 flags |= NL80211_RRF_DFS;
1095
1096 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
1097 flags |= NL80211_RRF_NO_OUTDOOR;
1098
1099 /* Set the GO concurrent flag only in case that NO_IR is set.
1100 * Otherwise it is meaningless
1101 */
1102 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
1103 (flags & NL80211_RRF_NO_IR))
1104 flags |= NL80211_RRF_GO_CONCURRENT;
1105
1106 /*
1107 * cap_flags is per regulatory domain so apply it for every channel
1108 */
1109 if (ch_idx >= NUM_2GHZ_CHANNELS) {
1110 if (cap_flags & REG_CAPA_40MHZ_FORBIDDEN)
1111 flags |= NL80211_RRF_NO_HT40;
1112
1113 if (!(cap_flags & REG_CAPA_80MHZ_ALLOWED))
1114 flags |= NL80211_RRF_NO_80MHZ;
1115
1116 if (!(cap_flags & REG_CAPA_160MHZ_ALLOWED))
1117 flags |= NL80211_RRF_NO_160MHZ;
1118 }
1119
1120 return flags;
1121 }
1122
1123 struct ieee80211_regdomain *
1124 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
1125 int num_of_ch, __le32 *channels, u16 fw_mcc,
1126 u16 geo_info, u16 cap)
1127 {
1128 int ch_idx;
1129 u16 ch_flags;
1130 u32 reg_rule_flags, prev_reg_rule_flags = 0;
1131 const u16 *nvm_chan;
1132 struct ieee80211_regdomain *regd, *copy_rd;
1133 struct ieee80211_reg_rule *rule;
1134 enum nl80211_band band;
1135 int center_freq, prev_center_freq = 0;
1136 int valid_rules = 0;
1137 bool new_rule;
1138 int max_num_ch;
1139
1140 if (cfg->uhb_supported) {
1141 max_num_ch = IWL_NVM_NUM_CHANNELS_UHB;
1142 nvm_chan = iwl_uhb_nvm_channels;
1143 } else if (cfg->nvm_type == IWL_NVM_EXT) {
1144 max_num_ch = IWL_NVM_NUM_CHANNELS_EXT;
1145 nvm_chan = iwl_ext_nvm_channels;
1146 } else {
1147 max_num_ch = IWL_NVM_NUM_CHANNELS;
1148 nvm_chan = iwl_nvm_channels;
1149 }
1150
1151 if (WARN_ON(num_of_ch > max_num_ch))
1152 num_of_ch = max_num_ch;
1153
1154 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
1155 return ERR_PTR(-EINVAL);
1156
1157 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
1158 num_of_ch);
1159
1160 /* build a regdomain rule for every valid channel */
1161 regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL);
1162 if (!regd)
1163 return ERR_PTR(-ENOMEM);
1164
1165 /* set alpha2 from FW. */
1166 regd->alpha2[0] = fw_mcc >> 8;
1167 regd->alpha2[1] = fw_mcc & 0xff;
1168
1169 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
1170 ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
1171 band = (ch_idx < NUM_2GHZ_CHANNELS) ?
1172 NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
1173 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
1174 band);
1175 new_rule = false;
1176
1177 if (!(ch_flags & NVM_CHANNEL_VALID)) {
1178 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1179 nvm_chan[ch_idx], ch_flags);
1180 continue;
1181 }
1182
1183 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
1184 ch_flags, cap,
1185 cfg);
1186
1187 /* we can't continue the same rule */
1188 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags ||
1189 center_freq - prev_center_freq > 20) {
1190 valid_rules++;
1191 new_rule = true;
1192 }
1193
1194 rule = &regd->reg_rules[valid_rules - 1];
1195
1196 if (new_rule)
1197 rule->freq_range.start_freq_khz =
1198 MHZ_TO_KHZ(center_freq - 10);
1199
1200 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
1201
1202 /* this doesn't matter - not used by FW */
1203 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1204 rule->power_rule.max_eirp =
1205 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1206
1207 rule->flags = reg_rule_flags;
1208
1209 /* rely on auto-calculation to merge BW of contiguous chans */
1210 rule->flags |= NL80211_RRF_AUTO_BW;
1211 rule->freq_range.max_bandwidth_khz = 0;
1212
1213 prev_center_freq = center_freq;
1214 prev_reg_rule_flags = reg_rule_flags;
1215
1216 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1217 nvm_chan[ch_idx], ch_flags);
1218
1219 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) ||
1220 band == NL80211_BAND_2GHZ)
1221 continue;
1222
1223 reg_query_regdb_wmm(regd->alpha2, center_freq, rule);
1224 }
1225
1226 regd->n_reg_rules = valid_rules;
1227
1228 /*
1229 * Narrow down regdom for unused regulatory rules to prevent hole
1230 * between reg rules to wmm rules.
1231 */
1232 copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules),
1233 GFP_KERNEL);
1234 if (!copy_rd)
1235 copy_rd = ERR_PTR(-ENOMEM);
1236
1237 kfree(regd);
1238 return copy_rd;
1239 }
1240 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
1241
1242 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58
1243 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc
1244 #define MAX_NVM_FILE_LEN 16384
1245
1246 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data,
1247 unsigned int len)
1248 {
1249 #define IWL_4165_DEVICE_ID 0x5501
1250 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5)
1251
1252 if (section == NVM_SECTION_TYPE_PHY_SKU &&
1253 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 &&
1254 (data[4] & NVM_SKU_CAP_MIMO_DISABLE))
1255 /* OTP 0x52 bug work around: it's a 1x1 device */
1256 data[3] = ANT_B | (ANT_B << 4);
1257 }
1258 IWL_EXPORT_SYMBOL(iwl_nvm_fixups);
1259
1260 /*
1261 * Reads external NVM from a file into mvm->nvm_sections
1262 *
1263 * HOW TO CREATE THE NVM FILE FORMAT:
1264 * ------------------------------
1265 * 1. create hex file, format:
1266 * 3800 -> header
1267 * 0000 -> header
1268 * 5a40 -> data
1269 *
1270 * rev - 6 bit (word1)
1271 * len - 10 bit (word1)
1272 * id - 4 bit (word2)
1273 * rsv - 12 bit (word2)
1274 *
1275 * 2. flip 8bits with 8 bits per line to get the right NVM file format
1276 *
1277 * 3. create binary file from the hex file
1278 *
1279 * 4. save as "iNVM_xxx.bin" under /lib/firmware
1280 */
1281 int iwl_read_external_nvm(struct iwl_trans *trans,
1282 const char *nvm_file_name,
1283 struct iwl_nvm_section *nvm_sections)
1284 {
1285 int ret, section_size;
1286 u16 section_id;
1287 const struct firmware *fw_entry;
1288 const struct {
1289 __le16 word1;
1290 __le16 word2;
1291 u8 data[];
1292 } *file_sec;
1293 const u8 *eof;
1294 u8 *temp;
1295 int max_section_size;
1296 const __le32 *dword_buff;
1297
1298 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF))
1299 #define NVM_WORD2_ID(x) (x >> 12)
1300 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8))
1301 #define EXT_NVM_WORD1_ID(x) ((x) >> 4)
1302 #define NVM_HEADER_0 (0x2A504C54)
1303 #define NVM_HEADER_1 (0x4E564D2A)
1304 #define NVM_HEADER_SIZE (4 * sizeof(u32))
1305
1306 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n");
1307
1308 /* Maximal size depends on NVM version */
1309 if (trans->cfg->nvm_type != IWL_NVM_EXT)
1310 max_section_size = IWL_MAX_NVM_SECTION_SIZE;
1311 else
1312 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE;
1313
1314 /*
1315 * Obtain NVM image via request_firmware. Since we already used
1316 * request_firmware_nowait() for the firmware binary load and only
1317 * get here after that we assume the NVM request can be satisfied
1318 * synchronously.
1319 */
1320 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev);
1321 if (ret) {
1322 IWL_ERR(trans, "ERROR: %s isn't available %d\n",
1323 nvm_file_name, ret);
1324 return ret;
1325 }
1326
1327 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n",
1328 nvm_file_name, fw_entry->size);
1329
1330 if (fw_entry->size > MAX_NVM_FILE_LEN) {
1331 IWL_ERR(trans, "NVM file too large\n");
1332 ret = -EINVAL;
1333 goto out;
1334 }
1335
1336 eof = fw_entry->data + fw_entry->size;
1337 dword_buff = (__le32 *)fw_entry->data;
1338
1339 /* some NVM file will contain a header.
1340 * The header is identified by 2 dwords header as follow:
1341 * dword[0] = 0x2A504C54
1342 * dword[1] = 0x4E564D2A
1343 *
1344 * This header must be skipped when providing the NVM data to the FW.
1345 */
1346 if (fw_entry->size > NVM_HEADER_SIZE &&
1347 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) &&
1348 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) {
1349 file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE);
1350 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2]));
1351 IWL_INFO(trans, "NVM Manufacturing date %08X\n",
1352 le32_to_cpu(dword_buff[3]));
1353
1354 /* nvm file validation, dword_buff[2] holds the file version */
1355 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
1356 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP &&
1357 le32_to_cpu(dword_buff[2]) < 0xE4A) {
1358 ret = -EFAULT;
1359 goto out;
1360 }
1361 } else {
1362 file_sec = (void *)fw_entry->data;
1363 }
1364
1365 while (true) {
1366 if (file_sec->data > eof) {
1367 IWL_ERR(trans,
1368 "ERROR - NVM file too short for section header\n");
1369 ret = -EINVAL;
1370 break;
1371 }
1372
1373 /* check for EOF marker */
1374 if (!file_sec->word1 && !file_sec->word2) {
1375 ret = 0;
1376 break;
1377 }
1378
1379 if (trans->cfg->nvm_type != IWL_NVM_EXT) {
1380 section_size =
1381 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1));
1382 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2));
1383 } else {
1384 section_size = 2 * EXT_NVM_WORD2_LEN(
1385 le16_to_cpu(file_sec->word2));
1386 section_id = EXT_NVM_WORD1_ID(
1387 le16_to_cpu(file_sec->word1));
1388 }
1389
1390 if (section_size > max_section_size) {
1391 IWL_ERR(trans, "ERROR - section too large (%d)\n",
1392 section_size);
1393 ret = -EINVAL;
1394 break;
1395 }
1396
1397 if (!section_size) {
1398 IWL_ERR(trans, "ERROR - section empty\n");
1399 ret = -EINVAL;
1400 break;
1401 }
1402
1403 if (file_sec->data + section_size > eof) {
1404 IWL_ERR(trans,
1405 "ERROR - NVM file too short for section (%d bytes)\n",
1406 section_size);
1407 ret = -EINVAL;
1408 break;
1409 }
1410
1411 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS,
1412 "Invalid NVM section ID %d\n", section_id)) {
1413 ret = -EINVAL;
1414 break;
1415 }
1416
1417 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL);
1418 if (!temp) {
1419 ret = -ENOMEM;
1420 break;
1421 }
1422
1423 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size);
1424
1425 kfree(nvm_sections[section_id].data);
1426 nvm_sections[section_id].data = temp;
1427 nvm_sections[section_id].length = section_size;
1428
1429 /* advance to the next section */
1430 file_sec = (void *)(file_sec->data + section_size);
1431 }
1432 out:
1433 release_firmware(fw_entry);
1434 return ret;
1435 }
1436 IWL_EXPORT_SYMBOL(iwl_read_external_nvm);
1437
1438 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans,
1439 const struct iwl_fw *fw)
1440 {
1441 struct iwl_nvm_get_info cmd = {};
1442 struct iwl_nvm_data *nvm;
1443 struct iwl_host_cmd hcmd = {
1444 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
1445 .data = { &cmd, },
1446 .len = { sizeof(cmd) },
1447 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO)
1448 };
1449 int ret;
1450 bool empty_otp;
1451 u32 mac_flags;
1452 u32 sbands_flags = 0;
1453 /*
1454 * All the values in iwl_nvm_get_info_rsp v4 are the same as
1455 * in v3, except for the channel profile part of the
1456 * regulatory. So we can just access the new struct, with the
1457 * exception of the latter.
1458 */
1459 struct iwl_nvm_get_info_rsp *rsp;
1460 struct iwl_nvm_get_info_rsp_v3 *rsp_v3;
1461 bool v4 = fw_has_api(&fw->ucode_capa,
1462 IWL_UCODE_TLV_API_REGULATORY_NVM_INFO);
1463 size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3);
1464 void *channel_profile;
1465
1466 ret = iwl_trans_send_cmd(trans, &hcmd);
1467 if (ret)
1468 return ERR_PTR(ret);
1469
1470 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size,
1471 "Invalid payload len in NVM response from FW %d",
1472 iwl_rx_packet_payload_len(hcmd.resp_pkt))) {
1473 ret = -EINVAL;
1474 goto out;
1475 }
1476
1477 rsp = (void *)hcmd.resp_pkt->data;
1478 empty_otp = !!(le32_to_cpu(rsp->general.flags) &
1479 NVM_GENERAL_FLAGS_EMPTY_OTP);
1480 if (empty_otp)
1481 IWL_INFO(trans, "OTP is empty\n");
1482
1483 nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL);
1484 if (!nvm) {
1485 ret = -ENOMEM;
1486 goto out;
1487 }
1488
1489 iwl_set_hw_address_from_csr(trans, nvm);
1490 /* TODO: if platform NVM has MAC address - override it here */
1491
1492 if (!is_valid_ether_addr(nvm->hw_addr)) {
1493 IWL_ERR(trans, "no valid mac address was found\n");
1494 ret = -EINVAL;
1495 goto err_free;
1496 }
1497
1498 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr);
1499
1500 /* Initialize general data */
1501 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version);
1502 nvm->n_hw_addrs = rsp->general.n_hw_addrs;
1503 if (nvm->n_hw_addrs == 0)
1504 IWL_WARN(trans,
1505 "Firmware declares no reserved mac addresses. OTP is empty: %d\n",
1506 empty_otp);
1507
1508 /* Initialize MAC sku data */
1509 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags);
1510 nvm->sku_cap_11ac_enable =
1511 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED);
1512 nvm->sku_cap_11n_enable =
1513 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED);
1514 nvm->sku_cap_11ax_enable =
1515 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED);
1516 nvm->sku_cap_band_24ghz_enable =
1517 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED);
1518 nvm->sku_cap_band_52ghz_enable =
1519 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED);
1520 nvm->sku_cap_mimo_disabled =
1521 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED);
1522
1523 /* Initialize PHY sku data */
1524 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains);
1525 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains);
1526
1527 if (le32_to_cpu(rsp->regulatory.lar_enabled) &&
1528 fw_has_capa(&fw->ucode_capa,
1529 IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) {
1530 nvm->lar_enabled = true;
1531 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1532 }
1533
1534 rsp_v3 = (void *)rsp;
1535 channel_profile = v4 ? (void *)rsp->regulatory.channel_profile :
1536 (void *)rsp_v3->regulatory.channel_profile;
1537
1538 iwl_init_sbands(trans, nvm,
1539 channel_profile,
1540 nvm->valid_tx_ant & fw->valid_tx_ant,
1541 nvm->valid_rx_ant & fw->valid_rx_ant,
1542 sbands_flags, v4);
1543
1544 iwl_free_resp(&hcmd);
1545 return nvm;
1546
1547 err_free:
1548 kfree(nvm);
1549 out:
1550 iwl_free_resp(&hcmd);
1551 return ERR_PTR(ret);
1552 }
1553 IWL_EXPORT_SYMBOL(iwl_get_nvm);
Linux with added FPC-III support