drivers/net/wireless/realtek/rtw88/pci.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2 /* Copyright(c) 2018-2019  Realtek Corporation
   3  */
   4
   5 #ifndef __RTK_PCI_H_
   6 #define __RTK_PCI_H_
   7
   8 #define RTK_PCI_DEVICE(vend, dev, hw_config)    \
   9         PCI_DEVICE(vend, dev),                  \
  10         .driver_data = (kernel_ulong_t)&(hw_config),
  11
  12 #define RTK_DEFAULT_TX_DESC_NUM 128
  13 #define RTK_BEQ_TX_DESC_NUM     256
  14
  15 #define RTK_MAX_RX_DESC_NUM     512
  16 /* 8K + rx desc size */
  17 #define RTK_PCI_RX_BUF_SIZE     (8192 + 24)
  18
  19 #define RTK_PCI_CTRL            0x300
  20 #define BIT_RST_TRXDMA_INTF     BIT(20)
  21 #define BIT_RX_TAG_EN           BIT(15)
  22 #define REG_DBI_WDATA_V1        0x03E8
  23 #define REG_DBI_RDATA_V1        0x03EC
  24 #define REG_DBI_FLAG_V1         0x03F0
  25 #define BIT_DBI_RFLAG           BIT(17)
  26 #define BIT_DBI_WFLAG           BIT(16)
  27 #define BITS_DBI_WREN           GENMASK(15, 12)
  28 #define BITS_DBI_ADDR_MASK      GENMASK(11, 2)
  29
  30 #define REG_MDIO_V1             0x03F4
  31 #define REG_PCIE_MIX_CFG        0x03F8
  32 #define BITS_MDIO_ADDR_MASK     GENMASK(4, 0)
  33 #define BIT_MDIO_WFLAG_V1       BIT(5)
  34 #define RTW_PCI_MDIO_PG_SZ      BIT(5)
  35 #define RTW_PCI_MDIO_PG_OFFS_G1 0
  36 #define RTW_PCI_MDIO_PG_OFFS_G2 2
  37 #define RTW_PCI_WR_RETRY_CNT    20
  38
  39 #define RTK_PCIE_LINK_CFG       0x0719
  40 #define BIT_CLKREQ_SW_EN        BIT(4)
  41 #define BIT_L1_SW_EN            BIT(3)
  42 #define RTK_PCIE_CLKDLY_CTRL    0x0725
  43
  44 #define BIT_PCI_BCNQ_FLAG       BIT(4)
  45 #define RTK_PCI_TXBD_DESA_BCNQ  0x308
  46 #define RTK_PCI_TXBD_DESA_H2CQ  0x1320
  47 #define RTK_PCI_TXBD_DESA_MGMTQ 0x310
  48 #define RTK_PCI_TXBD_DESA_BKQ   0x330
  49 #define RTK_PCI_TXBD_DESA_BEQ   0x328
  50 #define RTK_PCI_TXBD_DESA_VIQ   0x320
  51 #define RTK_PCI_TXBD_DESA_VOQ   0x318
  52 #define RTK_PCI_TXBD_DESA_HI0Q  0x340
  53 #define RTK_PCI_RXBD_DESA_MPDUQ 0x338
  54
  55 #define TRX_BD_IDX_MASK         GENMASK(11, 0)
  56
  57 /* BCNQ is specialized for rsvd page, does not need to specify a number */
  58 #define RTK_PCI_TXBD_NUM_H2CQ   0x1328
  59 #define RTK_PCI_TXBD_NUM_MGMTQ  0x380
  60 #define RTK_PCI_TXBD_NUM_BKQ    0x38A
  61 #define RTK_PCI_TXBD_NUM_BEQ    0x388
  62 #define RTK_PCI_TXBD_NUM_VIQ    0x386
  63 #define RTK_PCI_TXBD_NUM_VOQ    0x384
  64 #define RTK_PCI_TXBD_NUM_HI0Q   0x38C
  65 #define RTK_PCI_RXBD_NUM_MPDUQ  0x382
  66 #define RTK_PCI_TXBD_IDX_H2CQ   0x132C
  67 #define RTK_PCI_TXBD_IDX_MGMTQ  0x3B0
  68 #define RTK_PCI_TXBD_IDX_BKQ    0x3AC
  69 #define RTK_PCI_TXBD_IDX_BEQ    0x3A8
  70 #define RTK_PCI_TXBD_IDX_VIQ    0x3A4
  71 #define RTK_PCI_TXBD_IDX_VOQ    0x3A0
  72 #define RTK_PCI_TXBD_IDX_HI0Q   0x3B8
  73 #define RTK_PCI_RXBD_IDX_MPDUQ  0x3B4
  74
  75 #define RTK_PCI_TXBD_RWPTR_CLR  0x39C
  76 #define RTK_PCI_TXBD_H2CQ_CSR   0x1330
  77
  78 #define BIT_CLR_H2CQ_HOST_IDX   BIT(16)
  79 #define BIT_CLR_H2CQ_HW_IDX     BIT(8)
  80
  81 #define RTK_PCI_HIMR0           0x0B0
  82 #define RTK_PCI_HISR0           0x0B4
  83 #define RTK_PCI_HIMR1           0x0B8
  84 #define RTK_PCI_HISR1           0x0BC
  85 #define RTK_PCI_HIMR2           0x10B0
  86 #define RTK_PCI_HISR2           0x10B4
  87 #define RTK_PCI_HIMR3           0x10B8
  88 #define RTK_PCI_HISR3           0x10BC
  89 /* IMR 0 */
  90 #define IMR_TIMER2              BIT(31)
  91 #define IMR_TIMER1              BIT(30)
  92 #define IMR_PSTIMEOUT           BIT(29)
  93 #define IMR_GTINT4              BIT(28)
  94 #define IMR_GTINT3              BIT(27)
  95 #define IMR_TBDER               BIT(26)
  96 #define IMR_TBDOK               BIT(25)
  97 #define IMR_TSF_BIT32_TOGGLE    BIT(24)
  98 #define IMR_BCNDMAINT0          BIT(20)
  99 #define IMR_BCNDOK0             BIT(16)
 100 #define IMR_HSISR_IND_ON_INT    BIT(15)
 101 #define IMR_BCNDMAINT_E         BIT(14)
 102 #define IMR_ATIMEND             BIT(12)
 103 #define IMR_HISR1_IND_INT       BIT(11)
 104 #define IMR_C2HCMD              BIT(10)
 105 #define IMR_CPWM2               BIT(9)
 106 #define IMR_CPWM                BIT(8)
 107 #define IMR_HIGHDOK             BIT(7)
 108 #define IMR_MGNTDOK             BIT(6)
 109 #define IMR_BKDOK               BIT(5)
 110 #define IMR_BEDOK               BIT(4)
 111 #define IMR_VIDOK               BIT(3)
 112 #define IMR_VODOK               BIT(2)
 113 #define IMR_RDU                 BIT(1)
 114 #define IMR_ROK                 BIT(0)
 115 /* IMR 1 */
 116 #define IMR_TXFIFO_TH_INT       BIT(30)
 117 #define IMR_BTON_STS_UPDATE     BIT(29)
 118 #define IMR_MCUERR              BIT(28)
 119 #define IMR_BCNDMAINT7          BIT(27)
 120 #define IMR_BCNDMAINT6          BIT(26)
 121 #define IMR_BCNDMAINT5          BIT(25)
 122 #define IMR_BCNDMAINT4          BIT(24)
 123 #define IMR_BCNDMAINT3          BIT(23)
 124 #define IMR_BCNDMAINT2          BIT(22)
 125 #define IMR_BCNDMAINT1          BIT(21)
 126 #define IMR_BCNDOK7             BIT(20)
 127 #define IMR_BCNDOK6             BIT(19)
 128 #define IMR_BCNDOK5             BIT(18)
 129 #define IMR_BCNDOK4             BIT(17)
 130 #define IMR_BCNDOK3             BIT(16)
 131 #define IMR_BCNDOK2             BIT(15)
 132 #define IMR_BCNDOK1             BIT(14)
 133 #define IMR_ATIMEND_E           BIT(13)
 134 #define IMR_ATIMEND             BIT(12)
 135 #define IMR_TXERR               BIT(11)
 136 #define IMR_RXERR               BIT(10)
 137 #define IMR_TXFOVW              BIT(9)
 138 #define IMR_RXFOVW              BIT(8)
 139 #define IMR_CPU_MGQ_TXDONE      BIT(5)
 140 #define IMR_PS_TIMER_C          BIT(4)
 141 #define IMR_PS_TIMER_B          BIT(3)
 142 #define IMR_PS_TIMER_A          BIT(2)
 143 #define IMR_CPUMGQ_TX_TIMER     BIT(1)
 144 /* IMR 3 */
 145 #define IMR_H2CDOK              BIT(16)
 146
 147 /* one element is reserved to know if the ring is closed */
 148 static inline int avail_desc(u32 wp, u32 rp, u32 len)
 149 {
 150         if (rp > wp)
 151                 return rp - wp - 1;
 152         else
 153                 return len - wp + rp - 1;
 154 }
 155
 156 #define RTK_PCI_TXBD_OWN_OFFSET 15
 157 #define RTK_PCI_TXBD_BCN_WORK   0x383
 158
 159 struct rtw_pci_tx_buffer_desc {
 160         __le16 buf_size;
 161         __le16 psb_len;
 162         __le32 dma;
 163 };
 164
 165 struct rtw_pci_tx_data {
 166         dma_addr_t dma;
 167         u8 sn;
 168 };
 169
 170 struct rtw_pci_ring {
 171         u8 *head;
 172         dma_addr_t dma;
 173
 174         u8 desc_size;
 175
 176         u32 len;
 177         u32 wp;
 178         u32 rp;
 179 };
 180
 181 struct rtw_pci_tx_ring {
 182         struct rtw_pci_ring r;
 183         struct sk_buff_head queue;
 184         bool queue_stopped;
 185 };
 186
 187 struct rtw_pci_rx_buffer_desc {
 188         __le16 buf_size;
 189         __le16 total_pkt_size;
 190         __le32 dma;
 191 };
 192
 193 struct rtw_pci_rx_ring {
 194         struct rtw_pci_ring r;
 195         struct sk_buff *buf[RTK_MAX_RX_DESC_NUM];
 196 };
 197
 198 #define RX_TAG_MAX      8192
 199
 200 struct rtw_pci {
 201         struct pci_dev *pdev;
 202
 203         /* Used for PCI interrupt. */
 204         spinlock_t hwirq_lock;
 205         /* Used for PCI TX queueing. */
 206         spinlock_t irq_lock;
 207         u32 irq_mask[4];
 208         bool irq_enabled;
 209
 210         u16 rx_tag;
 211         DECLARE_BITMAP(tx_queued, RTK_MAX_TX_QUEUE_NUM);
 212         struct rtw_pci_tx_ring tx_rings[RTK_MAX_TX_QUEUE_NUM];
 213         struct rtw_pci_rx_ring rx_rings[RTK_MAX_RX_QUEUE_NUM];
 214         u16 link_ctrl;
 215
 216         void __iomem *mmap;
 217 };
 218
 219 static inline u32 max_num_of_tx_queue(u8 queue)
 220 {
 221         u32 max_num;
 222
 223         switch (queue) {
 224         case RTW_TX_QUEUE_BE:
 225                 max_num = RTK_BEQ_TX_DESC_NUM;
 226                 break;
 227         case RTW_TX_QUEUE_BCN:
 228                 max_num = 1;
 229                 break;
 230         default:
 231                 max_num = RTK_DEFAULT_TX_DESC_NUM;
 232                 break;
 233         }
 234
 235         return max_num;
 236 }
 237
 238 static inline struct
 239 rtw_pci_tx_data *rtw_pci_get_tx_data(struct sk_buff *skb)
 240 {
 241         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 242
 243         BUILD_BUG_ON(sizeof(struct rtw_pci_tx_data) >
 244                      sizeof(info->status.status_driver_data));
 245
 246         return (struct rtw_pci_tx_data *)info->status.status_driver_data;
 247 }
 248
 249 static inline
 250 struct rtw_pci_tx_buffer_desc *get_tx_buffer_desc(struct rtw_pci_tx_ring *ring,
 251                                                   u32 size)
 252 {
 253         u8 *buf_desc;
 254
 255         buf_desc = ring->r.head + ring->r.wp * size;
 256         return (struct rtw_pci_tx_buffer_desc *)buf_desc;
 257 }
 258
 259 #endif