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gpio: rcar: Fix runtime PM imbalance on error
[linux/fpc-iii.git] / drivers / pinctrl / qcom / pinctrl-sc7180.c
blob1b6465a882f216bc26959ef3d4209842b8047d50
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2019, The Linux Foundation. All rights reserved.
3
4 #include <linux/module.h>
5 #include <linux/of.h>
6 #include <linux/platform_device.h>
7 #include <linux/pinctrl/pinctrl.h>
8
9 #include "pinctrl-msm.h"
10
11 static const char * const sc7180_tiles[] = {
12 "north",
13 "south",
14 "west",
15 };
16
17 enum {
18 NORTH,
19 SOUTH,
20 WEST
21 };
22
23 #define FUNCTION(fname) \
24 [msm_mux_##fname] = { \
25 .name = #fname, \
26 .groups = fname##_groups, \
27 .ngroups = ARRAY_SIZE(fname##_groups), \
28 }
29
30 #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
31 { \
32 .name = "gpio" #id, \
33 .pins = gpio##id##_pins, \
34 .npins = ARRAY_SIZE(gpio##id##_pins), \
35 .funcs = (int[]){ \
36 msm_mux_gpio, /* gpio mode */ \
37 msm_mux_##f1, \
38 msm_mux_##f2, \
39 msm_mux_##f3, \
40 msm_mux_##f4, \
41 msm_mux_##f5, \
42 msm_mux_##f6, \
43 msm_mux_##f7, \
44 msm_mux_##f8, \
45 msm_mux_##f9 \
46 }, \
47 .nfuncs = 10, \
48 .ctl_reg = 0x1000 * id, \
49 .io_reg = 0x1000 * id + 0x4, \
50 .intr_cfg_reg = 0x1000 * id + 0x8, \
51 .intr_status_reg = 0x1000 * id + 0xc, \
52 .intr_target_reg = 0x1000 * id + 0x8, \
53 .tile = _tile, \
54 .mux_bit = 2, \
55 .pull_bit = 0, \
56 .drv_bit = 6, \
57 .oe_bit = 9, \
58 .in_bit = 0, \
59 .out_bit = 1, \
60 .intr_enable_bit = 0, \
61 .intr_status_bit = 0, \
62 .intr_target_bit = 5, \
63 .intr_target_kpss_val = 3, \
64 .intr_raw_status_bit = 4, \
65 .intr_polarity_bit = 1, \
66 .intr_detection_bit = 2, \
67 .intr_detection_width = 2, \
68 }
69
70 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
71 { \
72 .name = #pg_name, \
73 .pins = pg_name##_pins, \
74 .npins = ARRAY_SIZE(pg_name##_pins), \
75 .ctl_reg = ctl, \
76 .io_reg = 0, \
77 .intr_cfg_reg = 0, \
78 .intr_status_reg = 0, \
79 .intr_target_reg = 0, \
80 .tile = SOUTH, \
81 .mux_bit = -1, \
82 .pull_bit = pull, \
83 .drv_bit = drv, \
84 .oe_bit = -1, \
85 .in_bit = -1, \
86 .out_bit = -1, \
87 .intr_enable_bit = -1, \
88 .intr_status_bit = -1, \
89 .intr_target_bit = -1, \
90 .intr_raw_status_bit = -1, \
91 .intr_polarity_bit = -1, \
92 .intr_detection_bit = -1, \
93 .intr_detection_width = -1, \
94 }
95
96 #define UFS_RESET(pg_name, offset) \
97 { \
98 .name = #pg_name, \
99 .pins = pg_name##_pins, \
100 .npins = ARRAY_SIZE(pg_name##_pins), \
101 .ctl_reg = offset, \
102 .io_reg = offset + 0x4, \
103 .intr_cfg_reg = 0, \
104 .intr_status_reg = 0, \
105 .intr_target_reg = 0, \
106 .tile = SOUTH, \
107 .mux_bit = -1, \
108 .pull_bit = 3, \
109 .drv_bit = 0, \
110 .oe_bit = -1, \
111 .in_bit = -1, \
112 .out_bit = 0, \
113 .intr_enable_bit = -1, \
114 .intr_status_bit = -1, \
115 .intr_target_bit = -1, \
116 .intr_raw_status_bit = -1, \
117 .intr_polarity_bit = -1, \
118 .intr_detection_bit = -1, \
119 .intr_detection_width = -1, \
120 }
121 static const struct pinctrl_pin_desc sc7180_pins[] = {
122 PINCTRL_PIN(0, "GPIO_0"),
123 PINCTRL_PIN(1, "GPIO_1"),
124 PINCTRL_PIN(2, "GPIO_2"),
125 PINCTRL_PIN(3, "GPIO_3"),
126 PINCTRL_PIN(4, "GPIO_4"),
127 PINCTRL_PIN(5, "GPIO_5"),
128 PINCTRL_PIN(6, "GPIO_6"),
129 PINCTRL_PIN(7, "GPIO_7"),
130 PINCTRL_PIN(8, "GPIO_8"),
131 PINCTRL_PIN(9, "GPIO_9"),
132 PINCTRL_PIN(10, "GPIO_10"),
133 PINCTRL_PIN(11, "GPIO_11"),
134 PINCTRL_PIN(12, "GPIO_12"),
135 PINCTRL_PIN(13, "GPIO_13"),
136 PINCTRL_PIN(14, "GPIO_14"),
137 PINCTRL_PIN(15, "GPIO_15"),
138 PINCTRL_PIN(16, "GPIO_16"),
139 PINCTRL_PIN(17, "GPIO_17"),
140 PINCTRL_PIN(18, "GPIO_18"),
141 PINCTRL_PIN(19, "GPIO_19"),
142 PINCTRL_PIN(20, "GPIO_20"),
143 PINCTRL_PIN(21, "GPIO_21"),
144 PINCTRL_PIN(22, "GPIO_22"),
145 PINCTRL_PIN(23, "GPIO_23"),
146 PINCTRL_PIN(24, "GPIO_24"),
147 PINCTRL_PIN(25, "GPIO_25"),
148 PINCTRL_PIN(26, "GPIO_26"),
149 PINCTRL_PIN(27, "GPIO_27"),
150 PINCTRL_PIN(28, "GPIO_28"),
151 PINCTRL_PIN(29, "GPIO_29"),
152 PINCTRL_PIN(30, "GPIO_30"),
153 PINCTRL_PIN(31, "GPIO_31"),
154 PINCTRL_PIN(32, "GPIO_32"),
155 PINCTRL_PIN(33, "GPIO_33"),
156 PINCTRL_PIN(34, "GPIO_34"),
157 PINCTRL_PIN(35, "GPIO_35"),
158 PINCTRL_PIN(36, "GPIO_36"),
159 PINCTRL_PIN(37, "GPIO_37"),
160 PINCTRL_PIN(38, "GPIO_38"),
161 PINCTRL_PIN(39, "GPIO_39"),
162 PINCTRL_PIN(40, "GPIO_40"),
163 PINCTRL_PIN(41, "GPIO_41"),
164 PINCTRL_PIN(42, "GPIO_42"),
165 PINCTRL_PIN(43, "GPIO_43"),
166 PINCTRL_PIN(44, "GPIO_44"),
167 PINCTRL_PIN(45, "GPIO_45"),
168 PINCTRL_PIN(46, "GPIO_46"),
169 PINCTRL_PIN(47, "GPIO_47"),
170 PINCTRL_PIN(48, "GPIO_48"),
171 PINCTRL_PIN(49, "GPIO_49"),
172 PINCTRL_PIN(50, "GPIO_50"),
173 PINCTRL_PIN(51, "GPIO_51"),
174 PINCTRL_PIN(52, "GPIO_52"),
175 PINCTRL_PIN(53, "GPIO_53"),
176 PINCTRL_PIN(54, "GPIO_54"),
177 PINCTRL_PIN(55, "GPIO_55"),
178 PINCTRL_PIN(56, "GPIO_56"),
179 PINCTRL_PIN(57, "GPIO_57"),
180 PINCTRL_PIN(58, "GPIO_58"),
181 PINCTRL_PIN(59, "GPIO_59"),
182 PINCTRL_PIN(60, "GPIO_60"),
183 PINCTRL_PIN(61, "GPIO_61"),
184 PINCTRL_PIN(62, "GPIO_62"),
185 PINCTRL_PIN(63, "GPIO_63"),
186 PINCTRL_PIN(64, "GPIO_64"),
187 PINCTRL_PIN(65, "GPIO_65"),
188 PINCTRL_PIN(66, "GPIO_66"),
189 PINCTRL_PIN(67, "GPIO_67"),
190 PINCTRL_PIN(68, "GPIO_68"),
191 PINCTRL_PIN(69, "GPIO_69"),
192 PINCTRL_PIN(70, "GPIO_70"),
193 PINCTRL_PIN(71, "GPIO_71"),
194 PINCTRL_PIN(72, "GPIO_72"),
195 PINCTRL_PIN(73, "GPIO_73"),
196 PINCTRL_PIN(74, "GPIO_74"),
197 PINCTRL_PIN(75, "GPIO_75"),
198 PINCTRL_PIN(76, "GPIO_76"),
199 PINCTRL_PIN(77, "GPIO_77"),
200 PINCTRL_PIN(78, "GPIO_78"),
201 PINCTRL_PIN(79, "GPIO_79"),
202 PINCTRL_PIN(80, "GPIO_80"),
203 PINCTRL_PIN(81, "GPIO_81"),
204 PINCTRL_PIN(82, "GPIO_82"),
205 PINCTRL_PIN(83, "GPIO_83"),
206 PINCTRL_PIN(84, "GPIO_84"),
207 PINCTRL_PIN(85, "GPIO_85"),
208 PINCTRL_PIN(86, "GPIO_86"),
209 PINCTRL_PIN(87, "GPIO_87"),
210 PINCTRL_PIN(88, "GPIO_88"),
211 PINCTRL_PIN(89, "GPIO_89"),
212 PINCTRL_PIN(90, "GPIO_90"),
213 PINCTRL_PIN(91, "GPIO_91"),
214 PINCTRL_PIN(92, "GPIO_92"),
215 PINCTRL_PIN(93, "GPIO_93"),
216 PINCTRL_PIN(94, "GPIO_94"),
217 PINCTRL_PIN(95, "GPIO_95"),
218 PINCTRL_PIN(96, "GPIO_96"),
219 PINCTRL_PIN(97, "GPIO_97"),
220 PINCTRL_PIN(98, "GPIO_98"),
221 PINCTRL_PIN(99, "GPIO_99"),
222 PINCTRL_PIN(100, "GPIO_100"),
223 PINCTRL_PIN(101, "GPIO_101"),
224 PINCTRL_PIN(102, "GPIO_102"),
225 PINCTRL_PIN(103, "GPIO_103"),
226 PINCTRL_PIN(104, "GPIO_104"),
227 PINCTRL_PIN(105, "GPIO_105"),
228 PINCTRL_PIN(106, "GPIO_106"),
229 PINCTRL_PIN(107, "GPIO_107"),
230 PINCTRL_PIN(108, "GPIO_108"),
231 PINCTRL_PIN(109, "GPIO_109"),
232 PINCTRL_PIN(110, "GPIO_110"),
233 PINCTRL_PIN(111, "GPIO_111"),
234 PINCTRL_PIN(112, "GPIO_112"),
235 PINCTRL_PIN(113, "GPIO_113"),
236 PINCTRL_PIN(114, "GPIO_114"),
237 PINCTRL_PIN(115, "GPIO_115"),
238 PINCTRL_PIN(116, "GPIO_116"),
239 PINCTRL_PIN(117, "GPIO_117"),
240 PINCTRL_PIN(118, "GPIO_118"),
241 PINCTRL_PIN(119, "UFS_RESET"),
242 PINCTRL_PIN(120, "SDC1_RCLK"),
243 PINCTRL_PIN(121, "SDC1_CLK"),
244 PINCTRL_PIN(122, "SDC1_CMD"),
245 PINCTRL_PIN(123, "SDC1_DATA"),
246 PINCTRL_PIN(124, "SDC2_CLK"),
247 PINCTRL_PIN(125, "SDC2_CMD"),
248 PINCTRL_PIN(126, "SDC2_DATA"),
249 };
250
251 #define DECLARE_MSM_GPIO_PINS(pin) \
252 static const unsigned int gpio##pin##_pins[] = { pin }
253 DECLARE_MSM_GPIO_PINS(0);
254 DECLARE_MSM_GPIO_PINS(1);
255 DECLARE_MSM_GPIO_PINS(2);
256 DECLARE_MSM_GPIO_PINS(3);
257 DECLARE_MSM_GPIO_PINS(4);
258 DECLARE_MSM_GPIO_PINS(5);
259 DECLARE_MSM_GPIO_PINS(6);
260 DECLARE_MSM_GPIO_PINS(7);
261 DECLARE_MSM_GPIO_PINS(8);
262 DECLARE_MSM_GPIO_PINS(9);
263 DECLARE_MSM_GPIO_PINS(10);
264 DECLARE_MSM_GPIO_PINS(11);
265 DECLARE_MSM_GPIO_PINS(12);
266 DECLARE_MSM_GPIO_PINS(13);
267 DECLARE_MSM_GPIO_PINS(14);
268 DECLARE_MSM_GPIO_PINS(15);
269 DECLARE_MSM_GPIO_PINS(16);
270 DECLARE_MSM_GPIO_PINS(17);
271 DECLARE_MSM_GPIO_PINS(18);
272 DECLARE_MSM_GPIO_PINS(19);
273 DECLARE_MSM_GPIO_PINS(20);
274 DECLARE_MSM_GPIO_PINS(21);
275 DECLARE_MSM_GPIO_PINS(22);
276 DECLARE_MSM_GPIO_PINS(23);
277 DECLARE_MSM_GPIO_PINS(24);
278 DECLARE_MSM_GPIO_PINS(25);
279 DECLARE_MSM_GPIO_PINS(26);
280 DECLARE_MSM_GPIO_PINS(27);
281 DECLARE_MSM_GPIO_PINS(28);
282 DECLARE_MSM_GPIO_PINS(29);
283 DECLARE_MSM_GPIO_PINS(30);
284 DECLARE_MSM_GPIO_PINS(31);
285 DECLARE_MSM_GPIO_PINS(32);
286 DECLARE_MSM_GPIO_PINS(33);
287 DECLARE_MSM_GPIO_PINS(34);
288 DECLARE_MSM_GPIO_PINS(35);
289 DECLARE_MSM_GPIO_PINS(36);
290 DECLARE_MSM_GPIO_PINS(37);
291 DECLARE_MSM_GPIO_PINS(38);
292 DECLARE_MSM_GPIO_PINS(39);
293 DECLARE_MSM_GPIO_PINS(40);
294 DECLARE_MSM_GPIO_PINS(41);
295 DECLARE_MSM_GPIO_PINS(42);
296 DECLARE_MSM_GPIO_PINS(43);
297 DECLARE_MSM_GPIO_PINS(44);
298 DECLARE_MSM_GPIO_PINS(45);
299 DECLARE_MSM_GPIO_PINS(46);
300 DECLARE_MSM_GPIO_PINS(47);
301 DECLARE_MSM_GPIO_PINS(48);
302 DECLARE_MSM_GPIO_PINS(49);
303 DECLARE_MSM_GPIO_PINS(50);
304 DECLARE_MSM_GPIO_PINS(51);
305 DECLARE_MSM_GPIO_PINS(52);
306 DECLARE_MSM_GPIO_PINS(53);
307 DECLARE_MSM_GPIO_PINS(54);
308 DECLARE_MSM_GPIO_PINS(55);
309 DECLARE_MSM_GPIO_PINS(56);
310 DECLARE_MSM_GPIO_PINS(57);
311 DECLARE_MSM_GPIO_PINS(58);
312 DECLARE_MSM_GPIO_PINS(59);
313 DECLARE_MSM_GPIO_PINS(60);
314 DECLARE_MSM_GPIO_PINS(61);
315 DECLARE_MSM_GPIO_PINS(62);
316 DECLARE_MSM_GPIO_PINS(63);
317 DECLARE_MSM_GPIO_PINS(64);
318 DECLARE_MSM_GPIO_PINS(65);
319 DECLARE_MSM_GPIO_PINS(66);
320 DECLARE_MSM_GPIO_PINS(67);
321 DECLARE_MSM_GPIO_PINS(68);
322 DECLARE_MSM_GPIO_PINS(69);
323 DECLARE_MSM_GPIO_PINS(70);
324 DECLARE_MSM_GPIO_PINS(71);
325 DECLARE_MSM_GPIO_PINS(72);
326 DECLARE_MSM_GPIO_PINS(73);
327 DECLARE_MSM_GPIO_PINS(74);
328 DECLARE_MSM_GPIO_PINS(75);
329 DECLARE_MSM_GPIO_PINS(76);
330 DECLARE_MSM_GPIO_PINS(77);
331 DECLARE_MSM_GPIO_PINS(78);
332 DECLARE_MSM_GPIO_PINS(79);
333 DECLARE_MSM_GPIO_PINS(80);
334 DECLARE_MSM_GPIO_PINS(81);
335 DECLARE_MSM_GPIO_PINS(82);
336 DECLARE_MSM_GPIO_PINS(83);
337 DECLARE_MSM_GPIO_PINS(84);
338 DECLARE_MSM_GPIO_PINS(85);
339 DECLARE_MSM_GPIO_PINS(86);
340 DECLARE_MSM_GPIO_PINS(87);
341 DECLARE_MSM_GPIO_PINS(88);
342 DECLARE_MSM_GPIO_PINS(89);
343 DECLARE_MSM_GPIO_PINS(90);
344 DECLARE_MSM_GPIO_PINS(91);
345 DECLARE_MSM_GPIO_PINS(92);
346 DECLARE_MSM_GPIO_PINS(93);
347 DECLARE_MSM_GPIO_PINS(94);
348 DECLARE_MSM_GPIO_PINS(95);
349 DECLARE_MSM_GPIO_PINS(96);
350 DECLARE_MSM_GPIO_PINS(97);
351 DECLARE_MSM_GPIO_PINS(98);
352 DECLARE_MSM_GPIO_PINS(99);
353 DECLARE_MSM_GPIO_PINS(100);
354 DECLARE_MSM_GPIO_PINS(101);
355 DECLARE_MSM_GPIO_PINS(102);
356 DECLARE_MSM_GPIO_PINS(103);
357 DECLARE_MSM_GPIO_PINS(104);
358 DECLARE_MSM_GPIO_PINS(105);
359 DECLARE_MSM_GPIO_PINS(106);
360 DECLARE_MSM_GPIO_PINS(107);
361 DECLARE_MSM_GPIO_PINS(108);
362 DECLARE_MSM_GPIO_PINS(109);
363 DECLARE_MSM_GPIO_PINS(110);
364 DECLARE_MSM_GPIO_PINS(111);
365 DECLARE_MSM_GPIO_PINS(112);
366 DECLARE_MSM_GPIO_PINS(113);
367 DECLARE_MSM_GPIO_PINS(114);
368 DECLARE_MSM_GPIO_PINS(115);
369 DECLARE_MSM_GPIO_PINS(116);
370 DECLARE_MSM_GPIO_PINS(117);
371 DECLARE_MSM_GPIO_PINS(118);
372
373 static const unsigned int ufs_reset_pins[] = { 119 };
374 static const unsigned int sdc1_rclk_pins[] = { 120 };
375 static const unsigned int sdc1_clk_pins[] = { 121 };
376 static const unsigned int sdc1_cmd_pins[] = { 122 };
377 static const unsigned int sdc1_data_pins[] = { 123 };
378 static const unsigned int sdc2_clk_pins[] = { 124 };
379 static const unsigned int sdc2_cmd_pins[] = { 125 };
380 static const unsigned int sdc2_data_pins[] = { 126 };
381
382 enum sc7180_functions {
383 msm_mux_adsp_ext,
384 msm_mux_agera_pll,
385 msm_mux_aoss_cti,
386 msm_mux_atest_char,
387 msm_mux_atest_char0,
388 msm_mux_atest_char1,
389 msm_mux_atest_char2,
390 msm_mux_atest_char3,
391 msm_mux_atest_tsens,
392 msm_mux_atest_tsens2,
393 msm_mux_atest_usb1,
394 msm_mux_atest_usb2,
395 msm_mux_atest_usb10,
396 msm_mux_atest_usb11,
397 msm_mux_atest_usb12,
398 msm_mux_atest_usb13,
399 msm_mux_atest_usb20,
400 msm_mux_atest_usb21,
401 msm_mux_atest_usb22,
402 msm_mux_atest_usb23,
403 msm_mux_audio_ref,
404 msm_mux_btfm_slimbus,
405 msm_mux_cam_mclk,
406 msm_mux_cci_async,
407 msm_mux_cci_i2c,
408 msm_mux_cci_timer0,
409 msm_mux_cci_timer1,
410 msm_mux_cci_timer2,
411 msm_mux_cci_timer3,
412 msm_mux_cci_timer4,
413 msm_mux_cri_trng,
414 msm_mux_dbg_out,
415 msm_mux_ddr_bist,
416 msm_mux_ddr_pxi0,
417 msm_mux_ddr_pxi1,
418 msm_mux_ddr_pxi2,
419 msm_mux_ddr_pxi3,
420 msm_mux_dp_hot,
421 msm_mux_edp_lcd,
422 msm_mux_gcc_gp1,
423 msm_mux_gcc_gp2,
424 msm_mux_gcc_gp3,
425 msm_mux_gpio,
426 msm_mux_gp_pdm0,
427 msm_mux_gp_pdm1,
428 msm_mux_gp_pdm2,
429 msm_mux_gps_tx,
430 msm_mux_jitter_bist,
431 msm_mux_ldo_en,
432 msm_mux_ldo_update,
433 msm_mux_lpass_ext,
434 msm_mux_mdp_vsync,
435 msm_mux_mdp_vsync0,
436 msm_mux_mdp_vsync1,
437 msm_mux_mdp_vsync2,
438 msm_mux_mdp_vsync3,
439 msm_mux_mi2s_1,
440 msm_mux_mi2s_0,
441 msm_mux_mi2s_2,
442 msm_mux_mss_lte,
443 msm_mux_m_voc,
444 msm_mux_pa_indicator,
445 msm_mux_phase_flag,
446 msm_mux_PLL_BIST,
447 msm_mux_pll_bypassnl,
448 msm_mux_pll_reset,
449 msm_mux_prng_rosc,
450 msm_mux_qdss,
451 msm_mux_qdss_cti,
452 msm_mux_qlink_enable,
453 msm_mux_qlink_request,
454 msm_mux_qspi_clk,
455 msm_mux_qspi_cs,
456 msm_mux_qspi_data,
457 msm_mux_qup00,
458 msm_mux_qup01,
459 msm_mux_qup02_i2c,
460 msm_mux_qup02_uart,
461 msm_mux_qup03,
462 msm_mux_qup04_i2c,
463 msm_mux_qup04_uart,
464 msm_mux_qup05,
465 msm_mux_qup10,
466 msm_mux_qup11_i2c,
467 msm_mux_qup11_uart,
468 msm_mux_qup12,
469 msm_mux_qup13_i2c,
470 msm_mux_qup13_uart,
471 msm_mux_qup14,
472 msm_mux_qup15,
473 msm_mux_sdc1_tb,
474 msm_mux_sdc2_tb,
475 msm_mux_sd_write,
476 msm_mux_sp_cmu,
477 msm_mux_tgu_ch0,
478 msm_mux_tgu_ch1,
479 msm_mux_tgu_ch2,
480 msm_mux_tgu_ch3,
481 msm_mux_tsense_pwm1,
482 msm_mux_tsense_pwm2,
483 msm_mux_uim1,
484 msm_mux_uim2,
485 msm_mux_uim_batt,
486 msm_mux_usb_phy,
487 msm_mux_vfr_1,
488 msm_mux__V_GPIO,
489 msm_mux__V_PPS_IN,
490 msm_mux__V_PPS_OUT,
491 msm_mux_vsense_trigger,
492 msm_mux_wlan1_adc0,
493 msm_mux_wlan1_adc1,
494 msm_mux_wlan2_adc0,
495 msm_mux_wlan2_adc1,
496 msm_mux__,
497 };
498
499 static const char * const qup01_groups[] = {
500 "gpio0", "gpio1", "gpio2", "gpio3", "gpio12", "gpio94",
501 };
502 static const char * const gpio_groups[] = {
503 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
504 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
505 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
506 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
507 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
508 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
509 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
510 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
511 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
512 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
513 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
514 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
515 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
516 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
517 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
518 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
519 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
520 "gpio117", "gpio118",
521 };
522 static const char * const phase_flag_groups[] = {
523 "gpio0", "gpio1", "gpio2", "gpio8", "gpio9",
524 "gpio11", "gpio12", "gpio17", "gpio18", "gpio19",
525 "gpio20", "gpio25", "gpio26", "gpio27", "gpio28",
526 "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
527 "gpio37", "gpio38", "gpio39", "gpio42", "gpio44",
528 "gpio56", "gpio57", "gpio58", "gpio63", "gpio64",
529 "gpio108", "gpio109",
530 };
531 static const char * const cri_trng_groups[] = {
532 "gpio0", "gpio1", "gpio2",
533 };
534 static const char * const sp_cmu_groups[] = {
535 "gpio3",
536 };
537 static const char * const dbg_out_groups[] = {
538 "gpio3",
539 };
540 static const char * const qdss_cti_groups[] = {
541 "gpio3", "gpio4", "gpio8", "gpio9", "gpio33", "gpio44", "gpio45",
542 "gpio72",
543 };
544 static const char * const sdc1_tb_groups[] = {
545 "gpio4",
546 };
547 static const char * const sdc2_tb_groups[] = {
548 "gpio5",
549 };
550 static const char * const qup11_i2c_groups[] = {
551 "gpio6", "gpio7",
552 };
553 static const char * const qup11_uart_groups[] = {
554 "gpio6", "gpio7",
555 };
556 static const char * const ddr_bist_groups[] = {
557 "gpio7", "gpio8", "gpio9", "gpio10",
558 };
559 static const char * const gp_pdm1_groups[] = {
560 "gpio8", "gpio50",
561 };
562 static const char * const mdp_vsync_groups[] = {
563 "gpio10", "gpio11", "gpio12", "gpio70", "gpio71",
564 };
565 static const char * const edp_lcd_groups[] = {
566 "gpio11",
567 };
568 static const char * const ddr_pxi2_groups[] = {
569 "gpio11", "gpio26",
570 };
571 static const char * const m_voc_groups[] = {
572 "gpio12",
573 };
574 static const char * const wlan2_adc0_groups[] = {
575 "gpio12",
576 };
577 static const char * const atest_usb10_groups[] = {
578 "gpio12",
579 };
580 static const char * const ddr_pxi3_groups[] = {
581 "gpio12", "gpio108",
582 };
583 static const char * const cam_mclk_groups[] = {
584 "gpio13", "gpio14", "gpio15", "gpio16", "gpio23",
585 };
586 static const char * const pll_bypassnl_groups[] = {
587 "gpio13",
588 };
589 static const char * const qdss_groups[] = {
590 "gpio13", "gpio86", "gpio14", "gpio87",
591 "gpio15", "gpio88", "gpio16", "gpio89",
592 "gpio17", "gpio90", "gpio18", "gpio91",
593 "gpio19", "gpio21", "gpio20", "gpio22",
594 "gpio23", "gpio54", "gpio24", "gpio36",
595 "gpio25", "gpio57", "gpio26", "gpio31",
596 "gpio27", "gpio56", "gpio28", "gpio29",
597 "gpio30", "gpio35", "gpio93", "gpio104",
598 "gpio34", "gpio53", "gpio37", "gpio55",
599 };
600 static const char * const pll_reset_groups[] = {
601 "gpio14",
602 };
603 static const char * const qup02_i2c_groups[] = {
604 "gpio15", "gpio16",
605 };
606 static const char * const qup02_uart_groups[] = {
607 "gpio15", "gpio16",
608 };
609 static const char * const cci_i2c_groups[] = {
610 "gpio17", "gpio18", "gpio19", "gpio20", "gpio27", "gpio28",
611 };
612 static const char * const wlan1_adc0_groups[] = {
613 "gpio17",
614 };
615 static const char * const atest_usb12_groups[] = {
616 "gpio17",
617 };
618 static const char * const ddr_pxi1_groups[] = {
619 "gpio17", "gpio44",
620 };
621 static const char * const atest_char_groups[] = {
622 "gpio17",
623 };
624 static const char * const agera_pll_groups[] = {
625 "gpio18",
626 };
627 static const char * const vsense_trigger_groups[] = {
628 "gpio18",
629 };
630 static const char * const ddr_pxi0_groups[] = {
631 "gpio18", "gpio27",
632 };
633 static const char * const atest_char3_groups[] = {
634 "gpio18",
635 };
636 static const char * const atest_char2_groups[] = {
637 "gpio19",
638 };
639 static const char * const atest_char1_groups[] = {
640 "gpio20",
641 };
642 static const char * const cci_timer0_groups[] = {
643 "gpio21",
644 };
645 static const char * const gcc_gp2_groups[] = {
646 "gpio21",
647 };
648 static const char * const atest_char0_groups[] = {
649 "gpio21",
650 };
651 static const char * const cci_timer1_groups[] = {
652 "gpio22",
653 };
654 static const char * const gcc_gp3_groups[] = {
655 "gpio22",
656 };
657 static const char * const cci_timer2_groups[] = {
658 "gpio23",
659 };
660 static const char * const cci_timer3_groups[] = {
661 "gpio24",
662 };
663 static const char * const cci_async_groups[] = {
664 "gpio24", "gpio25", "gpio26",
665 };
666 static const char * const cci_timer4_groups[] = {
667 "gpio25",
668 };
669 static const char * const qup05_groups[] = {
670 "gpio25", "gpio26", "gpio27", "gpio28",
671 };
672 static const char * const atest_tsens_groups[] = {
673 "gpio26",
674 };
675 static const char * const atest_usb11_groups[] = {
676 "gpio26",
677 };
678 static const char * const PLL_BIST_groups[] = {
679 "gpio27",
680 };
681 static const char * const sd_write_groups[] = {
682 "gpio33",
683 };
684 static const char * const qup00_groups[] = {
685 "gpio34", "gpio35", "gpio36", "gpio37",
686 };
687 static const char * const gp_pdm0_groups[] = {
688 "gpio37", "gpio68",
689 };
690 static const char * const qup03_groups[] = {
691 "gpio38", "gpio39", "gpio40", "gpio41",
692 };
693 static const char * const atest_tsens2_groups[] = {
694 "gpio39",
695 };
696 static const char * const wlan2_adc1_groups[] = {
697 "gpio39",
698 };
699 static const char * const atest_usb1_groups[] = {
700 "gpio39",
701 };
702 static const char * const qup12_groups[] = {
703 "gpio42", "gpio43", "gpio44", "gpio45",
704 };
705 static const char * const wlan1_adc1_groups[] = {
706 "gpio44",
707 };
708 static const char * const atest_usb13_groups[] = {
709 "gpio44",
710 };
711 static const char * const qup13_i2c_groups[] = {
712 "gpio46", "gpio47",
713 };
714 static const char * const qup13_uart_groups[] = {
715 "gpio46", "gpio47",
716 };
717 static const char * const gcc_gp1_groups[] = {
718 "gpio48", "gpio56",
719 };
720 static const char * const mi2s_1_groups[] = {
721 "gpio49", "gpio50", "gpio51", "gpio52",
722 };
723 static const char * const btfm_slimbus_groups[] = {
724 "gpio49", "gpio50", "gpio51", "gpio52",
725 };
726 static const char * const atest_usb2_groups[] = {
727 "gpio51",
728 };
729 static const char * const atest_usb23_groups[] = {
730 "gpio52",
731 };
732 static const char * const mi2s_0_groups[] = {
733 "gpio53", "gpio54", "gpio55", "gpio56",
734 };
735 static const char * const qup15_groups[] = {
736 "gpio53", "gpio54", "gpio55", "gpio56",
737 };
738 static const char * const atest_usb22_groups[] = {
739 "gpio53",
740 };
741 static const char * const atest_usb21_groups[] = {
742 "gpio54",
743 };
744 static const char * const atest_usb20_groups[] = {
745 "gpio55",
746 };
747 static const char * const lpass_ext_groups[] = {
748 "gpio57", "gpio58",
749 };
750 static const char * const audio_ref_groups[] = {
751 "gpio57",
752 };
753 static const char * const jitter_bist_groups[] = {
754 "gpio57",
755 };
756 static const char * const gp_pdm2_groups[] = {
757 "gpio57",
758 };
759 static const char * const qup10_groups[] = {
760 "gpio59", "gpio60", "gpio61", "gpio62", "gpio68", "gpio72",
761 };
762 static const char * const tgu_ch3_groups[] = {
763 "gpio62",
764 };
765 static const char * const qspi_clk_groups[] = {
766 "gpio63",
767 };
768 static const char * const mdp_vsync0_groups[] = {
769 "gpio63",
770 };
771 static const char * const mi2s_2_groups[] = {
772 "gpio63", "gpio64", "gpio65", "gpio66",
773 };
774 static const char * const mdp_vsync1_groups[] = {
775 "gpio63",
776 };
777 static const char * const mdp_vsync2_groups[] = {
778 "gpio63",
779 };
780 static const char * const mdp_vsync3_groups[] = {
781 "gpio63",
782 };
783 static const char * const tgu_ch0_groups[] = {
784 "gpio63",
785 };
786 static const char * const qspi_data_groups[] = {
787 "gpio64", "gpio65", "gpio66", "gpio67",
788 };
789 static const char * const tgu_ch1_groups[] = {
790 "gpio64",
791 };
792 static const char * const vfr_1_groups[] = {
793 "gpio65",
794 };
795 static const char * const tgu_ch2_groups[] = {
796 "gpio65",
797 };
798 static const char * const qspi_cs_groups[] = {
799 "gpio68", "gpio72",
800 };
801 static const char * const ldo_en_groups[] = {
802 "gpio70",
803 };
804 static const char * const ldo_update_groups[] = {
805 "gpio71",
806 };
807 static const char * const prng_rosc_groups[] = {
808 "gpio72",
809 };
810 static const char * const uim2_groups[] = {
811 "gpio75", "gpio76", "gpio77", "gpio78",
812 };
813 static const char * const uim1_groups[] = {
814 "gpio79", "gpio80", "gpio81", "gpio82",
815 };
816 static const char * const _V_GPIO_groups[] = {
817 "gpio83", "gpio84", "gpio107",
818 };
819 static const char * const _V_PPS_IN_groups[] = {
820 "gpio83", "gpio84", "gpio107",
821 };
822 static const char * const _V_PPS_OUT_groups[] = {
823 "gpio83", "gpio84", "gpio107",
824 };
825 static const char * const gps_tx_groups[] = {
826 "gpio83", "gpio84", "gpio107", "gpio109",
827 };
828 static const char * const uim_batt_groups[] = {
829 "gpio85",
830 };
831 static const char * const dp_hot_groups[] = {
832 "gpio85", "gpio117",
833 };
834 static const char * const aoss_cti_groups[] = {
835 "gpio85",
836 };
837 static const char * const qup14_groups[] = {
838 "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
839 };
840 static const char * const adsp_ext_groups[] = {
841 "gpio87",
842 };
843 static const char * const tsense_pwm1_groups[] = {
844 "gpio88",
845 };
846 static const char * const tsense_pwm2_groups[] = {
847 "gpio88",
848 };
849 static const char * const qlink_request_groups[] = {
850 "gpio96",
851 };
852 static const char * const qlink_enable_groups[] = {
853 "gpio97",
854 };
855 static const char * const pa_indicator_groups[] = {
856 "gpio99",
857 };
858 static const char * const usb_phy_groups[] = {
859 "gpio104",
860 };
861 static const char * const mss_lte_groups[] = {
862 "gpio108", "gpio109",
863 };
864 static const char * const qup04_i2c_groups[] = {
865 "gpio115", "gpio116",
866 };
867 static const char * const qup04_uart_groups[] = {
868 "gpio115", "gpio116",
869 };
870
871 static const struct msm_function sc7180_functions[] = {
872 FUNCTION(adsp_ext),
873 FUNCTION(agera_pll),
874 FUNCTION(aoss_cti),
875 FUNCTION(atest_char),
876 FUNCTION(atest_char0),
877 FUNCTION(atest_char1),
878 FUNCTION(atest_char2),
879 FUNCTION(atest_char3),
880 FUNCTION(atest_tsens),
881 FUNCTION(atest_tsens2),
882 FUNCTION(atest_usb1),
883 FUNCTION(atest_usb2),
884 FUNCTION(atest_usb10),
885 FUNCTION(atest_usb11),
886 FUNCTION(atest_usb12),
887 FUNCTION(atest_usb13),
888 FUNCTION(atest_usb20),
889 FUNCTION(atest_usb21),
890 FUNCTION(atest_usb22),
891 FUNCTION(atest_usb23),
892 FUNCTION(audio_ref),
893 FUNCTION(btfm_slimbus),
894 FUNCTION(cam_mclk),
895 FUNCTION(cci_async),
896 FUNCTION(cci_i2c),
897 FUNCTION(cci_timer0),
898 FUNCTION(cci_timer1),
899 FUNCTION(cci_timer2),
900 FUNCTION(cci_timer3),
901 FUNCTION(cci_timer4),
902 FUNCTION(cri_trng),
903 FUNCTION(dbg_out),
904 FUNCTION(ddr_bist),
905 FUNCTION(ddr_pxi0),
906 FUNCTION(ddr_pxi1),
907 FUNCTION(ddr_pxi2),
908 FUNCTION(ddr_pxi3),
909 FUNCTION(dp_hot),
910 FUNCTION(edp_lcd),
911 FUNCTION(gcc_gp1),
912 FUNCTION(gcc_gp2),
913 FUNCTION(gcc_gp3),
914 FUNCTION(gpio),
915 FUNCTION(gp_pdm0),
916 FUNCTION(gp_pdm1),
917 FUNCTION(gp_pdm2),
918 FUNCTION(gps_tx),
919 FUNCTION(jitter_bist),
920 FUNCTION(ldo_en),
921 FUNCTION(ldo_update),
922 FUNCTION(lpass_ext),
923 FUNCTION(mdp_vsync),
924 FUNCTION(mdp_vsync0),
925 FUNCTION(mdp_vsync1),
926 FUNCTION(mdp_vsync2),
927 FUNCTION(mdp_vsync3),
928 FUNCTION(mi2s_0),
929 FUNCTION(mi2s_1),
930 FUNCTION(mi2s_2),
931 FUNCTION(mss_lte),
932 FUNCTION(m_voc),
933 FUNCTION(pa_indicator),
934 FUNCTION(phase_flag),
935 FUNCTION(PLL_BIST),
936 FUNCTION(pll_bypassnl),
937 FUNCTION(pll_reset),
938 FUNCTION(prng_rosc),
939 FUNCTION(qdss),
940 FUNCTION(qdss_cti),
941 FUNCTION(qlink_enable),
942 FUNCTION(qlink_request),
943 FUNCTION(qspi_clk),
944 FUNCTION(qspi_cs),
945 FUNCTION(qspi_data),
946 FUNCTION(qup00),
947 FUNCTION(qup01),
948 FUNCTION(qup02_i2c),
949 FUNCTION(qup02_uart),
950 FUNCTION(qup03),
951 FUNCTION(qup04_i2c),
952 FUNCTION(qup04_uart),
953 FUNCTION(qup05),
954 FUNCTION(qup10),
955 FUNCTION(qup11_i2c),
956 FUNCTION(qup11_uart),
957 FUNCTION(qup12),
958 FUNCTION(qup13_i2c),
959 FUNCTION(qup13_uart),
960 FUNCTION(qup14),
961 FUNCTION(qup15),
962 FUNCTION(sdc1_tb),
963 FUNCTION(sdc2_tb),
964 FUNCTION(sd_write),
965 FUNCTION(sp_cmu),
966 FUNCTION(tgu_ch0),
967 FUNCTION(tgu_ch1),
968 FUNCTION(tgu_ch2),
969 FUNCTION(tgu_ch3),
970 FUNCTION(tsense_pwm1),
971 FUNCTION(tsense_pwm2),
972 FUNCTION(uim1),
973 FUNCTION(uim2),
974 FUNCTION(uim_batt),
975 FUNCTION(usb_phy),
976 FUNCTION(vfr_1),
977 FUNCTION(_V_GPIO),
978 FUNCTION(_V_PPS_IN),
979 FUNCTION(_V_PPS_OUT),
980 FUNCTION(vsense_trigger),
981 FUNCTION(wlan1_adc0),
982 FUNCTION(wlan1_adc1),
983 FUNCTION(wlan2_adc0),
984 FUNCTION(wlan2_adc1),
985 };
986
987 /* Every pin is maintained as a single group, and missing or non-existing pin
988 * would be maintained as dummy group to synchronize pin group index with
989 * pin descriptor registered with pinctrl core.
990 * Clients would not be able to request these dummy pin groups.
991 */
992 static const struct msm_pingroup sc7180_groups[] = {
993 [0] = PINGROUP(0, SOUTH, qup01, cri_trng, _, phase_flag, _, _, _, _, _),
994 [1] = PINGROUP(1, SOUTH, qup01, cri_trng, _, phase_flag, _, _, _, _, _),
995 [2] = PINGROUP(2, SOUTH, qup01, cri_trng, _, phase_flag, _, _, _, _, _),
996 [3] = PINGROUP(3, SOUTH, qup01, sp_cmu, dbg_out, qdss_cti, _, _, _, _, _),
997 [4] = PINGROUP(4, NORTH, sdc1_tb, _, qdss_cti, _, _, _, _, _, _),
998 [5] = PINGROUP(5, NORTH, sdc2_tb, _, _, _, _, _, _, _, _),
999 [6] = PINGROUP(6, NORTH, qup11_i2c, qup11_uart, _, _, _, _, _, _, _),
1000 [7] = PINGROUP(7, NORTH, qup11_i2c, qup11_uart, ddr_bist, _, _, _, _, _, _),
1001 [8] = PINGROUP(8, NORTH, gp_pdm1, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _),
1002 [9] = PINGROUP(9, NORTH, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _, _),
1003 [10] = PINGROUP(10, NORTH, mdp_vsync, ddr_bist, _, _, _, _, _, _, _),
1004 [11] = PINGROUP(11, NORTH, mdp_vsync, edp_lcd, _, phase_flag, ddr_pxi2, _, _, _, _),
1005 [12] = PINGROUP(12, SOUTH, mdp_vsync, m_voc, qup01, _, phase_flag, wlan2_adc0, atest_usb10, ddr_pxi3, _),
1006 [13] = PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss, _, _, _, _, _, _),
1007 [14] = PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss, _, _, _, _, _, _),
1008 [15] = PINGROUP(15, SOUTH, cam_mclk, qup02_i2c, qup02_uart, qdss, _, _, _, _, _),
1009 [16] = PINGROUP(16, SOUTH, cam_mclk, qup02_i2c, qup02_uart, qdss, _, _, _, _, _),
1010 [17] = PINGROUP(17, SOUTH, cci_i2c, _, phase_flag, qdss, _, wlan1_adc0, atest_usb12, ddr_pxi1, atest_char),
1011 [18] = PINGROUP(18, SOUTH, cci_i2c, agera_pll, _, phase_flag, qdss, vsense_trigger, ddr_pxi0, atest_char3, _),
1012 [19] = PINGROUP(19, SOUTH, cci_i2c, _, phase_flag, qdss, atest_char2, _, _, _, _),
1013 [20] = PINGROUP(20, SOUTH, cci_i2c, _, phase_flag, qdss, atest_char1, _, _, _, _),
1014 [21] = PINGROUP(21, NORTH, cci_timer0, gcc_gp2, _, qdss, atest_char0, _, _, _, _),
1015 [22] = PINGROUP(22, NORTH, cci_timer1, gcc_gp3, _, qdss, _, _, _, _, _),
1016 [23] = PINGROUP(23, SOUTH, cci_timer2, cam_mclk, qdss, _, _, _, _, _, _),
1017 [24] = PINGROUP(24, SOUTH, cci_timer3, cci_async, qdss, _, _, _, _, _, _),
1018 [25] = PINGROUP(25, SOUTH, cci_timer4, cci_async, qup05, _, phase_flag, qdss, _, _, _),
1019 [26] = PINGROUP(26, SOUTH, cci_async, qup05, _, phase_flag, qdss, atest_tsens, atest_usb11, ddr_pxi2, _),
1020 [27] = PINGROUP(27, SOUTH, cci_i2c, qup05, PLL_BIST, _, phase_flag, qdss, ddr_pxi0, _, _),
1021 [28] = PINGROUP(28, SOUTH, cci_i2c, qup05, _, phase_flag, qdss, _, _, _, _),
1022 [29] = PINGROUP(29, NORTH, _, qdss, _, _, _, _, _, _, _),
1023 [30] = PINGROUP(30, SOUTH, qdss, _, _, _, _, _, _, _, _),
1024 [31] = PINGROUP(31, NORTH, _, qdss, _, _, _, _, _, _, _),
1025 [32] = PINGROUP(32, NORTH, _, phase_flag, _, _, _, _, _, _, _),
1026 [33] = PINGROUP(33, NORTH, sd_write, _, phase_flag, qdss_cti, _, _, _, _, _),
1027 [34] = PINGROUP(34, SOUTH, qup00, _, phase_flag, qdss, _, _, _, _, _),
1028 [35] = PINGROUP(35, SOUTH, qup00, _, phase_flag, qdss, _, _, _, _, _),
1029 [36] = PINGROUP(36, SOUTH, qup00, _, phase_flag, qdss, _, _, _, _, _),
1030 [37] = PINGROUP(37, SOUTH, qup00, gp_pdm0, _, phase_flag, qdss, _, _, _, _),
1031 [38] = PINGROUP(38, SOUTH, qup03, _, phase_flag, _, _, _, _, _, _),
1032 [39] = PINGROUP(39, SOUTH, qup03, _, phase_flag, atest_tsens2, wlan2_adc1, atest_usb1, _, _, _),
1033 [40] = PINGROUP(40, SOUTH, qup03, _, _, _, _, _, _, _, _),
1034 [41] = PINGROUP(41, SOUTH, qup03, _, _, _, _, _, _, _, _),
1035 [42] = PINGROUP(42, NORTH, qup12, _, phase_flag, _, _, _, _, _, _),
1036 [43] = PINGROUP(43, NORTH, qup12, _, _, _, _, _, _, _, _),
1037 [44] = PINGROUP(44, NORTH, qup12, _, phase_flag, qdss_cti, wlan1_adc1, atest_usb13, ddr_pxi1, _, _),
1038 [45] = PINGROUP(45, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _),
1039 [46] = PINGROUP(46, NORTH, qup13_i2c, qup13_uart, _, _, _, _, _, _, _),
1040 [47] = PINGROUP(47, NORTH, qup13_i2c, qup13_uart, _, _, _, _, _, _, _),
1041 [48] = PINGROUP(48, NORTH, gcc_gp1, _, _, _, _, _, _, _, _),
1042 [49] = PINGROUP(49, WEST, mi2s_1, btfm_slimbus, _, _, _, _, _, _, _),
1043 [50] = PINGROUP(50, WEST, mi2s_1, btfm_slimbus, gp_pdm1, _, _, _, _, _, _),
1044 [51] = PINGROUP(51, WEST, mi2s_1, btfm_slimbus, atest_usb2, _, _, _, _, _, _),
1045 [52] = PINGROUP(52, WEST, mi2s_1, btfm_slimbus, atest_usb23, _, _, _, _, _, _),
1046 [53] = PINGROUP(53, WEST, mi2s_0, qup15, qdss, atest_usb22, _, _, _, _, _),
1047 [54] = PINGROUP(54, WEST, mi2s_0, qup15, qdss, atest_usb21, _, _, _, _, _),
1048 [55] = PINGROUP(55, WEST, mi2s_0, qup15, qdss, atest_usb20, _, _, _, _, _),
1049 [56] = PINGROUP(56, WEST, mi2s_0, qup15, gcc_gp1, _, phase_flag, qdss, _, _, _),
1050 [57] = PINGROUP(57, WEST, lpass_ext, audio_ref, jitter_bist, gp_pdm2, _, phase_flag, qdss, _, _),
1051 [58] = PINGROUP(58, WEST, lpass_ext, _, phase_flag, _, _, _, _, _, _),
1052 [59] = PINGROUP(59, NORTH, qup10, _, _, _, _, _, _, _, _),
1053 [60] = PINGROUP(60, NORTH, qup10, _, _, _, _, _, _, _, _),
1054 [61] = PINGROUP(61, NORTH, qup10, _, _, _, _, _, _, _, _),
1055 [62] = PINGROUP(62, NORTH, qup10, tgu_ch3, _, _, _, _, _, _, _),
1056 [63] = PINGROUP(63, NORTH, qspi_clk, mdp_vsync0, mi2s_2, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, _, phase_flag),
1057 [64] = PINGROUP(64, NORTH, qspi_data, mi2s_2, tgu_ch1, _, phase_flag, _, _, _, _),
1058 [65] = PINGROUP(65, NORTH, qspi_data, mi2s_2, vfr_1, tgu_ch2, _, _, _, _, _),
1059 [66] = PINGROUP(66, NORTH, qspi_data, mi2s_2, _, _, _, _, _, _, _),
1060 [67] = PINGROUP(67, NORTH, qspi_data, _, _, _, _, _, _, _, _),
1061 [68] = PINGROUP(68, NORTH, qspi_cs, qup10, gp_pdm0, _, _, _, _, _, _),
1062 [69] = PINGROUP(69, WEST, _, _, _, _, _, _, _, _, _),
1063 [70] = PINGROUP(70, NORTH, _, _, mdp_vsync, ldo_en, _, _, _, _, _),
1064 [71] = PINGROUP(71, NORTH, _, mdp_vsync, ldo_update, _, _, _, _, _, _),
1065 [72] = PINGROUP(72, NORTH, qspi_cs, qup10, prng_rosc, _, qdss_cti, _, _, _, _),
1066 [73] = PINGROUP(73, WEST, _, _, _, _, _, _, _, _, _),
1067 [74] = PINGROUP(74, WEST, _, _, _, _, _, _, _, _, _),
1068 [75] = PINGROUP(75, WEST, uim2, _, _, _, _, _, _, _, _),
1069 [76] = PINGROUP(76, WEST, uim2, _, _, _, _, _, _, _, _),
1070 [77] = PINGROUP(77, WEST, uim2, _, _, _, _, _, _, _, _),
1071 [78] = PINGROUP(78, WEST, uim2, _, _, _, _, _, _, _, _),
1072 [79] = PINGROUP(79, WEST, uim1, _, _, _, _, _, _, _, _),
1073 [80] = PINGROUP(80, WEST, uim1, _, _, _, _, _, _, _, _),
1074 [81] = PINGROUP(81, WEST, uim1, _, _, _, _, _, _, _, _),
1075 [82] = PINGROUP(82, WEST, uim1, _, _, _, _, _, _, _, _),
1076 [83] = PINGROUP(83, WEST, _, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, gps_tx, _, _, _, _),
1077 [84] = PINGROUP(84, WEST, _, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, gps_tx, _, _, _, _),
1078 [85] = PINGROUP(85, WEST, uim_batt, dp_hot, aoss_cti, _, _, _, _, _, _),
1079 [86] = PINGROUP(86, NORTH, qup14, qdss, _, _, _, _, _, _, _),
1080 [87] = PINGROUP(87, NORTH, qup14, adsp_ext, qdss, _, _, _, _, _, _),
1081 [88] = PINGROUP(88, NORTH, qup14, qdss, tsense_pwm1, tsense_pwm2, _, _, _, _, _),
1082 [89] = PINGROUP(89, NORTH, qup14, qdss, _, _, _, _, _, _, _),
1083 [90] = PINGROUP(90, NORTH, qup14, qdss, _, _, _, _, _, _, _),
1084 [91] = PINGROUP(91, NORTH, qup14, qdss, _, _, _, _, _, _, _),
1085 [92] = PINGROUP(92, NORTH, _, _, _, _, _, _, _, _, _),
1086 [93] = PINGROUP(93, NORTH, qdss, _, _, _, _, _, _, _, _),
1087 [94] = PINGROUP(94, SOUTH, qup01, _, _, _, _, _, _, _, _),
1088 [95] = PINGROUP(95, WEST, _, _, _, _, _, _, _, _, _),
1089 [96] = PINGROUP(96, WEST, qlink_request, _, _, _, _, _, _, _, _),
1090 [97] = PINGROUP(97, WEST, qlink_enable, _, _, _, _, _, _, _, _),
1091 [98] = PINGROUP(98, WEST, _, _, _, _, _, _, _, _, _),
1092 [99] = PINGROUP(99, WEST, _, pa_indicator, _, _, _, _, _, _, _),
1093 [100] = PINGROUP(100, WEST, _, _, _, _, _, _, _, _, _),
1094 [101] = PINGROUP(101, NORTH, _, _, _, _, _, _, _, _, _),
1095 [102] = PINGROUP(102, NORTH, _, _, _, _, _, _, _, _, _),
1096 [103] = PINGROUP(103, NORTH, _, _, _, _, _, _, _, _, _),
1097 [104] = PINGROUP(104, WEST, usb_phy, _, qdss, _, _, _, _, _, _),
1098 [105] = PINGROUP(105, NORTH, _, _, _, _, _, _, _, _, _),
1099 [106] = PINGROUP(106, NORTH, _, _, _, _, _, _, _, _, _),
1100 [107] = PINGROUP(107, WEST, _, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, gps_tx, _, _, _, _),
1101 [108] = PINGROUP(108, SOUTH, mss_lte, _, phase_flag, ddr_pxi3, _, _, _, _, _),
1102 [109] = PINGROUP(109, SOUTH, mss_lte, gps_tx, _, phase_flag, _, _, _, _, _),
1103 [110] = PINGROUP(110, NORTH, _, _, _, _, _, _, _, _, _),
1104 [111] = PINGROUP(111, NORTH, _, _, _, _, _, _, _, _, _),
1105 [112] = PINGROUP(112, NORTH, _, _, _, _, _, _, _, _, _),
1106 [113] = PINGROUP(113, NORTH, _, _, _, _, _, _, _, _, _),
1107 [114] = PINGROUP(114, NORTH, _, _, _, _, _, _, _, _, _),
1108 [115] = PINGROUP(115, WEST, qup04_i2c, qup04_uart, _, _, _, _, _, _, _),
1109 [116] = PINGROUP(116, WEST, qup04_i2c, qup04_uart, _, _, _, _, _, _, _),
1110 [117] = PINGROUP(117, WEST, dp_hot, _, _, _, _, _, _, _, _),
1111 [118] = PINGROUP(118, WEST, _, _, _, _, _, _, _, _, _),
1112 [119] = UFS_RESET(ufs_reset, 0x7f000),
1113 [120] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x7a000, 15, 0),
1114 [121] = SDC_QDSD_PINGROUP(sdc1_clk, 0x7a000, 13, 6),
1115 [122] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x7a000, 11, 3),
1116 [123] = SDC_QDSD_PINGROUP(sdc1_data, 0x7a000, 9, 0),
1117 [124] = SDC_QDSD_PINGROUP(sdc2_clk, 0x7b000, 14, 6),
1118 [125] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x7b000, 11, 3),
1119 [126] = SDC_QDSD_PINGROUP(sdc2_data, 0x7b000, 9, 0),
1120 };
1121
1122 static const struct msm_gpio_wakeirq_map sc7180_pdc_map[] = {
1123 {0, 40}, {3, 50}, {4, 42}, {5, 70}, {6, 41}, {9, 35},
1124 {10, 80}, {11, 51}, {16, 20}, {21, 55}, {22, 90}, {23, 21},
1125 {24, 61}, {26, 52}, {28, 36}, {30, 100}, {31, 33}, {32, 81},
1126 {33, 62}, {34, 43}, {36, 91}, {37, 53}, {38, 63}, {39, 72},
1127 {41, 101}, {42, 7}, {43, 34}, {45, 73}, {47, 82}, {49, 17},
1128 {52, 109}, {53, 102}, {55, 92}, {56, 56}, {57, 57}, {58, 83},
1129 {59, 37}, {62, 110}, {63, 111}, {64, 74}, {65, 44}, {66, 93},
1130 {67, 58}, {68, 112}, {69, 32}, {70, 54}, {72, 59}, {73, 64},
1131 {74, 71}, {78, 31}, {82, 30}, {85, 103}, {86, 38}, {87, 39},
1132 {88, 45}, {89, 46}, {90, 47}, {91, 48}, {92, 60}, {93, 49},
1133 {94, 84}, {95, 94}, {98, 65}, {101, 66}, {104, 67}, {109, 104},
1134 {110, 68}, {113, 69}, {114, 113}, {115, 108}, {116, 121},
1135 {117, 114}, {118, 119},
1136 };
1137
1138 static const struct msm_pinctrl_soc_data sc7180_pinctrl = {
1139 .pins = sc7180_pins,
1140 .npins = ARRAY_SIZE(sc7180_pins),
1141 .functions = sc7180_functions,
1142 .nfunctions = ARRAY_SIZE(sc7180_functions),
1143 .groups = sc7180_groups,
1144 .ngroups = ARRAY_SIZE(sc7180_groups),
1145 .ngpios = 120,
1146 .tiles = sc7180_tiles,
1147 .ntiles = ARRAY_SIZE(sc7180_tiles),
1148 .wakeirq_map = sc7180_pdc_map,
1149 .nwakeirq_map = ARRAY_SIZE(sc7180_pdc_map),
1150 };
1151
1152 static int sc7180_pinctrl_probe(struct platform_device *pdev)
1153 {
1154 return msm_pinctrl_probe(pdev, &sc7180_pinctrl);
1155 }
1156
1157 static const struct of_device_id sc7180_pinctrl_of_match[] = {
1158 { .compatible = "qcom,sc7180-pinctrl", },
1159 { },
1160 };
1161
1162 static struct platform_driver sc7180_pinctrl_driver = {
1163 .driver = {
1164 .name = "sc7180-pinctrl",
1165 .pm = &msm_pinctrl_dev_pm_ops,
1166 .of_match_table = sc7180_pinctrl_of_match,
1167 },
1168 .probe = sc7180_pinctrl_probe,
1169 .remove = msm_pinctrl_remove,
1170 };
1171
1172 static int __init sc7180_pinctrl_init(void)
1173 {
1174 return platform_driver_register(&sc7180_pinctrl_driver);
1175 }
1176 arch_initcall(sc7180_pinctrl_init);
1177
1178 static void __exit sc7180_pinctrl_exit(void)
1179 {
1180 platform_driver_unregister(&sc7180_pinctrl_driver);
1181 }
1182 module_exit(sc7180_pinctrl_exit);
1183
1184 MODULE_DESCRIPTION("QTI sc7180 pinctrl driver");
1185 MODULE_LICENSE("GPL v2");
1186 MODULE_DEVICE_TABLE(of, sc7180_pinctrl_of_match);
Linux with added FPC-III support